®
February 2011
6024 Silver Creek Valley Road, San Jose, California 95138Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.©2011 Integrated Device Technology, Inc.
IDT™ 89EB-LOGAN-19Evaluation Board Manual
(Evaluation Board: 18-692-000)
DISCLAIMERIntegrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a Failure Analysis be performed.
LIFE SUPPORT POLICYIntegrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.
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89EB-LOGAN-19 Evalu
Table of Contents®
Description of the EB-LOGAN-19 Evaluation BoardIntroduction ..................................................................................................................................... 1-1Board Features ............................................................................................................................... 1-2
Hardware ................................................................................................................................ 1-2Software.................................................................................................................................. 1-2Other....................................................................................................................................... 1-2
Revision History .............................................................................................................................. 1-2
Installation of the EB-LOGAN-19 Evaluation BoardEB-LOGAN-19 Installation .............................................................................................................. 2-1PCI Express Mezzanine and Edge Adapters.................................................................................. 2-1Hardware Description ..................................................................................................................... 2-3Reference Clocks............................................................................................................................ 2-4
Global Reference Input Clocks ............................................................................................... 2-4Local Port Input Clocks........................................................................................................... 2-6Power Sources ....................................................................................................................... 2-7PCI Express Analog Power Voltage Regulator....................................................................... 2-8PCI Express Digital Power Voltage Converter........................................................................ 2-8PCI Express Transmitter Analog Voltage Converter .............................................................. 2-8Core Logic Voltage Converter ................................................................................................ 2-83.3V I/O Voltage Regulator.....................................................................................................2-8Power-up Sequence for PES24NT24G2 ................................................................................ 2-8
Heatsink Requirement .................................................................................................................... 2-8Reset............................................................................................................................................... 2-9
Fundamental Reset ................................................................................................................ 2-9Downstream Reset ................................................................................................................. 2-9Stack Configuration ................................................................................................................ 2-9
Boot Configuration Vector............................................................................................................. 2-10SMBus Interfaces.......................................................................................................................... 2-11
SMBus Slave Interface ......................................................................................................... 2-11SMBus Master Interface ....................................................................................................... 2-12
JTAG Header ................................................................................................................................ 2-12PCI Express Connectors............................................................................................................... 2-13EB-LOGAN-19 Board Figure ........................................................................................................ 2-15
Software for the EB-LOGAN-19 Eval BoardIntroduction ..................................................................................................................................... 3-1Device Management Software........................................................................................................ 3-1Device Drivers................................................................................................................................. 3-1
SchematicsSchematics ..................................................................................................................................... 4-1
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89EB-LOGAN-19 Evalu
List of Tables®
Table 2.1 EB-LOGAN-19 Global Clock Select .................................................................................... 2-4Table 2.2 Clock Buffer Input Sources ................................................................................................. 2-5Table 2.3 Global Reference Input Clock Frequency Select ................................................................ 2-5Table 2.4 Onboard Clock Generator Frequency Select ......................................................................2-6Table 2.5 Onboard Reference Clock Generator Access Points ......................................................... 2-6Table 2.6 EB24NT24G2 Port Clock Select .........................................................................................2-6Table 2.7 EB-LOGAN-19 Slot Clock Select ........................................................................................ 2-6Table 2.8 CLKMODE Selection PES24NT24G2 ................................................................................ 2-7Table 2.9 EPS12V 24-pin Power Connector - J6 ............................................................................... 2-7Table 2.10 EPS12V 8-Pin Connector - J5 ............................................................................................ 2-8Table 2.11 Ports in Each Stack .......................................................................................................... 2-10Table 2.12 Boot Configuration Vector Signals .................................................................................... 2-10Table 2.13 Boot Configuration Vector Switches S5, SW8 - SW10 ..................................................... 2-10Table 2.14 Slave SMBus Interface Connector .................................................................................... 2-11Table 2.15 SMBus Slave Interface Address Configuration ................................................................. 2-12Table 2.16 JTAG Connector Pin Out .................................................................................................. 2-12Table 2.17 PCI Express x8 Connector Pinout .................................................................................... 2-13
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89EB-LOGAN-19 Evalu
List of Figures®
Figure 1.1 Function Block Diagram of the EB-LOGAN-19 Evaluation Board ......................................1-1Figure 2.1 Bifurcated and Merged Mezzanine Cards ..........................................................................2-1Figure 2.2 MiniSAS Mezzanine Adapter ............................................................................................2-2Figure 2.3 EB-LOGAN-19 iSAS-to-SATA Breakout Cable ..................................................................2-2Figure 2.4 PCIe x1 Edge-to-SATA Adapter ........................................................................................2-3Figure 2.5 EB-LOGAN-19 Evaluation Main Board ..............................................................................2-3Figure 2.6 12PACK PCIe Slots Breakout Daughter Board .................................................................2-4Figure 2.7 Differential Jumper Arrangement .......................................................................................2-4Figure 2.8 Reference Clock Configuration ..........................................................................................2-5Figure 2.9 EB24NT24G2 Evaluation Board ......................................................................................2-15
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Chapter 1
Description of the EB-LOGAN-19 Evaluation Board
IntroductionThe 89HPES24NT24G2 switch is a member of the IDT PCI Express® Inter-Domain Switch family of
products. It is a PCIe® Base Specification 2.1 compliant (Gen2) 24-lane, 24-port switch. The EB-LOGAN-19 Evaluation Board provides an evaluation platform for the PES24NT24G2 switch and for other members of this switch family including PES16NT16G2 and PES12NT12G2.
Detailed information related to configuration of number of ports and lanes in the switch device can be found in the Device User Manual and the Device Datasheet. The evaluation board, along with additional adapters and daughter boards provided by IDT, can be configured to test every possible combination of the number of lanes and ports offered by the switch. Advanced capabilities such as switch partitioning, NTB, DMA and local port clocking can be evaluated with the evaluation board.
The EB-LOGAN-19 brings out all 24 lanes of the device to two Mezzanine connectors and two SAS connectors (see Figure 1.1) located close to the device - one connector per stack of 4 lanes. Various types of daughter cards (provided by IDT) can then be plugged into the Mezzanine connectors to facilitate connectivity to one x8 or two x4 or four x2 or eight x1 link partners. Link partners may be plugged directly into these daughter cards or they can be connected to these daughter cards via SAS or SATA cables and a different board with PCIe slots known as the 12-PACK board (provided by IDT). Given that majority of the hosts / servers offer PCIe standard slots, IDT provides the necessary adapter cards that may be plugged into these host / server slots as well as the cables that connect such adapters to the daughter cards which in turn are plugged into the main evaluation board on which the IDT PCIe switch device is populated.
The EB-LOGAN-19 is also used by IDT to reproduce system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main parts of the EB-LOGAN-19 board.
Figure 1.1 Function Block Diagram of the EB-LOGAN-19 Evaluation Board
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Board FeaturesHardwarePES24NT24G2 PCIe 24-port switch
– Twenty four ports (each x1) - for port 8 and higher, adjacent ports may be combined to create x2, x4 or x8 ports
– PCIe Base Specification Revision 2.1 compliant (Gen2 SerDes speeds of 5 GT/S)– Up to 2048 byte maximum Payload Size– Automatic lane reversal and polarity inversion supported on all lanes– Automatic per port link width negotiation to x8, x4, x2, x1– Power on reconfiguration via optional serial EEPROM connected to the SMBUS Master interfaceUpstream, Downstream Ports
– The EB-LOGAN-19 has minimum of one port configured as upstream port to be plugged into a host slot through an adaptor and a cable.
– Up to 23 ports can be configured as downstream ports, for PCIe endpoint add-on cards to be plugged in. The slot connectors can be configured to be x1, x2, x4 or x8, but are mechanically open-ended on one side to allow card widths greater than x8 (e.g. x16) to be populated.
– When used in multi-partition mode, the device can be programmed through the serial EEPROM to generate the appropriate number of upstream and downstream ports per partition.
Numerous user selectable configurations set using onboard jumpers and DIP-switches– Source of clock - host clock or onboard clock generator– Two clock rates (100/125 MHz) from an onboard clock generator– Flexible clocking modes
• Common clock • Non-common clock• Local port clocking on ports that support this feature
– Boot mode selectionSMBUS Slave Interface (4 pin header)SMBUS Master Interface connected to the Serial EEPROMs through I/O expanderPush button for Warm Reset Many LEDs to display status, reset, power, hotplug, etc.JTAG connector to the PES24NT24G2 JTAG pins.
SoftwareThere is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES24NT24G2 within host systems running popular operating systems.
Installation programs– Operating Systems Supported: WindowsServer200x, WindowsXP, Vista, LinuxGUI based application for Windows and Linux
– Allows users to view and modify registers in the PES24NT24G2– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
OtherSMBUS cable may be required for certain evaluation exercises.SMA connectors are provided on the EB-LOGAN-19 board for clock outputs.
Revision HistoryApril 13, 2010: Initial publication of evaluation board manual.
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April 23, 2010: Updated Schematics in Chapter 4.February 16, 2011: Changed default settings from Off to On in Tables 2.3 and 2.4.ation Board 1 - 3 February 16, 2011
IDT Description of the EB-LOGAN-19 Evaluation Board
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Chapter 2
Installation of the EB-LOGAN-19 Evaluation Board
EB-LOGAN-19 InstallationThis chapter discusses the steps required to configure and install the EB-LOGAN-19 evaluation board.
All available DIP switches and jumper configurations are explained in detail. The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.3. Make sure that the host system (motherboard with root complex chipset) is powered off.4. Connect the evaluation board to the host system.5. Apply power to the host system.The EB-LOGAN-19 board is typically shipped with all jumpers and switches configured to their default
settings. In most cases, the board does not require further modification or setup however please visit IDT website and fill out the Technical Support Request form at http://www.idt.com/?app=TechSupport for other configurations.
PCI Express Mezzanine and Edge AdaptersThe PCI Express lanes are broken out to four Mezzanine connectors on EB-LOGAN-19 Evaluation
Board. The adapter cards are used to convert Mezzanine connector into PCI Express slot connector(s) or Internal mini SAS (iSAS) connectors or both. A Bifurcated Mezzanine Card has two mechanical x8 PCIe Slots (x4 electrically) while a Merged Mezzanine Card has single x8 PCIe Slot. Pictured in Figure 2.1.
Figure 2.1 Bifurcated and Merged Mezzanine Cards
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Pictured in Figure 2.2 is the mini-SAS Mezzanine card which consists of two iSAS and two SATA connectors. Each iSAS connector supports up to PCI Express x4 width and the SATA connectors are used for clock and reset signals of each x4 or less stack/port. An iSAS-to-SATA breakout cable shown in Figure 2.3 is used connect from iSAS to edge adapter and/or 12PACK.Figure 2.2 MiniSAS Mezzanine Adapter
Figure 2.3 EB-LOGAN-19 iSAS-to-SATA Breakout Cable
The PCI Express Edge to SATA Adapter, pictured in Figure 2.4, can be inserted into any physical PCIe slot on a host system and in combination with mini-SAS Mezzanine Card, such as the one in Figure 2.2, to form a link between evaluation main board and the host system. There are 5 SATA connectors which one connector (J7) is for clock and reset, and the rest supports one PICe lane per SATA connector. The edge adapters can be inserted into a mechanical x1 or greater slot.
SAS (x4) – four SATA (x1) breakout cable
SAS (x4) – four SATA (x1) breakout cable
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Figure 2.4 PCIe x1 Edge-to-SATA Adapter
Hardware DescriptionThe PES24NT24G2 is a 24-lane, 24-port PCI Express® switch. It is a peripheral chip that performs PCI
Express based switching with a feature set optimized for high performance applications such as servers and storage. It provides fan-out and switching functions between a PCI Express upstream port and down-stream ports or peer-to-peer switching between downstream ports. Furthermore, up to eight ports can be configured as NTB ports for multi-root application.
The EB-LOGAN-19 Main Board, shown in Figure 2.5, will support up to 4 PCI Express downstream ports and up to 23 ports when using two 12PACK Daughter Boards.
Basic requirements for the board to run are:– Host system with a PCI Express root complex supporting x1 configuration through a PCI Express
x1 slot.– – x1, x2, x4, or x8 PCI Express Endpoint Cards.
Figure 2.5 EB-LOGAN-19 Evaluation Main Board
Mezz to two x4 slot connectors
x4 iSAS connectors
DUT on bottom side
Mezz to two x4 slot connectors
x4 iSAS connectors
DUT on bottom side
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Figure 2.6 12PACK PCIe Slots Breakout Daughter Board
Reference Clocks
Global Reference Input ClocksThe PES24NT24G2 requires two differential reference clocks. The EB-LOGAN-19 derives these clocks
from SMA connectors (J17, J20, J66, J67), clock buffer (U50), or SATA connectors (J21, J22) as described in Table 2.1 and Figures 2.7 and 2.8.
Figure 2.7 Differential Jumper Arrangement
Global Clock# Jumper Selection
0 J18 [1-3 / 2-4] SMA (J66/J67)[5-7 /6-8] From Clock Buffer U51 (default)[7-9 / 8-10] SATA, J21
1 J19 [1-3 / 2-4] SMA (J17/J20)[5-7 /6-8] From Clock Buffer U51 (default)[7-9 / 8-10] SATA, J22
Table 2.1 EB-LOGAN-19 Global Clock Select
On-BoardClock Gen
1:12Buffer
SATA
SMA
clk[0:11]
8-PIN EPS12V24-PIN ATX
+12+3.3 +12
SLOT
11
x2 Data
SATA
CLK
SATA
SATA
SLOT
10
x4 Data
SATA
CLK
SATA
SATA
SATA
SATA
SLOT
9
x2 Data
SATA
CLK
SATA
SATA
SLOT
8
x8 Data
SATA
CLK
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SLOT
7
x2 Data
SATA
CLK
SATA
SATA
SLOT
6
x4 Data
SATA
CLK
SATA
SATA
SATA
SATA
SLOT
5
x2 Data
SATA
CLK
SATA
SATA
SLOT
4
x8 Data
SATA
CLK
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SLOT
3
x2 Data
SATA
CLK
SATA
SATA
SLOT
2
x4 Data
SATA
CLK
SATA
SATA
SATA
SATA
SLOT
1
x2 Data
SATA
CLK
SATA
SATA
SLOT
0
x8 Data
SATA
CLK
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
On-BoardClock Gen
1:12Buffer
SATA
SMASMA
clk[0:11]
8-PIN EPS12V24-PIN ATX
+12+3.3 +12
SLOT
11
x2 Data
SATA
CLK
SATA
SATA
SLOT
10
x4 Data
SATA
CLK
SATA
SATA
SATA
SATA
SLOT
9
x2 Data
SATA
CLK
SATA
SATA
SLOT
8
x8 Data
SATA
CLK
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SLOT
7
x2 Data
SATA
CLK
SATA
SATA
SLOT
6
x4 Data
SATA
CLK
SATA
SATA
SATA
SATA
SLOT
5
x2 Data
SATA
CLK
SATA
SATA
SLOT
4
x8 Data
SATA
CLK
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SLOT
3
x2 Data
SATA
CLK
SATA
SATA
SLOT
2
x4 Data
SATA
CLK
SATA
SATA
SATA
SATA
SLOT
1
x2 Data
SATA
CLK
SATA
SATA
SLOT
0
x8 Data
SATA
CLK
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
1
3
5
7
9
11
2
4
6
8
10
12
IOA
IOB
IOC
IOD
1
3
5
7
9
11
2
4
6
8
10
12
IOA
IOB
IOC
IOD10-129-11IOD <-> COM
8-107-9IOC <-> COM
4-63-5IOB <-> COM
2-41-3IOA <-> COM
JMP2JMP1CONNECTION
10-129-11IOD <-> COM
8-107-9IOC <-> COM
4-63-5IOB <-> COM
2-41-3IOA <-> COM
JMP2JMP1CONNECTION
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Figure 2.8 Reference Clock Configuration
By default the clock buffer derives its clock from a common source. The common source can be the host system’s reference clock, the onboard clock generator, or SATA connector (J8). See Table 2.2.
.
The frequency of the global reference clock input may be selected by the Clock Frequency Select (GCLKFEL) pin to be either 100 MHz or 125 MHz as described in Table 2.3.
The source for the onboard clock is the ICS841484 clock generator device (U49) connected to a 25MHz oscillator (X1). When using the onboard clock generator, the output frequency is fixed at 100MHz. There-fore, ICS_FS (S10, bit 1) is ON as the default setting. See Table 2.4.
Jumper Selection
J6 [1-3 / 2-4] SMA (J5/J7) [5-7 / 6-8] Onboard Clock Generator (U49)[7-9 / 8-10] SATA (J8) (default)
Table 2.2 Clock Buffer Input Sources
Global Clock Frequency Switch - SW10[2
SW10[2] Clock Frequency
ON 100 MHz (Default)
OFF 125 MHz
Table 2.3 Global Reference Input Clock Frequency Select
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The output of the onboard clock generator is accessible through two yellow colored loop connectors located on the Evaluation Board. See Table 2.5. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive the clock from an external source.
Local Port Input ClocksAssociated with some ports is a port reference clock input (PxCLK). Depending on the port clocking
mode, a differential reference clock is driven into the device on the corresponding PxCLKP and PxCLKN pins. The frequency of a port reference clock input is always 100 MHz. Table 2.6 lists the possible sources for the port reference clock input, and Table 2.7 lists the possible sources for the slot clock input.
Onboard Clock Frequency Switch - S10[1]
S10[1] Clock Frequency
ON 100 MHz (Default)
OFF 125 MHz
Table 2.4 Onboard Clock Generator Frequency Select
Onboard Reference Clock Output (Differential)
J119 Positive Reference Clock
J120 Negative Reference Clock
J121 SATA Reference Clock
Table 2.5 Onboard Reference Clock Generator Access Points
Port # Header Selection
8 J13 [1-3 / 2-4] Onboard Clock Generator (U118)[5-7 / 6-8] Slot Clock Header (J31)[7-9 / 8-10] SATA (J62) (default)
16 J15 [1-3 / 2-4] Onboard Clock Generator (U120)[5-7 / 6-8] Slot Clock Header (J33)[7-9 / 8-10] SATA (J64) (default)
Table 2.6 EB24NT24G2 Port Clock Select
Slot/Port # Header Selection
8 J31 [1-3 / 2-4] Onboard Clock Generator (U118)[3-5 / 4-6] From Clock Buffer (default)[7-9 / 8-10] To P08CLK Clock Header (J13)[9-11 / 8-10] SATA (J35)
Table 2.7 EB-LOGAN-19 Slot Clock Select (Part 1 of 2)
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CLKMODE SelectionAll ports in the PES24NT24G2 device (upstream and downstream) use global clocked mode. The port
clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot configuration vector as shown in Table 2.8. This field determines the initial value of the Slot Clock Configuration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register. The SCLK field controls the advertise-ment of whether or not the port uses the same reference clock source as the link partner. A one in the SCLK field indicates that the port and its link partner use the same reference clock source. This is defined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK field indicates that the port and its link partner do not use the same reference clock source.
Power SourcesPower for the PES24NT24G2 and all downstream ports will be generated from the 12V from an external
power connector. See Table 2.9. A 12V to 3.3V DC-DC converter will be used to provide power to five switching regulators to generate VDDCORE, VDDPEA, VDDPETA, VDDPEHA, and VDDIO voltages. The 3.3V from the DC-DC converter will be used to power the clock buffers and circuitries.
The external power supply connectors are 24-pin (J69) and 8-pin (J68) molex connector as described in Tables 2.9 and 2.10. The +12V3 is used to power PES32NT24AG2 and downstream slots 16 and 20. The +12V2 is used to power downstream slots 8 and 12.
12 J32 [1-3 / 2-4] From Clock Buffer (default)[3-5 / 4-6] SATA (J36)
16 J33 [1-3 / 2-4] Onboard Clock Generator (U120)[3-5 / 4-6] From Clock Buffer (default)[7-9 / 8-10] To P16CLK Clock Header (J15)[9-11 / 8-10] SATA (J37)
20 J34 [1-3 / 2-4] From Clock Buffer (default)[3-5 / 4-6] SATA (J38)
SW10[8]CLKMODE[0]
SW10[7]CLKMODE[1]
Port 0 SCLK
Port[23:1] SCLK
ON ON 0 0
OFF ON 1 0
ON OFF 0 1
OFF OFF 1 1
Table 2.8 CLKMODE Selection PES24NT24G2
Pin Signal Pin Signal
1 +3.3V 13 +3.3V
2 +3.3V 14 -12V
3 GND 15 GND
4 +5V 16 PS_ON
5 GND 17 GND
Table 2.9 EPS12V 24-pin Power Connector - J6 (Part 1 of 2)
Slot/Port # Header Selection
Table 2.7 EB-LOGAN-19 Slot Clock Select (Part 2 of 2)
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The power on switch located at S1 can be used to control the supply power from the external power supply connector. Add a shunt to W27 to enable power on switch.
PCI Express Analog Power Voltage RegulatorA voltage regulator (U65) provides a 2.5V PCI Express analog power voltage (shown as VDDPEHA) to
the PES24NT24G2.
PCI Express Digital Power Voltage ConverterA separate voltage regulator (U62) provides a 1.0V PCI Express analog power voltage (shown as
VDDPEA) to the PES24NT24G2.
PCI Express Transmitter Analog Voltage ConverterA separate voltage regulator (U68) provides a 1.0V PCI Express transmitter analog voltage (shown as
VDDPETA) to the PES24NT24G2.
Core Logic Voltage ConverterA separate voltage regulator (U59) provides the 1.0V core voltage (VDDCORE) to the PES24NT24G2.
3.3V I/O Voltage RegulatorA separate voltage regulator (U56) provides the 3.3V I/O voltage (VDDIO) to the PES24NT24G2.
Power-up Sequence for PES24NT24G2During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There
are no other power-up sequence requirements for the various operating supply voltages.
Heatsink Requirement The EB-LOGAN-19 evaluation board utilizes a heatsink with integrated fan.
6 +5V 18 GND
7 GND 19 GND
8 PWR_OK 20 NC
9 5VSB 21 +5V
10 +12V3 22 +5V
11 +12V3 23 +5V
12 +3.3V 24 GND
Pin Signal Pin Signal
1 GND 5 +12V1
2 GND 6 +12V1
3 GND 7 +12V2
4 GND 8 +12V2
Table 2.10 EPS12V 8-Pin Connector - J5
Pin Signal Pin Signal
Table 2.9 EPS12V 24-pin Power Connector - J6 (Part 2 of 2)
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ResetThe PES24NT24G2 supports two types of reset mechanisms as described in the PCI Express specifica-tion:– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the PES24NT24G2, and the endpoints.
– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to another. Hot Reset may be initiated by software. This is further discussed in the PES24NT24G2 User Manual. The EB-LOGAN-19 evaluation board provides seamless support for Hot Reset.
Fundamental ResetThere are two types of Fundamental Resets which may occur on the EB-LOGAN-19 evaluation board:
– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI Express Reset (PERSTN) input pin of the PES24NT24G2.
– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be initiated by two methods: • Pressing a push-button switch (S3) located on EB-LOGAN-19 board• The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB-LOGAN-19.Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset (PERSTN) input of the PES24NT24G2 while power is on.
Downstream ResetSingle Partition Mode without Hot Plug:When the evaluation board initially powers on is assumes the following:
The switch is configured in single partition mode. Slot 0 is the root port and controls the downstream port resets. Ports 1-23 are downstream ports. Hot Plug is disabled.
The following behavior should be observed: The resets to slots 1-23 should initially be asserted and remain this way until after the fundamental reset is initially de-asserted. The assertion of slot 0 reset should propagate to slots 1-23.
Stack ConfigurationThe PES24NT24G2 contains four stack blocks labeled Stack 0, Stack 1, Stack 2, and Stack 3. Stacks 0
and 1 have four x1 ports each, and stacks 2 and 3 have eight x1 ports each. This provides a total of 24 ports in the device labeled port 0 through port 23. Table 2.11 lists the ports associated with each stack.
Stacks 0 and 1 have non-mergeable x1 ports. Stacks 2 and 3 may be configured as eight x1 ports, four x2 ports, two x4 ports, one x8 port, and any combinations in between. The configuration of each stack is controlled by the Stack Configuration (STK[3:2]CFG) registers. For possible configurations please refer to the device user manual.
ation Board 2 - 9 February 16, 2011
IDT Installation of the EB-LOGAN-19 Evaluation Board
89EB-LOGAN-19 Evalu
Notes
Boot Configuration VectorA boot configuration vector consisting of the signals listed in Table 2.12 is sampled by the
PES24NT24G2 during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential parameters for switch operation and is set using DIP switches S5, SW8, SW9 and SW10 as defined in Table 2.13.
Stack Ports Associated with the Stack
Stack 0 0, 1, 2, 3
Stack 1 4, 5, 6, 7
Stack 2 8, 9, 10, 11, 12, 13, 14, 15
Stack 3 16, 17, 18, 19, 20, 21, 22, 23
Table 2.11 Ports in Each Stack
Signal Description
GCLKFSEL Global Clock Frequency Select. This pin specifies the frequency of the GCLKP and GCLKN signals.. Default: low
CLKMODE[1:0] Clock Mode. These pins specify the clocking mode used by switch ports. See Table 2.8 for a definition of the encoding of these signals. The value of these signals may be overridden by modifying the Port Clocking Mode (PCLKMODE) register.. Default: 0x3
RSTHALT Reset Halt. When this pin is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the quasi-reset state when the RSTHALTbit is cleared in the SWCTL register by an SMBus master. Refer to section Switch Funda-mental Reset on page 3-2 for further details. Default: low
SSMBADDR[2:1] Slave SMBus Address. SMBus address of the switch on the slave SMBus. Default: 0x3
SWMODE[3:0] Switch Mode. These pins specify the switch operating mode. Default: 0x0
STK2CFG[4:0] Stack 2 Configuration. These pins select the configuration of stack 2 during a switch fun-damental reset. Default: 0x1
STK3CFG[4:0] Stack 3 Configuration. These pins select the configuration of stack 3 during a switch fun-damental reset. Default: 0x1
Table 2.12 Boot Configuration Vector Signals
Location Signal Default
S5[1] SWMODE[0] ON
S5[2] SWMODE[1] ON
S5[3] SWMODE[2] ON
S5[4] SWMODE[3] ON
SW8[1] STK2CFG[0] OFF
SW8[2] STK2CFG[1] ON
Table 2.13 Boot Configuration Vector Switches S5, SW8 - SW10 (Part 1 of 2)
ation Board 2 - 10 February 16, 2011
IDT Installation of the EB-LOGAN-19 Evaluation Board
89EB-LOGAN-19 Evalu
Notes
SMBus InterfacesThe System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus signals in the PCI Express connector is optional and may not be present on the host system. The SMBus interface consists of an SMBus clock pin and an SMBus data pin.
The PES24NT24G2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface. The slave SMBus interface allows a SMBus Master device full access to all software-visible regis-ters. The Master SMBus interface provides a connection to the external serial EEPROM used for initializa-tion and the I/O expanders used for hot-plug signals.
SMBus Slave InterfaceOn the PES24NT24G2 board, the slave SMBus interface is accessible through a 4-pin header as
described in Table 2.14. .
For a fixed address, the SMBus address of the PES24NT24G2 slave interface is 0b1110111 by default and is configurable using DIP Switches SW10[5] and SW10[6] as described in Table 2.15.
SW8[3] STK2CFG[2] ON
SW8[4] STK2CFG[3] ON
SW8[5] STK2CFG[4] ON
SW9[1] STK3CFG[0] OFF
SW9[2] STK3CFG[1] ON
SW9[3] STK3CFG[2] ON
SW9[4] STK3CFG[3] ON
SW9[5] STK3CFG[4] ON
SW10[2] GCLKFSEL ON
SW10[4] RSTHALT ON
SW10[5] SSMBADDR[2] OFF
SW10[6] SSMBADDR[1] OFF
SW10[7] CLKMODE[1] OFF
SW10[8] CLKMODE[0] OFF
Slave SMBus Interface Connector J71
Pin Signal
1 SDA
2 GND
3 SCL
4 NC
Table 2.14 Slave SMBus Interface Connector
Location Signal Default
Table 2.13 Boot Configuration Vector Switches S5, SW8 - SW10 (Part 2 of 2)
ation Board 2 - 11 February 16, 2011
IDT Installation of the EB-LOGAN-19 Evaluation Board
89EB-LOGAN-19 Evalu
Notes
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. Initiation of any SMBus transaction other than those listed above produces undefined results. See the SMBus 2.0 specification for a detailed description of the following transactions:
– Byte and Word Write/Read– Block Write/Read
SMBus Master InterfaceConnected to the master SMBus interface are twenty-two 16-bit I/O Expanders (MAX7311AUG) and a
serial EEPROM, U77 (24LC512). The I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B). The lower three bits of the bus address for the I/O Expander 0 through I/O Expander 20 are fixed through the stuffing resistor as 0x20, 0x22, 0x24, 0x26, 0x28, 0x2A, 0x2C, 0x2E, 0x50, 0x52, x54, 0x56, 0x58, 0x5A, 0x5C, 0x5E, 0xB0, 0xA2, 0xA4, 0xA6, 0xA8, and 0xAA, respectively.
Note: Hot-plug is not implemented when the PES24NT24G2 is installed.The seven bits address for the selected EEPROM device is fixed at 0b1010_000 by default.
JTAG HeaderThe EB-LOGAN-19 provides a JTAG connector J73 for access to the PES24NT24G2 JTAG interface.
The connector is a 2.54 x 2.54 mm pitch male 14-pin connector. Refer to Table 2.16 for the JTAG Connector J73 pin out.
Slave Interface Address Configuration
Address Bit Signal
1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 1
4 0
5 1
6 1
7 1
Table 2.15 SMBus Slave Interface Address Configuration
JTAG Connector J73
Pin Signal Direction Pin Signal Direction
1 /TRST - Test reset Input 2 GND —
3 TDI - Test data Input 4 GND —
5 TDO - Test data Output 6 GND —
7 TMS - Test mode select Input 8 GND —
9 TCK - Test clock Input 10 GND —
11 3.3V 12 N/C —
13 GND — 14 3.3V
Table 2.16 JTAG Connector Pin Out
ation Board 2 - 12 February 16, 2011
IDT Installation of the EB-LOGAN-19 Evaluation Board
89EB-LOGAN-19 Evalu
Notes
PCI Express ConnectorsPin Side A Side B
1 +12V 12V power PRSNT1# Hot-Plug presence detect
2 +12V 12V power +12V 12V power
3 RSVD Reserved +12V 12V power
4 GND Ground GND Ground
5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p
6 SMDAT SMBus Data JTAG TDI (Test Data Input)
7 GND Ground JTAG TDO (Test Data Output)
8 +3.3V 3.3V power JTAG TMS (Test Mode Select)
9 JTAG1 TRST# (Test/Reset) resets JTAG i/f
+3.3V 3.3V power
10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power
11 WAKE# Signal for Link reactivation PERST# Fundamental Reset
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ REFCLK Reference clock
14 PETp0 Transmitter differential REFCLK- (differential pair)
15 PETn0 pair, Lane 0 GND Ground
16 GND Ground PERp0 Receiver differential
17 PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0
18 GND Ground GND Ground
19 PETp1 Transmitter differential RSVD Reserved
20 PETn1 pair, Lane 1 GND Ground
21 GND Ground PERp1 Receiver differential
22 GND Ground PERn1 pair, Lane 1
23 PETp2 Transmitter differential GND Ground
24 PETn2 pair, Lane 2 GND Ground
25 GND Ground PERp2 Receiver differential
26 GND Ground PERn2 pair, Lane 2
27 PETp3 Transmitter differential GND Ground
28 PETn3 pair, Lane 3 GND Ground
29 GND Ground PERp3 Receiver differential
30 RSVD Reserved PERn3 pair, Lane 3
31 PRSNT2# Hot-Plug presence detect GND Ground
32 GND Ground RSVD Reserved
33 PETp4 Transmitter differential RSVD Reserved
Table 2.17 PCI Express x8 Connector Pinout (Part 1 of 2)
ation Board 2 - 13 February 16, 2011
IDT Installation of the EB-LOGAN-19 Evaluation Board
89EB-LOGAN-19 Evalu
Notes
34 PETn4 pair, Lane 4 GND Ground35 GND Ground PERp4 Receiver differential
36 GND Ground PERn4 pair, Lane 4
37 PETp5 Transmitter differential GND Ground
38 PETn5 pair, Lane 5 GND Ground
39 GND Ground PERp5 Receiver differential
40 GND Ground PERn5 pair, Lane 5
41 PETp6 Transmitter differential GND Ground
42 PETn6 pair, Lane 6 GND Ground
43 GND Ground PERp6 Receiver differential
44 GND Ground PERn6 pair, Lane 6
45 PETp7 Transmitter differential GND Ground
46 PETn7 pair, Lane 7 GND Ground
47 GND Ground PERp7 Receiver differential
48 PRSNT2# Hot-Plug presence detect PERn7 pair, Lane 7
49 GND Ground GND Ground
Pin Side A Side B
Table 2.17 PCI Express x8 Connector Pinout (Part 2 of 2)
ation Board 2 - 14 February 16, 2011
IDT Installation of the EB-LOGAN-19 Evaluation Board
89EB-LOGAN-19 Evalu
Notes
EB-LOGAN-19 Board FigureFigure 2.9 EB24NT24G2 Evaluation Board
ation Board 2 - 15 February 16, 2011
IDT Installation of the EB-LOGAN-19 Evaluation Board
89EB-LOGAN-19 Evalu
Notes
ation Board 2 - 16 February 16, 2011
Notes
89EB-LOGAN-19 Evaluation Board 3 - 1 Febru
®
Chapter 3
Software for the EB-LOGAN-19 Eval Board
IntroductionThis chapter discusses some of the main features of the available software to give users a better under-
standing of what can be achieved with the EB-LOGAN-19 evaluation board using the device management software.
Device management software and related user documentation are available on a CD which is included in the Evaluation Board Kit. This information is also available on IDT FTP site and also at my.idt.com. For more information, please go to: http://www.idt.com/?app=TechSupport&prodFamily=PCIe%20Switches or email IDT at [email protected].
Device Management SoftwareThe primary use of the Device Management Software package is to enable users of the evaluation
board to access all the registers in the PES24NT24G2 device. This access can be achieved using the PCI Express in-band configuration cycles through the upstream port on the PES24NT24G2 or through the SMBUS salve interface available on the IDT PCIe switch.
This software also enables users to save a snapshot of the current register set into a dump file which can be used for debugging purposes. An export/import facility is also available to create and use “Configu-ration” files which can be used to initialize the switch device with specific values in specific registers.
A conversion utility is also provided to translate a configuration file into an EEPROM programmable data structure. This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES24NT24G2, and then to populate that EEPROM onto the Evaluation Board. It is also possible to program the EEPROM directly on the Evaluation Board using a feature provided by the software package.
The front-end of the Device Management Software is a user-friendly Graphical User Interface which allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for the PES24NT24G2 in the absence of the actual device.
Much of the Device Management Software is written with device-independent and OS-independent code. The software is expected to work on Linux (/sys interface) and MS Windows XP. It may function well on various flavors of MS Windows, but may not be validated on all. The fact that the software is device-inde-pendent assures its scalability to future PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc.
The actual program name of the Device Management Software is “PCIeBrowser” (an executable file under Windows or Linux). Revision 5.0.1 or later is required for devices in the PES24NT24G2 product family family.
Device DriversThe PES24NT24G2 and other members of this switch family offer Non-Transparent Bridging and built-in
DMA capability inside the device. Device drivers are needed to take advantage of these features. Sample code for these drivers is available from IDT for the Linux operating system. Additionally, there a few other software packages available from IDT. These packages are not related to the evaluation board per se, and therefore not listed here. However, several of these packages may prove to be useful for specific device or system functionality. For more information, please go to http://www.idt.com/?app=TechSupport&prod-Family=PCIe%20Switches or email IDT at [email protected].
ary 16, 2011
IDT Software for the EB-LOGAN-19 Eval Board
89EB-LOGAN-19 Evalu
Notes
ation Board 3 - 2 February 16, 2011
Notes
89EB-LOGAN-19 Evaluation Board 4 - 1 Febru
®
Chapter 4
Schematics
Schematics
ary 16, 2011
TITLE PAGE / TABLE OF CONTENTS1.
MEZZANINE CONNECTOR PORTS 16, 20
24NT24AG2 - CLK, CONFIG, GPIO
PORT 8 CLOCK GENERATORPORT 16 CLOCK GENERATOR
POWER REGULATOR - VDDIOPOWER REGULATOR - VDDCOREPOWER REGULATOR - VDDPEAPOWER REGULATOR - VDDPEHAPOWER REGULATOR - VDDPETA
MIN LOAD RESISTORS
LED - PORT STATUS (6 OF 7)LED - PORT STATUS (5 OF 7)LED - PORT STATUS (4 OF 7)LED - PORT STATUS (3 OF 7)LED - PORT STATUS (2 OF 7)LED - PORT STATUS (1 OF 7)DIP SWITCHESRESET, SMBUS, EEPROM, JTAG
22.23.24.25.26.27.
31.32.
28.29.30.
33.34.
36.35.
SLOT RESET SELECT HEADERSPARTITION RESET SELECT HEADERS12PK RIBBON CONNECTORS
41.40.39.3837.
CLOCK SELECTOR - DUT PCLK 0-20, GCLK 1-2
SLOT RESETS AND WAKE PULL-UPSHOT PLUG CONTROL PORTS 16-20HOT PLUG CONTROL PORTS 8-12
24NT24AG2 - SERDES
24NT24AG2 - POWER, GNDIOEXPANDER 0-3IOEXPANDER 4-7IOEXPANDER 8-11IOEXPANDER 12-13IOEXPANDER 16-19IOEXPANDER 20-21
3.
16.15.14.13.12.11.10.
9.
7.
4.
6.
8.
POWER CONNECTORSCLOCK SELECTOR - SLOTS 0-20
CLOCK BUFFER - 1CLOCK
21.20.19.18.17.
SAS CONNECTOR PORTS 0-72.
5.
MEZZANINE CONNECTOR PORTS 8, 12
LED - PORT STATUS (7 OF 7)
Tue Apr 20 12:37:19 2010 SHEET 1 OF 41
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C81C80
C76C73
C71C68
C67C63
B16B17
B13B14
B5B6
B2B3
A8
B11A11A10
A9B10B9B8
A16A17
A13A14
A5A6
A2A3
MTG9MTG8MTG7MTG6
MTG5MTG4MTG3MTG2MTG1
B7
B4
B1
A18
A15
A12
A7
A4
B18
B15
B12
A1
J40
B16B17
B13B14
B5B6
B2B3
A8
B11A11A10
A9B10B9B8
A16A17
A13A14
A5A6
A2A3
MTG9MTG8MTG7MTG6
MTG5MTG4MTG3MTG2MTG1
B7
B4
B1
A18
A15
A12
A7
A4
B18
B15
B12
A1
J39
C32C28
C36C38
C56C50
C58C59 5
5
55
55
555
5
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5
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SAS CONNECTOR PORTS 0-7
0.1UF PE07TN00.1UF PE07TP0
0.1UF PE06TN00.1UF PE06TP0
0.1UF PE05TN00.1UF PE05TP0
0.1UF PE04TN00.1UF PE04TP00.1UF PE00TP0
0.1UF PE00TN0
0.1UF PE01TP00.1UF PE01TN0
0.1UF PE02TP00.1UF PE02TN0
0.1UF PE03TP00.1UF PE03TN0
VERT
PE00RP0PE00RN0
PE01RP0
PE03RN0PE03RP0
PE02RN0PE02RP0
PE01RN0
SMT
PE07RN0PE07RP0
PE06RN0PE06RP0
PE05RN0PE05RP0
PE04RN0PE04RP0
SMTVERT
IDT
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OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
ININ
ININ
IN
ININ
IN
MOLEX_IPASS_36
MTG9MTG8MTG7MTG6
MTG5MTG4MTG3MTG2MTG1
GND12TX3NTX3P
GND11TX2NTX2P
GND10SB6SB2SB1SB0
GND9TX1NTX1PGND8TX0NTX0PGND7
GND6RX3NRX3PGND5RX2NRX2PGND4SB5SB4SB3SB7GND3RX1NRX1PGND2RX0NRX0PGND1
ININ
ININ
ININ
ININ
MOLEX_IPASS_36
MTG9MTG8MTG7MTG6
MTG5MTG4MTG3MTG2MTG1
GND12TX3NTX3P
GND11TX2NTX2P
GND10SB6SB2SB1SB0
GND9TX1NTX1PGND8TX0NTX0PGND7
GND6RX3NRX3PGND5RX2NRX2PGND4SB5SB4SB3SB7GND3RX1NRX1PGND2RX0NRX0PGND1
X4 - STK2CFG1 = 0, STK2CFG0 = 1X8 - STK2CFG1 = 0, STK2CFG0 = 0STK2CFG1 & STK2CFG0 SET BY MEZZ CARDS
Tue Apr 20 12:38:31 2010 SHEET 3 OF 41
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B
R32
R31
J51
W19
W17
W15
W13
W11
V20
V18
V16
V14
V12
U19
U17
U15
U13
U11
T20
T18
T16
T14
T12
R19
R17
R15
R13
R11
P20
P18
P16
P14
P12
N19
N17
N15
N13
N11
M20
M18
M16
M14
M12
L19
L17
L15
L13
L11
K20
K18
K16
K14
K12
J19
J17
J15
J13
J11
H20
H18
H16
H14
H12
G19
G17
G15
G13
G11
F20
F18
F16
F14
F12
E19
E17
E15
E13
E11
D20
D18
D16
D14
D12
C19
C17
C15
C13
C11
B20
B18
B16
B14
B12
A19
A17
A15
A13
A11
J3
R27R28
R30R29
W9
W7
W5
W3
W1
V8
V6
V4
V2
V10U9
U7
U5
U3
U1
T8
T6
T4
T2
T10R9
R7
R5
R3
R1
P8
P6
P4
P2
P10N9
N7
N5
N3
N1
M8
M6
M4
M2
M10L9
L7
L5
L3
L1
K8
K6
K4
K2
K10J9
J7
J5
J3
J1
H8
H6
H4
H2
H10G9
G7
G5
G3
G1
F8
F6
F4
F2
F10E9
E7
E5
E3
E1
D8
D6
D4
D2
D10C9
C7
C5
C3
C1
B8
B6
B4
B2
B10A9
A7
A5
A3
A1
J3
5
5
5
55
5
55
55
5
5
55
55
82937
5
5
5
82937
628
5
628
3316376343839
2020
63438391637
2020
55
55
55
55
55
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3
3
470-1075-600 (1 of 2)
PE13TN0
PE13RP0
PE11RN0
PE11TN0PE11TP0
PE11RP0
PE12TP0PE12TN0
PE12RN0PE12RP0
PE13TP0
PE13RN0
PE14TP0PE14TN0
PE14RP0PE14RN0
M812_ID<2>
P8_PDN
PE15RN0
PE15TP0
PE15RP0
P12_PDN
STK2CFG1
PE15TN0
STK2CFG0
MEZZ_SMBDAT3MEZZ_SMBCLK3SLOT_WAKEN8SLOT_HDR_RSTN8
S8_CLKPS8_CLKN
M812_ID<1>
SLOT_HDR_RSTN12SLOT_WAKEN12
S12_CLKPS12_CLKN
PE08RP0PE08RN0
PE08TP0PE08TN0
PE09RP0PE09RN0
PE09TP0PE09TN0
PE10RP0PE10RN0
PE10TP0PE10TN0
S8_12V
S12_12V
100100
100100
S12_3VAUX
S8_3V
S8_3VAUX
S12_3V470-1075-600 (2 of 2)
1K 1K06
03
MEZZ_SMBDAT3
MEZZ_SMBCLK3
5%06
03
5%
+3V3
MEZZANINE CONNECTOR PORTS 8/12
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ININ
BI
OUT
OUTCommon
Power
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
SignalWafer 9
Wafer 8
Wafer 7
Wafer 6
Wafer 5
V18T18P18M18K18H18F18D18B18A17
C17E17G17J17L17N17R17U17W17
B16D16F16H16K16M16P16T16V16
W15U15R15N15L15J15G15E15C15A15
V20T20P20M20K20H20F20D20B20A19
C19E19G19J19L19N19R19U19W19
B14D14F14H14K14M14P14T14V14
W13U13R13N13L13J13G13E13C13A13
B12D12F12H12K12M12P12T12V12
W11U11R11N11L11J11G11E11C11A11
OUT
ININ
OUTOUT
ININ
OUTOUT
IN
IN
IN
OUTOUT
ININ
OUTOUT
OUT
IN
OUT
ININ
OUTOUT
OUT
OUT
ININ
OUT
OUT
OUT
ININ
INOUT
OUT
IN
OUT
IN
INOUTBIIN
OUT
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
Wafer 4
Wafer 3
Wafer 2
Wafer 1
Wafer 0
V8T8P8M8K8H8F8D8B8A7
C7E7G7J7L7N7R7U7W7
B6D6F6H6K6M6P6T6V6
W5U5R5N5L5J5G5E5C5A5
V10T10P10M10K10H10F10D10B10A9
C9E9G9J9L9N9R9U9W9
B4D4F4H4K4M4P4T4V4
W3U3R3N3L3J3G3E3C3A3
B2D2F2H2K2M2P2T2V2
W1U1R1N1L1J1G1E1C1A1
X4 - STK3CFG1 = 0, STK3CFG0 = 1X8 - STK3CFG1 = 0, STK3CFG0 = 0STK3CFG1 & STK3CFG0 SET BY MEZZ CARDS
Tue Apr 20 12:38:32 2010 SHEET 4 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R43
R42
J52
W19
W17
W15
W13
W11
V20
V18
V16
V14
V12
U19
U17
U15
U13
U11
T20
T18
T16
T14
T12
R19
R17
R15
R13
R11
P20
P18
P16
P14
P12
N19
N17
N15
N13
N11
M20
M18
M16
M14
M12
L19
L17
L15
L13
L11
K20
K18
K16
K14
K12
J19
J17
J15
J13
J11
H20
H18
H16
H14
H12
G19
G17
G15
G13
G11
F20
F18
F16
F14
F12
E19
E17
E15
E13
E11
D20
D18
D16
D14
D12
C19
C17
C15
C13
C11
B20
B18
B16
B14
B12
A19
A17
A15
A13
A11
J4
R38R39
R41R40
W9
W7
W5
W3
W1
V8
V6
V4
V2
V10U9
U7
U5
U3
U1
T8
T6
T4
T2
T10R9
R7
R5
R3
R1
P8
P6
P4
P2
P10N9
N7
N5
N3
N1
M8
M6
M4
M2
M10L9
L7
L5
L3
L1
K8
K6
K4
K2
K10J9
J7
J5
J3
J1
H8
H6
H4
H2
H10G9
G7
G5
G3
G1
F8
F6
F4
F2
F10E9
E7
E5
E3
E1
D8
D6
D4
D2
D10C9
C7
C5
C3
C1
B8
B6
B4
B2
B10A9
A7
A5
A3
A1
J4
55
55
55
55
55
55
82937
55
55
628
82937
55
55
628
4416376343839
2020
1637
2020
6343839
55
55
55
55
55
55
4
4
PE20TN0PE20TP0
PE20RN0PE20RP0
PE21RP0PE21RN0
PE21TP0PE21TN0
PE19TN0PE19TP0
PE19RN0PE19RP0
M1620_ID<2>
P16_PDN
PE22RP0PE22RN0
PE22TP0PE22TN0
STK3CFG1
P20_PDN
PE23RP0PE23RN0
PE23TP0PE23TN0
470-1075-600 (1 of 2)
S20_12V
S16_12V
STK3CFG0
MEZZ_SMBDAT4MEZZ_SMBCLK4SLOT_WAKEN16SLOT_HDR_RSTN16
S16_CLKPS16_CLKN
M1620_ID<1>
SLOT_WAKEN20
S20_CLKNS20_CLKP
SLOT_HDR_RSTN20
PE16RP0PE16RN0
PE16TP0PE16TN0
PE17RP0PE17RN0
PE17TN0PE17TP0
PE18RP0PE18RN0
PE18TP0PE18TN0
100100
100100
S20_3V
S16_3V
S20_3VAUX
470-1075-600 (2 of 2)
S16_3VAUX
MEZZ_SMBDAT4
MEZZ_SMBCLK4
5%06
031K
06031K
5%
+3V3
MEZZANINE CONNECTOR PORTS 16/20
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUT
ININ
OUT
BI
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
SignalWafer 9
Wafer 8
Wafer 7
Wafer 6
Wafer 5
V18T18P18M18K18H18F18D18B18A17
C17E17G17J17L17N17R17U17W17
B16D16F16H16K16M16P16T16V16
W15U15R15N15L15J15G15E15C15A15
V20T20P20M20K20H20F20D20B20A19
C19E19G19J19L19N19R19U19W19
B14D14F14H14K14M14P14T14V14
W13U13R13N13L13J13G13E13C13A13
B12D12F12H12K12M12P12T12V12
W11U11R11N11L11J11G11E11C11A11
OUT
ININ
OUTOUT
OUTOUT
ININ
OUT
ININ
OUTOUT
ININ
IN
INOUT
OUT
IN
IN
IN
OUT
IN
OUT
BI
IN
ININ
OUTOUT
OUT
OUT
IN
OUT
IN
OUTOUT
OUT
OUT
ININ
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
CommonPower
Signal
Wafer 4
Wafer 3
Wafer 2
Wafer 1
Wafer 0
V8T8P8M8K8H8F8D8B8A7
C7E7G7J7L7N7R7U7W7
B6D6F6H6K6M6P6T6V6
W5U5R5N5L5J5G5E5C5A5
V10T10P10M10K10H10F10D10B10A9
C9E9G9J9L9N9R9U9W9
B4D4F4H4K4M4P4T4V4
W3U3R3N3L3J3G3E3C3A3
B2D2F2H2K2M2P2T2V2
W1U1R1N1L1J1G1E1C1A1
OUT
OUT
Tue Apr 20 12:38:33 2010 SHEET 5 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
U18T18
N18P18
V17U17
P17R17
V15U15
R16T16
V14U14
R13T13
V8U8
R10T10
V7U7
R9T9
V4U4
R6T6
V3U3
R5T5
U1
A9B9
D7C7
A10B10
D8C8
A15B15
D13C13
A16B16
D14C14
E18E17
G15G16
F18F17
H15H16
J18J17
L15L16
K18K17
M15M16
U1
T1T2
P4P3
R1R2
N4N3
M1M2
K4K3
L1L2
J4J3
H1H2
F4F3
G1G2
E4E3
B1B2
C4C3
A2A3
B5B4
U1
33
3
33
3
3
33
3
33
33
33
33
33
33
33
33
33
33
33
4
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
422
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
24NT24G2 - SERDES
PE15RN0PE15RP0
PE14RN0
PE13RN0PE13RP0
PE14RP0
PE11RN0
PE12RP0PE12RN0
PE11RP0
PE10RP0PE10RN0
PE09RN0PE09RP0
PE08RN0PE08RP0
PE15TN0PE15TP0
PE14TN0PE14TP0
PE13TP0PE13TN0
PE12TN0PE12TP0
PE11TN0PE11TP0
PE10TN0PE10TP0
PE09TN0PE09TP0
PE08TN0PE08TP0
PE16TP0
PE23RP0PE23RN0
PE22RN0PE22RP0
PE21RN0PE21RP0
PE20RN0PE20RP0
PE19RN0PE19RP0
PE18RP0PE18RN0
PE17RN0PE17RP0
PE16RN0PE16RP0
PE23TN0PE23TP0
PE22TN0PE22TP0
PE21TN0PE21TP0
PE20TP0PE20TN0
PE19TN0PE19TP0
PE18TN0PE18TP0
PE17TN0PE17TP0
PE16TN0PE00RP0PE00RN0
PE07TP0PE07TN0
PE06TN0PE06TP0
PE05TP0PE05TN0
PE04TP0PE04TN0
PE07RP0PE07RN0
PE06RN0PE06RP0
PE05RP0PE05RN0
PE04RP0PE04RN0
PE03TP0PE03TN0
PE02TN0PE02TP0
PE01TP0PE01TN0
PE00TP0PE00TN0
PE03RP0PE03RN0
PE02RN0PE02RP0
PE01RP0PE01RN0
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUT
OUTOUT
OUT
OUT
OUTOUT
OUTOUT
OUT
IN
OUT
IN
ININ
ININ
ININ
ININ
ININ
ININOUT
OUT
OUTOUT
OUTOUT
OUTOUT
IN
OUTOUT
OUTOUT
OUT
IN
OUT
OUTOUT
89HPES24NT24G2 (3/8)
PE07TP0PE07TN0
PE07RP0PE07RN0
PE06TP0PE06TN0
PE06RP0PE06RN0
PE05TP0PE05TN0
PE05RP0PE05RN0
PE04TP0PE04TN0
PE04RP0PE04RN0
PE03TP0PE03TN0
PE03RP0PE03RN0
PE02TP0PE02TN0
PE02RP0PE02RN0
PE01TP0PE01TN0
PE01RP0PE01RN0
PE00TP0PE00TN0
PE00RP0PE00RN0
ININ
ININ
ININ
ININ
IN
89HPES24NT24G2 (4/8)
PE15TP0PE15TN0
PE15RP0PE15RN0
PE14TP0PE14TN0
PE14RP0PE14RN0
PE13TP0PE13TN0
PE13RP0PE13RN0
PE12TP0PE12TN0
PE12RP0PE12RN0
PE11TP0PE11TN0
PE11RP0PE11RN0
PE10TP0PE10TN0
PE10RP0PE10RN0
PE09TP0PE09TN0
PE09RP0PE09RN0
PE08TP0PE08TN0
PE08RP0PE08RN0
OUTOUT
OUTOUT
OUT
OUTOUT
OUTOUT
IN
OUT
OUTOUT
OUTOUT
OUTOUT
OUT
OUTOUT
IN
ININ
ININ
89HPES24NT24G2 (5/8)
PE23TP0PE23TN0
PE23RP0PE23RN0
PE22TP0PE22TN0
PE22RP0PE22RN0
PE21TP0PE21TN0
PE21RP0PE21RN0
PE20TP0PE20TN0
PE20RP0PE20RN0
PE19TP0PE19TN0
PE19RP0PE19RN0
PE18TP0PE18TN0
PE18RP0PE18RN0
PE17TP0PE17TN0
PE17RP0PE17RN0
PE16TP0PE16TN0
PE16RP0PE16RN0
ININ
ININ
ININ
ININ
IN
ININ
IN
ININ
INOUT
OUT
IN
IN
DUT RESET
PLACE RESISTORS AS CLOSE TO U1 AS POSSIBLE
Tue Apr 20 12:38:32 2010 SHEET 6 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R55
R24
R46R47R48R49R50R51R52R53
R54T4P5R3N1
E5A5B7C6U2
D5D6B6C5R4
T3
C10
U16U6L4H4C9C12G17M18
E14
V11U11
D1D2
V12
A12
U12
B12
N2A8A4B8
C15U1
U1
R45
C17C18
F15R18
M17B14
D16B18
C16D15B17E15D17
N17N14N15P16N16R15T15R14T14
U1
98765432
121110
1
J118
TP108
4343839
328
891011121327891011121327
28
27
3343839
43438393343839
2739282828
1919
27
28
1919
1919
19
28
19
2828
28
282828
28
28
42828
428
2828
28
328
29
272727
2929
2929292929
8 9 10 11 12 13 29
27
27
28
24NT24G2 - CLK, CONFIG, GPIO
REFRES05REFRES06REFRES07
REFRESPLL
REFRES00REFRES01REFRES02REFRES03REFRES04
3.01K
3.01K
3.01K3.01K3.01K3.01K3.01K3.01K
3.01K
SLOT_HDR_RSTN20
STK2CFG1
MSMBCLKMSMBDAT
5%06
031K
+3V3
5%06
031K
SSMBADDR1
SSMBCLK
SLOT_HDR_RSTN8
NO-SHROUDVERT-TH 2.54MM
SLOT_HDR_RSTN16SLOT_HDR_RSTN12
MAIN_RSTNG1G2G3
GCLK1PGCLK1N
DUT_JTAG_TCK
CLKMODE1
YEL
P16CLKNP16CLKP
P08CLKNP08CLKP
GCLK0N
GCLKFSEL
GCLK0P
PERSTN
STK2CFG3STK2CFG4
RSTHALT
SWMODE2SWMODE1SWMODE0
SWMODE3
CLKMODE0
STK3CFG1STK3CFG2
STK3CFG0
STK3CFG3STK3CFG4
STK2CFG2
STK2CFG0
GPIO5
DUT_JTAG_TMSDUT_JTAG_TDODUT_JTAG_TDI
GPIO7GPIO6
GPIO4GPIO3GPIO2GPIO1GPIO0
GPIO8_IOEXPINTN
DUT_JTAG_TRST_N
0
SSMBDAT
SSMBADDR2
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
ININININ
ININ
ININ
ININ
INOUT
IN
OUT
OUTOUTOUTOUTOUT
OUTOUTOUT
IN
IN
ININ
IN
IN
IN
ININININ
IN
ININ
INININININ
89HPES24NT24G2 (1/8)
G3G2G1
P16CLKPP16CLKN
P08CLKPP08CLKN
SWMODE3SWMODE2SWMODE1SWMODE0
STK3CFG4STK3CFG3STK3CFG2STK3CFG1STK3CFG0
STK2CFG4STK2CFG3STK2CFG2STK2CFG1STK2CFG0
RSTHALT
REFRESPLL
REFRES07REFRES06REFRES05REFRES04REFRES03REFRES02REFRES01REFRES00
PERSTN
GCLKP1
GCLKP0
GCLKN1
GCLKN0
GCLKFSEL
CLKMODE1CLKMODE0
89HPES24NT24G2 (2/8)
SSMBDATSSMBCLK
SSMBADDR2SSMBADDR1
NC2NC1
MSMBDATMSMBCLK
JTAG_TRST_NJTAG_TMSJTAG_TDOJTAG_TDIJTAG_TCK
GPIO_08GPIO_07GPIO_06GPIO_05GPIO_04GPIO_03GPIO_02GPIO_01GPIO_00
IN
ININ
IN
ININ
OUTBI
ININ
BIIN
HDR_2x6
1211109
8765
1 23 4
IN
LABEL:
3 NC1 GND2 12V/5V
LABEL: FAN
Tue Apr 20 12:38:33 2010 SHEET 7 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
4321
5678
CP10
C2
V18V16V6V5U13U10U9
C1
U5T17V13T8T7R12V10V9R8R7
B13
P2P1N12N8M12M10M8M5M4M3
B11
L18L17L12L10L8L3K16K15K13K10
B3K8K6K2K1J16J15
J13J10
J8J6
A14
J2J1
H18H17H13H10
H8H6H3
G18
A13
G14G12G10
G8G4G3
F16F14F12
F8
A11
F2F1
E16E2E1
D18D10
D9D4D3
A1
U1
L5K14K5J14J5H14F10E10
P10P9P8N10L6
E9
M14L14L13
H5G5F5
D12D11
T12T11R11
C11
U1
4321
5678
CP7
4321
5678
CP4
4321
5678
CP2C118
C115
C111
C109
4321
5678
CP8
4321
5678
CP5
4321
5678
CP3
4321
5678
CP1C54
C31
C66
C62
C107
C104
C97
C93
C90
C87
C82
C74
C65
C61
C57
C47
C42
C39
C34
C27
C23
C18
C13
C8C3
C45
C40
C35
C26
C22
C17
C12
C7C2
C114
4321
5678
CP9
4321
5678
CP6
C106
C96
C91
C77
C69
C86
C92
C41
C51
C46
C44
C33
C37
C24
C29
C25
C19
C14
C9C4
C10
C15
C20
C5
C21
C16
C11
C6C1
W31
321
W30
G6F13F6E13E12E11E8
P13
E7
P12P11P7P6N13N6N5M13M6G13
E6
V2V1P15P14A18A17A7A6
H11H9H7
G11G9G7
F11
N11N9N7
M11M9M7
L11L9
F9
L7K12K11
K9K7
J12J11
J9J7
H12
F7
U1
24NT24G2 - POWER
0.1UF0.1UF
0.1UF 0.1UF 0.1UF 0.1UF
0.1UF 0.1UF0.1UF0.1UF
0.1U
F
0.1U
F
0.1U
F
0.1U
F
1.0U
F
1.0U
F
47UF
47UF
47UF
0.1U
F
+12V3_PS
0.1U
F
0.1U
F
0.1U
F
47UF
47UF
47UF
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
47UF
47UF
1.0U
F
47UF
47UF
47UF
47UF
1.0U
F
+3V3_IO
+1V0_PEA
+2V5_PEHA +1V0_PETA
+1V0_CORE
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
47UF
47UF
47UF
47UF
0.01
UF
0.01
UF0.
01UF
0.01
UF0.
01UF
0.01
UF0.
01UF
0.01
UF
47UF
0.1U
F
0.1U
F
0.1U
F
0.01
UF
47UF
47UF
1.0U
F
+1V0_PEA
+2V5_PEHA
+1V0_PETA47
UF
+5V0_PS
+1V0_CORE
0.1U
F
0.1U
F
0.1U
F
+3V3_IO
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
89HPES24NT24G2 (8/8)
VSS86VSS85VSS84VSS83VSS82VSS81VSS80VSS79VSS78VSS77VSS76VSS75VSS74VSS73VSS72VSS71VSS70VSS69VSS68VSS67VSS66VSS65VSS64VSS63VSS62VSS61VSS60VSS59VSS58VSS57VSS56VSS55VSS54VSS53VSS52VSS51VSS50VSS49VSS48VSS47VSS46VSS45VSS44
VSS43VSS42VSS41VSS40VSS39VSS38VSS37VSS36VSS35VSS34VSS33VSS32VSS31VSS30VSS29VSS28VSS27VSS26VSS25VSS24VSS23VSS22VSS21VSS20VSS19VSS18VSS17VSS16VSS15VSS14VSS13VSS12VSS11VSS10VSS9VSS8VSS7VSS6VSS5VSS4VSS3VSS2VSS1
89HPES24NT24G2 (7/8)
VDDPETA14VDDPETA13VDDPETA12VDDPETA11VDDPETA10
VDDPETA9VDDPETA8VDDPETA7VDDPETA6VDDPETA5VDDPETA4VDDPETA3VDDPETA2VDDPETA1
VDDPEHA12VDDPEHA11VDDPEHA10VDDPEHA9VDDPEHA8VDDPEHA7VDDPEHA6VDDPEHA5VDDPEHA4VDDPEHA3VDDPEHA2VDDPEHA1
89HPES24NT24G2 (6/8)
VDDPEA20VDDPEA19VDDPEA18VDDPEA17VDDPEA16VDDPEA15VDDPEA14VDDPEA13VDDPEA12VDDPEA11VDDPEA10
VDDPEA9VDDPEA8VDDPEA7VDDPEA6VDDPEA5VDDPEA4VDDPEA3VDDPEA2VDDPEA1
VDDIO8VDDIO7VDDIO6VDDIO5VDDIO4VDDIO3VDDIO2VDDIO1
VDDCORE27VDDCORE26VDDCORE25VDDCORE24VDDCORE23VDDCORE22VDDCORE21VDDCORE20VDDCORE19VDDCORE18VDDCORE17VDDCORE16VDDCORE15VDDCORE14VDDCORE13VDDCORE12VDDCORE11VDDCORE10VDDCORE9VDDCORE8VDDCORE7VDDCORE6VDDCORE5VDDCORE4VDDCORE3VDDCORE2VDDCORE1
ADDR: 0X24IOEXPANDER 2
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ADDR: 0X26IOEXPANDER 3
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ADDR: 0X20IOEXPANDER 0
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ADDR: 0X22IOEXPANDER 1
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
Tue Apr 20 12:38:33 2010 SHEET 8 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R1614
R77R78
12
24
2322
20191817161514131110987654
1
32
21
U22
C186
R72R73
R71
R1615
R79R80
12
24
2322
20191817161514131110987654
1
32
21
U23
C187
R75R74
R76
R69
R1612
R66R65
R59R60R61
12
24
2322
20191817161514131110987654
1
32
21
U20
C184
R1613
R62R63
R68R67
R64
12
24
2322
20191817161514131110987654
1
32
21
U21
C185
68910111213276891011121327
15 30 374 29 3729
15 32 37
3 29 37
31
13 16 32
6 8 9 10 11 12 13 29
13 16 32
3115 30 37
14 32 37313114 30 3714 30 37
29
68910111213276891011121327
29 37
30 37313132 3713 16 3229
30 37
13 16 32
3132 37
31
30 37
30 3729 3729
6 8 9 10 11 12 13 29
68910111213276891011121327
13 16 3215 32 37
4 29 37
14 30 37
29
14 30 37
293 29 37
13 16 3214 32 373131
15 30 37
3131
15 30 37
6 8 9 10 11 1213 29
68910111213276891011121327
313132 3713 16 32
2929 37
30 37313132 3713 16 3229
30 37
29 3730 3730 37
6 8 9 10 11 1213 29
IOEXPANDER 0-3
MSMBDATMSMBCLK
P16_PFNP16_PDNP16_APN
P16_PEP
P8_PDN
P16_PIN
P8_RSTN
GPIO8_IOEXPINTN
P16_RSTN
P16_AINP16_PWRGDN
P8_PEPP8_PINP8_AINP8_PWRGDNP8_PFN
P8_APN
MSMBCLKMSMBDAT
P4_PDN
P0_PWRGDNP0_AINP0_PINP0_PEPP0_RSTNP4_APN
P4_PWRGDN
P4_RSTN
P4_PINP4_PEP
P4_AIN
P4_PFN
P0_PFNP0_PDNP0_APN
GPIO8_IOEXPINTN
MSMBCLKMSMBDAT
P20_RSTNP20_PEP
P20_PDN
P12_PFN
P20_APN
P12_PWRGDN
P12_APNP12_PDN
P12_RSTNP12_PEPP12_PINP12_AIN
P20_PFN
P20_AINP20_PIN
P20_PWRGDN
GPIO8_IOEXPINTN
MSMBCLKMSMBDAT
P6_AINP6_PINP6_PEPP6_RSTN
P2_APNP2_PDN
P2_PWRGDNP2_AINP2_PINP2_PEPP2_RSTNP6_APN
P2_PFN
P6_PDNP6_PFNP6_PWRGDN
GPIO8_IOEXPINTN
+3V3
0.1U
F
MAX7311AUG
0
00
02.7K
0
+3V3
0.1U
F
MAX7311AUG
000
00
+3V3
0
1K
0
+3V3
2.7K2.7K
0.1U
F
MAX7311AUG
00
0
0
02.7K
+3V3
+3V3
0.1U
F
MAX7311AUG
00
+3V3
0
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
BIIN
OUT
INININ
INOUT
OUT
OUTOUT
IN
OUTINININ
OUTOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
BIIN
ININININ
OUTOUT
OUT
INOUT
ININ
OUT
INOUTOUTOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
INBI
IN
IN
INININ
OUTOUT
OUTOUT
INININBI
OUTIN
OUT
OUT
OUTOUT
OUT
ININ
OUT
INOUT
IN
OUT
ININ
OUTIN
IN
OUTOUT
OUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
IOEXPANDER 6
IOEXPANDER 7
ADDR: 0X2C
ADDR: 0X2E
PLACE RESISTORS ON CLOSE AND
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ON SAME SIDE OF BOARD
ADDR: 0X28IOEXPANDER 4
IOEXPANDER 5ADDR: 0X2A
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
Tue Apr 20 12:38:18 2010 SHEET 9 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R1618
R1619
12
24
2322
20191817161514131110987654
1
32
21
U26
C190
R101R102
R95R96R97
12
24
2322
20191817161514131110987654
1
32
21
U27
C191
R98R99
R104R103
R100
R1616
R1617
12
24
2322
20191817161514131110987654
1
32
21
U24
C188
R89R90
R84R83
R85
12
24
2322
20191817161514131110987654
1
32
21
U25
C189
R91R92
R87R86
R88
68910111213276891011121327
68910111213276891011121327
13 16 32
29 3730 37
32 3713 16 32
3131
29
30 3730 3729 37
32 37
3131
30 37
2929 3730 3730 37313132 3713 16 32
13 16 3232 373131
29 3729
30 3730 37
29
6 8 9 10 11 12 13 29
6 8 9 10 11 12 13 29
68910111213276891011121327
68910111213276891011121327
29 37
3131
30 3730 37
32 3713 16 32
30 3730 37
2929 37
32 373131
13 16 32
30 37
2929 3730 3730 37313132 3713 16 3229
2929 3730 37
313132 3713 16 32
6 8 9 10 11 1213 29
6 8 9 10 11 1213 29
IOEXPANDER 4-7
MSMBCLKMSMBDAT
MSMBCLKMSMBDAT
P1_RSTN
P3_PDNP3_PFN
P3_PEPP3_RSTN
P1_AINP1_PIN
P1_APN
P1_PWRGDNP1_PFNP1_PDN
P1_PEP
P3_AINP3_PIN
P3_PWRGDN
P5_APNP5_PDNP5_PFNP5_PWRGDNP5_AINP5_PINP5_PEPP5_RSTN
P7_RSTNP7_PEPP7_PINP7_AIN
P7_PDNP7_APN
P7_PWRGDNP7_PFN
P3_APN
GPIO8_IOEXPINTN
GPIO8_IOEXPINTN
MSMBCLKMSMBDAT
MSMBCLKMSMBDAT
P14_PDN
P14_AINP14_PIN
P14_PWRGDNP14_PFN
P14_PEPP14_RSTN
P18_PWRGDNP18_PFN
P18_APNP18_PDN
P18_PEPP18_PINP18_AIN
P18_RSTN
P22_PWRGDN
P10_APNP10_PDNP10_PFNP10_PWRGDNP10_AINP10_PINP10_PEPP10_RSTNP14_APN
P22_APNP22_PDNP22_PFN
P22_AINP22_PINP22_PEPP22_RSTN
GPIO8_IOEXPINTN
GPIO8_IOEXPINTN
2.7K
+3V3
2.7K0
00
0.1U
F
MAX7311AUG
+3V3
2.7K
00
+3V3
00
0.1U
F
MAX7311AUG
+3V3
0
0
2.7K
00
+3V3
2.7K2.7K
0.1U
F
MAX7311AUG
+3V3
2.7K2.7K
0
00
+3V3
0.1U
F
MAX7311AUG
+3V3
0
0
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUTOUTOUT
OUT
ININ
OUTIN
OUT
OUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
BIIN
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
INBI
OUT
ININ
ININ
OUTOUTOUT
INOUT
IN
ININ
OUTOUT
OUTOUT
OUT
IN
ININ
IN
OUTOUT
OUT
INOUT
ININ
INOUTOUT
IN
OUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
BI
INBI
ININ
OUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
ININ
OUT
IN
ININ
OUT
IN
OUT
OUT
OUT
OUTOUT
INININ
INOUT
IN
ADDR: 0X52
IOEXPANDER 9
PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ADDR: 0X50IOEXPANDER 8
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ADDR: 0X56IOEXPANDER 11
ADDR: 0X54IOEXPANDER 10
Tue Apr 20 12:38:19 2010 SHEET 10 OF 41
B
2009
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
R119R120R121
R162212
24
2322
20191817161514131110987654
1
32
21
U30
R125R126
C194
R122R123R124
R162312
24
2322
20191817161514131110987654
1
32
21
U31
C195
R127R128
R108R107
R109
R162012
24
2322
20191817161514131110987654
1
32
21
U28
C192
R113R114
R110R111R112
R162112
24
2322
20191817161514131110987654
1
32
21
U29
C193
R116R115
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
68910111213276891011121327
13 16 322929 37
30 3730 37
3131
32 3713 16 32
6 8 9 10 11 12 13 29
32 37
68910111213276891011121327
29 3729
30 3730 37
3131
29
29 37
30 3731
32 3713 16 32
31
30 37
29 37
2913 16 3232 37313130 3730 37
6 8 9 10 11 12 13 29
68910111213276891011121327
13 16 322929 37
30 3730 37
3131
32 3713 16 32
6 8 9 1011 12 13
29
32 37
68910111213276891011121327
29 3729
30 3730 37
3131
29 3729
30 3730 37
32 373131
13 16 322929 37
30 3730 37
3131
32 3713 16 32
6 8 9 1011 12 13
29
IOEXPANDER 8-11
MSMBDATMSMBCLK
P13_RSTNP15_APNP15_PDN
P15_PWRGDNP15_PFN
P15_PINP15_AIN
P15_PEPP15_RSTN
GPIO8_IOEXPINTN
P13_PEP
MSMBDATMSMBCLK
P13_PDNP13_APN
P13_PFNP13_PWRGDN
P13_PINP13_AIN
P9_APN
P11_PDN
P11_PWRGDNP11_AIN
P11_PEPP11_RSTN
P11_PIN
P11_PFN
P9_PDN
P11_APNP9_RSTNP9_PEPP9_PINP9_AINP9_PWRGDNP9_PFN
GPIO8_IOEXPINTN
MSMBCLKMSMBDAT
P21_RSTNP23_APNP23_PDN
P23_PWRGDNP23_PFN
P23_PINP23_AIN
P23_PEPP23_RSTN
GPIO8_IOEXPINTN
P21_PEP
MSMBDATMSMBCLK
P21_PDNP21_APN
P21_PFNP21_PWRGDN
P21_PINP21_AIN
P17_PDNP17_APN
P17_PFNP17_PWRGDN
P17_PEPP17_PINP17_AIN
P17_RSTNP19_APNP19_PDN
P19_PWRGDNP19_PFN
P19_PINP19_AIN
P19_PEPP19_RSTN
GPIO8_IOEXPINTN
00
0.1U
F
MAX7311AUG
0
000
00
0.1U
F
MAX7311AUG
0
0
00
00
0.1U
F
MAX7311AUG
0
02.7K
0
0.1U
F
00
MAX7311AUG
0
02.7K
0
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
OUT
OUT
IN
ININ
IN
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
OUT
OUTOUTOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
ININ
ININ
INBI
OUT
OUTOUTOUTOUT
ININININ
OUTOUTOUTOUT
IN
ININ
INOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
IN
INBI
INBI
OUT
BI
OUTOUT
ININININ
OUT
IN
IN
IN
OUT
IN
OUT
OUT
IN
OUTOUT
IN
OUT
OUTOUT
OUT
ININ
OUTOUT
ININ
IN
OUTIN
OUT
OUT
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ADDR: 0X5CIOEXPANDER 14
ADDR: 0X5EIOEXPANDER 15
PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD
PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD
IOEXPANDER 12ADDR: 0X58
IOEXPANDER 13ADDR: 0X5A
PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD
Tue Apr 20 12:38:19 2010 SHEET 11 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R1166R1167
R1160R1161R1162
R162612
24
2322
20191817161514131110987654
1
32
21
U96
C647
R162712
24
2322
20191817161514131110987654
1
32
21
U97
C648
R1168R1169
R1165R1164R1163
R1149R1148
R1154R1155
R1150
R162412
24
2322
20191817161514131110987654
1
32
21
U89
C645
R162512
24
2322
20191817161514131110987654
1
32
21
U90
C646
R1151R1152R1153
R1156R1157
68910111213276891011121327
6 8 9 10 11 12 13 29
33
33
333333
3333
3333
6 8 9 10 11 12 13 29
33
68910111213276891011121327
3333
3333
333333
333333
3333
3333
68910111213276891011121327
6 8 9 1011 12 13
29
333333333333333334
3434
3434
34
3434
6 8 9 1011 12 13
293434
68910111213276891011121327
3434
3434
343433
333333
3333
3333
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
IOEXPANDER 12-15
MSMBCLKMSMBDAT
GPIO8_IOEXPINTN
P22_MRLN
P23_MRLN
P17_MRLNP19_MRLNP21_MRLN
P15_MRLNP13_MRLN
P9_MRLNP11_MRLN
GPIO8_IOEXPINTN
P20_MRLN
MSMBCLKMSMBDAT
P16_MRLNP18_MRLN
P12_MRLNP14_MRLN
P10_MRLNP8_MRLNP7_MRLN
P4_MRLNP5_MRLNP6_MRLN
P3_MRLNP2_MRLN
P0_MRLNP1_MRLN
MSMBCLKMSMBDAT
GPIO8_IOEXPINTN
P1_ILOCKSTP3_ILOCKSTP5_ILOCKSTP7_ILOCKSTP10_ILOCKSTP14_ILOCKSTP18_ILOCKSTP22_ILOCKSTP1_ILOCKP
P5_ILOCKPP3_ILOCKP
P10_ILOCKPP7_ILOCKP
P14_ILOCKP
P22_ILOCKPP18_ILOCKP
GPIO8_IOEXPINTN
P20_ILOCKPP16_ILOCKP
MSMBCLKMSMBDAT
P8_ILOCKPP12_ILOCKP
P4_ILOCKPP6_ILOCKP
P2_ILOCKPP0_ILOCKPP20_ILOCKST
P8_ILOCKSTP12_ILOCKSTP16_ILOCKST
P6_ILOCKSTP4_ILOCKST
P0_ILOCKSTP2_ILOCKST
00
2.7K00
0.1U
F
MAX7311AUG
0
0.1U
F
MAX7311AUG
0
2.7K
00
00
02.7K2.7K
00
0.1U
F
MAX7311AUG
0
0.1U
F
MAX7311AUG
0
2.7K2.7K
0
00
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
INBI
OUT
OUTOUT
IN
ININ
IN
ININ
ININ
OUTOUTOUTOUTOUTOUTOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
OUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
BIIN
INININININININ
ININ
INININININ
INBI
OUT
IN
ININ
ININININ
ININ
ININ
BI
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
OUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
ININ
ININ
ININ
IN
OUTIN
OUTOUTOUTOUTOUT
IOEXPANDER 18ADDR: 0XA4
PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
ADDR: 0XA6IOEXPANDER 19
IOEXPANDER 16
PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD
IOEXPANDER 17ADDR: 0XA2
ADDR: 0XB0
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
Tue Apr 20 12:38:20 2010 SHEET 12 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
12
24
2322
20191817161514131110987654
1
32
21
U87
C643
R1143R1142
R1137R1136
R1138
12
24
2322
20191817161514131110987654
1
32
21
U88
C644
R1145R1144
R1139R1140R1141
C641
R162812
24
2322
20191817161514131110987654
1
32
21
U85
R1131R1130
R1124R1125R1126
12
24
2322
20191817161514131110987654
1
32
21
U86
C642
R1132R1133
R1127R1128R1129
6891011121327
6 8 9 10 11 13 29
34
33
33
68910111213276891011121327
3535
3535
3535
353535
353535
3535
3535
6891011121327
3434
3434
34343433
33
33
333333
68910111213276891011121327
35
3535
353535
3535
353535353535
3535
68910111213276891011121327
3535
3535
3535
353535
353535
3535
3535
IOEXPANDER 16-19
MSMBCLK
GPIO8_IOEXPINTN
P15_ILOCKP
P19_ILOCKST
P9_ILOCKST
0
MSMBDATMSMBCLK
P15_LINKUPNP14_LINKUPN
P12_LINKUPNP13_LINKUPN
P10_LINKUPNP11_LINKUPN
P9_LINKUPNP8_LINKUPNP7_LINKUPN
P4_LINKUPNP5_LINKUPNP6_LINKUPN
P3_LINKUPNP2_LINKUPN
P0_LINKUPNP1_LINKUPN
MSMBDAT
P23_ILOCKPP21_ILOCKP
P17_ILOCKPP19_ILOCKP
P13_ILOCKPP11_ILOCKPP9_ILOCKPP23_ILOCKST
P17_ILOCKST
P21_ILOCKST
P15_ILOCKSTP13_ILOCKSTP11_ILOCKST
MSMBCLKMSMBDAT
P16_LINKUPN
P18_LINKUPNP17_LINKUPN
P19_LINKUPNP20_LINKUPNP21_LINKUPN
P23_LINKUPNP22_LINKUPN
P16_ACTIVENP17_ACTIVENP18_ACTIVENP19_ACTIVENP20_ACTIVENP21_ACTIVEN
P23_ACTIVENP22_ACTIVEN
MSMBCLKMSMBDAT
P15_ACTIVENP14_ACTIVEN
P12_ACTIVENP13_ACTIVEN
P10_ACTIVENP11_ACTIVEN
P9_ACTIVENP8_ACTIVENP7_ACTIVEN
P4_ACTIVENP5_ACTIVENP6_ACTIVEN
P3_ACTIVENP2_ACTIVEN
P0_ACTIVENP1_ACTIVEN
+3V3
00
2.7K
00
0.1U
F
MAX7311AUG
000
00
+3V3
MAX7311AUG
0.1U
F
+3V3
+3V3
00
2.7K
00
0.1U
F
MAX7311AUG
+3V3
0
00
00
0.1U
F
+3V3
MAX7311AUG
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
BIIN
OUT
OUT
OUTOUT
OUTOUT
OUTOUT
OUTOUTOUT
OUT
OUTOUT
OUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
BIIN
ININ
ININ
ININ
IN
OUTIN
OUTOUTOUTOUTOUT
OUTOUT
OUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
INBI
OUTOUTOUTOUTOUTOUTOUTOUTOUT
BIOUTOUTOUTOUTOUTOUTOUT
OUTOUTOUT
OUTOUT
OUTOUTOUTOUTOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
OUTOUT
OUTOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
IN
PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD
ADDR: 0XA8
IOEXPANDER 20
IOEXPANDER 21
ADDR: 0XAA
ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND
Tue Apr 20 12:38:20 2010 SHEET 13 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R131R132
R137R138
R133
R163312
24
2322
20191817161514131110987654
1
32
21
U83
C196
R135R134
R136
R139R140
12
24
2322
20191817161514131110987654
1
32
21
U84
C197
8 16 32
34 3834 3834 38
68910111213276891011121327
9 16 329 16 32
9 16 329 16 32
10 16 329 16 3210 16 32
10 16 329 16 3210 16 32
9 16 3210 16 32
10 16 3210 16 32
9 16 3210 16 32
34 38
6 8 9 10 11 12 29
34 38
68910111213276891011121327
8 16 328 16 32
8 16 328 16 32
8 16 32
8 16 32
8 16 3234 3834 38
34 38
+3V3
+3V3
+3V3
IOEXPANDER 20-21
P12_RSTN
PART2_PERSTNPART3_PERSTNPART4_PERSTN
MSMBCLKMSMBDAT
P3_RSTNP1_RSTN
P5_RSTNP7_RSTN
P11_RSTNP10_RSTNP9_RSTN
P13_RSTNP14_RSTNP15_RSTN
P18_RSTNP17_RSTN
P21_RSTNP19_RSTN
P22_RSTNP23_RSTN
PART7_PERSTN
GPIO8_IOEXPINTN
PART6_PERSTN
MSMBDATMSMBCLK
P2_RSTNP0_RSTN
P4_RSTNP6_RSTN
P16_RSTN
P8_RSTN
P20_RSTNPART0_PERSTNPART1_PERSTN
PART5_PERSTN
0.1U
F
MAX7311AUG
00
0
2.7K0
0.1U
F
MAX7311AUG
0
0
00
00
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUTOUTOUTOUTOUTOUTOUTOUT
IN
ININ
BI
IN
ININ
IN
INBI
OUT
ININ
OUT
OUTOUT
OUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
OUT
OUTOUT
OUTOUTOUT
OUTOUT
OUTOUTOUT
A0
A2
VSS
A1
V+
SDASCL
P1P0
P2P3
P6P5P4
P7P8P9
P11P10
P13P12
P14P15
INT_N
Tue Apr 20 12:38:20 2010 SHEET 14 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
W15
W16
C263
R256R254
8765
4321Q1
1
C261
R250
R252
R248
R246
8765
4321Q9
R245
W17
W18
W19
W20C264
R257R255
C262
R251
8765
4321Q1
2
R253
R247
7
19
33
14
38
3926
15
37
17
35
16
36
20
32
25
27
13
1
8
6
18
34
10
4
12
2
9
5
11
3
22
30
24
28
21
31
23
29
U47
C260
R249
8765
4321Q1
0
R244
R243
R241
R242
R240
R239
R238
R237
R225R226R227R228R229R230R231R232R233R234R235R236
R224
R223
83237
83037
83037
83037
83237
83037
+3V3_PS
S12_12V
S12_3V
S12_3VAUX
S8_3VAUX
+12V2_PS
S8_12V
+3V3_PS
S8_3V
HOT PLUG CONTROL PORTS 8-12
P12_PEPP12_PWRGDNP12_PFNP8_PWRGDN
P8_PEPP8_PFN
10K
10K
100100100100100100100100100100100100
10K
10K
10K
10K
10K
10K
10K
10K
10
1.0U
F
0.008
0.013
51
0.01
5UF
10 15
0.04
7UF
33
0.008
10
0.013
51
0.01
5UF
10 15
0.04
7UF
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
NMOS
FET S S S G
D D D D
OUT
NMOS
FET
S S S G
D D D D
IN
NMOS
FET S S S G
D D D D
OUT
LTC4242CUHF
FON2ENN2
GND2GND1
ENN1FON1
3VIN2
3VGATE23VSENSE2
3VOUT2
AUXOUT2
AUXOUT1
3VOUT13VGATE1
3VIN13VSENSE1
12VOUT212VGATE212VSENSE212VIN2
AUXIN2AUXON2ON2PGOODN2AUXPGOODN2AUXFAULTN2FAULTN2
AUXPGOODN1PGOODN1
AUXFAULTN1FAULTN1ON1AUXON1AUXIN1
VCC
12VSENSE112VIN1
12VOUT112VGATE1
NMOS
FET
S S S G
D D D D
OUT
OUT
IN
Tue Apr 20 12:38:21 2010 SHEET 15 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
W21
C268
R291R289
C266
R285
R281
W22
W23
W24
W25
W26
8765
4321Q1
5
R292
C269
R290
8765
4321Q1
6
C267
R287
R283
8765
4321Q1
3
R286
R288
R284
7
19
33
14
38
3926
15
37
17
35
16
36
20
32
25
27
13
1
8
6
18
34
10
4
12
2
9
5
11
3
22
30
24
28
21
31
23
29
U48
R282
8765
4321Q1
4
R280
R278
R279
R277
R276
R275
R274
R273
R272
R261R260
R263R262
R264R265R266
R268R267
R269R270R271
C265
R258
R259
83037
83037
83237
83037
83037
83237
S20_12V
S20_3V
S20_3VAUX
S16_3VAUX
S16_12V
+3V3_PS +12V3_PS +3V3_PS
S16_3V
HOT PLUG CONTROL PORTS 16-20
P20_PWRGDNP20_PFN
P20_PEP
P16_PFNP16_PWRGDN
P16_PEP
10K
10K
1.0U
F
100100100
100100
100100100
100100
100100
10K
10K
10K
10K
10K
10K
10K
10K
33
0.008
10
0.013
51
10
0.013
0.01
5UF
10
0.04
7UF
15
0.008
51
0.01
5UF
10 15
0.04
7UF
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
NMOS
FET S S S G
D D D D
OUT
NMOS
FET S S S G
D D D D
NMOS
FET
S S S G
D D D D
OUT
LTC4242CUHF
FON2ENN2
GND2GND1
ENN1FON1
3VIN2
3VGATE23VSENSE2
3VOUT2
AUXOUT2
AUXOUT1
3VOUT13VGATE1
3VIN13VSENSE1
12VOUT212VGATE212VSENSE212VIN2
AUXIN2AUXON2ON2PGOODN2AUXPGOODN2AUXFAULTN2FAULTN2
AUXPGOODN1PGOODN1
AUXFAULTN1FAULTN1ON1AUXON1AUXIN1
VCC
12VSENSE112VIN1
12VOUT112VGATE1
NMOS
FET
S S S G
D D D D
IN
OUT
OUT
Tue Apr 20 12:38:34 2010 SHEET 16 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R1285R1286R1287R1288
R1289R1290R1291R1292
R1293R1294R1295R1296
R1297
R1299R1298
R1300
R1301
R1303R1302
R1304
R1305R1306R1307R1308
R36
R37
R44
R1280
R1281
4
51
3
2
U108
4
51
3
2
U109
4
51
3
2
U110
4
51
3
2
U111
4
51
3
2
U112
R1282
R1283
R1284
C672
C671
C670
C669
4
51
3
2
U113
4
51
3
2
U114
4
51
3
2
U115
R15
R22
R23
R25
R26
4
51
3
2
U100
4
51
3
2
U101
4
51
3
2
U102
4
51
3
2
U103
4
51
3
2
U104
R1
R2
R3
4
51
3
2
U4
4
51
3
2
U5
R4
R11
4
51
3
2
U6
4
51
3
2
U7
4
51
3
2
U8
R33
R34
R35
C668
C667
C666
C665
4
51
3
2
U105
4
51
3
2
U106
4
51
3
2
U107
R12
R13
R14
4
51
3
2
U9
4
51
3
2
U10
C664
C663
C662
C661
4
51
3
2
U11
37 39
37 38 39
37 38 39
37 38 39
37 39
37 38 39
37 38 39
37 38 39
37 39
37 38 39 37 38 39
37 38 39
37 38 39
37 38 39
37 39
37 38 39
37 38 39
37 38 39
37 38 39
37 38 39
37 38 39
37 38 39
37 38 39
37 38 39
81332
101332
81332
101332
91332
101332
81332
101332
91332
101332
91332
101332
81332
101332
91332
101332
81332
91332
81332
91332
81332
91332
81332
91332
3737374 37
3737374 37
3737373 37
3737373 37
37373737
37373737
SLOT RESETS AND WAKE PULL-UPS
0.1U
F
SLOT_RSTN16
SLOT_RSTN17
SLOT_RSTN18
SLOT_RSTN19
SLOT_RSTN20
SLOT_RSTN21
SLOT_RSTN22
SLOT_RSTN23
SLOT_RSTN8
SLOT_RSTN9 SLOT_RSTN1
SLOT_RSTN0
SLOT_RSTN10
SLOT_RSTN11
SLOT_RSTN12
SLOT_RSTN13
SLOT_RSTN14
SLOT_RSTN15
SLOT_RSTN2
SLOT_RSTN3
SLOT_RSTN4
SLOT_RSTN5
SLOT_RSTN6
SLOT_RSTN7
P16_RSTN
P17_RSTN
0.1U
F
0.1U
F
0.1U
F
0.1U
F
10K
10K
P8_RSTN
P9_RSTN
P18_RSTN
P19_RSTN
P20_RSTN
P21_RSTN
P22_RSTN
P23_RSTN
10K
10K
P10_RSTN
P11_RSTN
10K
10K
10K
P12_RSTN
P13_RSTN
P14_RSTN
+3V3
10K
P15_RSTN
0.1U
F
0.1U
F10K
10K
P0_RSTN
P1_RSTN
0.1U
F
0.1U
F
10K
10K
0.1U
F
10K
P2_RSTN
P3_RSTN
10K
10K
10K
P4_RSTN
P5_RSTN
P6_RSTN
+3V3
10K
P7_RSTN
10K
10K
10K
10K
10K
10K
+3V3
10K
0.1U
F
0.1U
F
SLOT_WAKEN23SLOT_WAKEN22SLOT_WAKEN21SLOT_WAKEN20
SLOT_WAKEN19SLOT_WAKEN18SLOT_WAKEN17SLOT_WAKEN16
SLOT_WAKEN15SLOT_WAKEN14SLOT_WAKEN13SLOT_WAKEN12
SLOT_WAKEN11SLOT_WAKEN10SLOT_WAKEN9SLOT_WAKEN8
SLOT_WAKEN7SLOT_WAKEN6SLOT_WAKEN5SLOT_WAKEN4
SLOT_WAKEN3SLOT_WAKEN2SLOT_WAKEN1SLOT_WAKEN0
1K1K1K1K
1K
1K1K
1K
1K
1K1K
1K
1K1K1K1K
1K1K1K1K
1K1K1K1K
+3V3
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
SN74LVC1G125
Y
VCCOE_N
A
GND
OUT
OUT
OUT
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
IN
OUT
IN
OUT
INSN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
OUT
IN
OUT
IN
OUT
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
IN
OUT
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
IN
OUT
IN
IN
OUT
INSN74LVC1G125
Y
VCCOE_N
A
GND
OUTOUT
OUT
OUT
OUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUTOUTOUT
OUTOUTOUTOUT
OUTOUTOUTOUT
OUT
OUT
SN74LVC1G125
Y
VCCOE_N
A
GND
OUT
OUT
OUT
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
SN74LVC1G125
Y
VCCOE_N
A
GND
PLACE R317 & R318 U51
NCNCNCNC
PLACE J6 CLOSE TO U51
Tue Apr 20 12:38:21 2010 SHEET 17 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
MTG2MTG1
7654321
J121
C281
5 4
32
1
J119
5 4
32
1
J120
FB1
C280
C279
C278
C277
R306
C276
C275
C274C2
73
TP2
R309
R307
R308
R310
R302
R301
R304
R303
R305
R299
R297
R295
C270
R298
R296
R294
21
X1
9
8765
4
3332
31
30
3
29
28
27
2625
24
2322
21
20
2
19
18171615
14
13121110
1
U49
R300
R293
C271
R311
R313
R315
R317
R318
R316
R314
R312
MTG2MTG1
7654321
J8
54
3 2
1
J7
5 4
32
1
J5
98765432
10
1
J6
171728
28
17
17
18
17
17
18
27
1717
CLOCK49
.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
33.2
33.2
33.2
33.2 CGCLKN
33.2
33.2
33.2
33.2 CGCLKP
33.2
CONNSMA
CG_SMA_CLKN
DNP
10K
ICS_FS
ICS_SSM47
5
22PF
22PF
CGCLKP
SATAIN_CLKP
MAIN_CLKPSMAIN_CLKP SMAIN_CLKN
CGCLKN
SATAIN_CLKN
MAIN_CLKN
SATAIN_RSTN
SATAIN_CLKNSATAIN_CLKP
CG_SATA_CLKNCG_SMA_CLKP
CG_SATA_CLKP
NO-SHROUDVERT-SM 2.00MM
221789-0
CONNSMA
221789-0
CONNSMA
1%
DNP
1%04
02
1%04
02DNP
DNP
1%04
02
1%04
02DNP
DNP
1%04
02
YEL
16V
10UF
0.1U
F
0.1U
F
0.1U
F
100603 5%
0.1U
F
0.1U
F
10UF
0.1U
F
400MA120OHM
0805
+3V3
CONNSMA
221789-0
221789-0
1.0U
F
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
678005005
MTG2MTG1
7654321
OUTOUT
HDR_2x5
1098765
1 23 4
12
ICS841484
REF_IN
XTAL_OUT
XTAL_IN
REF_SEL
FSEL0FSEL1
OE_REFOUTMR_nOEIREFSSM
GND
PGNDGNDGND
VDDVDDVDDVDD
REF_OUT
NC
VDDA
Q2
nQ0
BYPASS
NCNCNC
nQ3Q3
nQ2
nQ1Q1
Q0
OUT
IN
IN
IN
OUTOUT
OUT
678005005
MTG2MTG1
7654321
OUT
IN
3 P16_CLK_EN
SWITCH S11
4 P20_CLK_EN-------------------
SILKSCREEN LABEL:POS DESCRIPTION-------------------
1 P8_CLK_EN2 P12_CLK_EN
SCH-PESEB-002
Tue Apr 20 12:38:22 2010
B
Tony Tran2010
Derek HuangSHEET 18 OF 41
1.118-692-000
EB-LOGAN-19
48393119112
54
12423
26
40
44
36
35
43
7
15
14
6
45
46
28
47322518
103
27
4142
3738
3334
2930
2120
1716
1312
98
22
U50
R359
R360
C292
C291
R365
R362
R364
R363
R361
R357
R358
R355
R356
R354
R351
R350
R333
C290
C289
C288
C287
C286
C285
R334R335
R337R336
R338R339
R340R341
R342
FB2
C283
C282
R328
R326
R324
R343
R344R345
R348R349
TP5
R332
R329
R327
R325
R322
R323
R320
R321
54
3 2
1
J122
54
3 2
1
J123
R164
8
R164
6
54637281
S11
C753C754
R164
9
R164
7
MTG2MTG1
7654321
J124
2020
2020
2020
1717
2020
1919
1919
CLOCK BUFFER - 1
+3V3
SATAOUT_CLKNSATAOUT_CLKP
33.233.2
49.9
49.9
DNP
DNP
33.2SMAOUT_CLKN_R33.2SMAOUT_CLKP_R
33.2BS20CLKN_R33.2BS20CLKP_R
33.2BS16CLKN_R33.2BS16CLKP_R
33.2BS12CLKN_R33.2BS12CLKP_R
33.2BS08CLKP_R33.2BS08CLKN_R
33.2BGCLK1N_R33.2BGCLK1P_R
33.2BGCLK0N_R33.2BGCLK0P_R
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
P20_CLK_EN
P8_CLK_EN
SATAOUT_CLKNSATAOUT_CLKP
DNP
10.0
KDN
P10
.0K
BS16CLKNBS16CLKP
YEL
BS20CLKNBS20CLKP
BS12CLKNBS12CLKP
221789-0
CONNSMA
CONNSMA
221789-0
475
1%
0.1U
F
1.0U
F
+3V3
2.21%
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
10UF
600OHM0805 500MA
0.1U
F
1.0U
F
DNP
10.0
KDN
P
10.0
K10
.0K
10.0
K
MAIN_CLKPMAIN_CLKN
+3V3
P12_CLK_ENP16_CLK_EN
SMAOUT_CLKNSMAOUT_CLKP
BS08CLKNBS08CLKP
BGCLK1NBGCLK1P
BGCLK0NBGCLK0P
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUTOUT
OUTOUT
ININ
OE_INV=1
ICS9DB803
DIFF_STOP
GNDGNDGND
SCLKSDATASRC_DIV#
OE_INVBYPASS#/PLL
PDHIGH_BW#
OE7#
OE5#
OE6#
OE4#
OE2#
OE3#
OE1#
OE0#
SRC_IN#SRC_IN
VDDVDDVDD
GNDGNDA
GND
DIF_7#
LOCK
IREF
DIF_7
DIF_6DIF_6#
DIF_5#DIF_5
DIF_4DIF_4#
DIF_3DIF_3#
DIF_2DIF_2#
DIF_1#
DIF_0#
DIF_1
DIF_0
VDDAVDDVDD
OUTOUT
OUTOUT
OUTOUT
OUTOUT
SM_SW4S1A
S4BS3BS2BS1B
S4AS3AS2A
678005005
MTG2MTG1
7654321
PXXCLK - DUT CLK
SHXXCLK - SLOT HDR. CLKLPXXLCK - LOCAL CLOCK GEN. PORT CLK
Tue Apr 20 12:38:22 2010 SHEET 19 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
MTG2MTG1
7654321
J21
54
3 2
1
J67
5 4
32
1
J66
MTG2MTG1
7654321
J22
54
3 2
1
J20
98765432
10
1
J189
8765432
10
1
J19
5 4
32
1
J17
TP129
TP131
MTG2MTG1
7
65
4 321
J62
MTG2MTG1
7
65
4 321
J64
98765432
10
1
J13
98765432
10
1
J15
1919
1919
6
19
2041
6
19
4020
19
2041
19
2040
6
6
19
18
6
19
18
1919
6
18
19
6 6
18
19
1919
CLOCK SELECTOR DUT PCLK 8 & 16
CONNSMA
P16_SATACLKNP16_SATACLKP
P16_SATARSTN
P8_SATACLKNP8_SATACLKP
P8_SATARSTN
YEL
YEL
P16CLKP
P16_SATACLKP
SH16_CLKPLP16_CLKP
P08CLKP
P8_SATACLKP
LP8_CLKPSH8_CLKP
P16_SATACLKN
SH16_CLKNLP16_CLKN
P8_SATACLKN
SH8_CLKNLP8_CLKN
P16CLKN
P08CLKN
2.00MMVERT-SMNO-SHROUD
2.00MMVERT-SMNO-SHROUD
G0_SATACLKP
BGCLK0P
GCLK0P
G0_SATACLKN
BGCLK0N
G0_SATACLKNG0_SATACLKP
GCLK0N
CONNSMA
221789-0
2.00MMVERT-SMNO-SHROUD
CONNSMA
221789-0
CONNSMA
BGCLK1P
G1_SATACLKP
GCLK1P GCLK1N
BGCLK1N
G1_SATACLKN
G1_SATACLKPG1_SATACLKN
221789-0
2.00MMVERT-SMNO-SHROUD
221789-0
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
ININ
IN
OUTOUT
OUT OUTOUT
678005005
321
47MTG1MTG2
56
INOUT
IN
IN
678005005
321
47MTG1MTG2
56
IN
ININ
OUT
HDR_2x5
1098765
1 23 4
HDR_2x5
1098765
1 23 4
OUTININ
IN
OUTOUT
OUT
678005005
MTG2MTG1
7654321
OUT
OUTOUT
IN
IN
678005005
MTG2MTG1
7654321
OUT
IN
IN
HDR_2x5
1098765
1 23 4
HDR_2x5
1098765
1 23 4
IN
IN
OUT
IN
IN
SXXCLK - SLOT CLKBSXXLCK - BUFFER SLOT CLKLSXXCLK - LOCAL CLOCK GEN. SLOT CLKSHXXCLK - SLOT HDR.CLK
Tue Apr 20 12:38:34 2010 SHEET 20 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
TP93
TP94
TP95
MTG2MTG1
7654321
J35
98765432
121110
1
J31
MTG2MTG1
7654321
J36
MTG2MTG1
7654321
J37
654321
J32
98765432
121110
1
J33
TP96
MTG2MTG1
7654321
J38
654321
J34
340
1819
20
340
1819
20
39
2020
2020
39
2020
39
4
2020
39
331818
20 20441818
20 20
44141
18 1819 19
20 20
CLOCK SELECTOR SLOTS 8-20
2.00MMVERT-SMNO-SHROUD
S8_CLKNLS8_CLKN
BS08CLKNSH8_CLKN
S8_SATACLKN
S8_CLKPLS8_CLKP
BS08CLKPSH8_CLKP
S8_SATACLKP
DNPS16_SATA_WAKES16_SATA_RSTN
S16_SATACLKPS16_SATACLKN
DNPS20_SATA_WAKE
S20_SATACLKPS20_SATACLKN
S20_SATA_RSTN
DNP
DNP
S12_SATACLKPS12_SATACLKN
S12_SATA_RSTN
S16_CLKN
S8_SATACLKPS8_SATACLKN
S8_SATA_RSTNS8_SATA_WAKE
S12_SATA_WAKES12_CLKNS12_CLKPBS12CLKNBS12CLKP
S12_SATACLKP S12_SATACLKN2.00MMVERTNO
S20_CLKNS20_CLKPBS20CLKNBS20CLKP
S20_SATACLKP S20_SATACLKN2.00MMVERTNO
S16_CLKPLS16_CLKNLS16_CLKP
BS16CLKP BS16CLKNSH16_CLKP SH16_CLKN
S16_SATACLKP S16_SATACLKN2.00MMNO-SHROUD
VERT-SM
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
OUTININ
OUTIN
IN
OUTIN
ININ
IN
OUT
OUT
678005005
MTG2MTG1
7654321
INOUT
INHDR_2x3
65
1 23 4OUT
IN
IN
OUTOUT
OUT
OUTOUT
OUT
OUTOUT
OUT
OUT
678005005
MTG2MTG1
7654321
IN
IN
OUT
ININ
HDR_2x6
1211109
8765
1 23 4
678005005
MTG2MTG1
7654321
678005005
MTG2MTG1
7654321
INOUT
IN
HDR_2x3
65
1 23 4
IN
ININ
OUT
IN
HDR_2x6
1211109
8765
1 23 4
RIGHT ANGLED
RIGHT ANGLED
SCATTER AROUND BOARDGND TEST POINTS
LOADED SYSTEMSUSED FOR LIGHTLY
+12.0V -> +3.3V
Tue Apr 20 12:38:22 2010 SHEET 21 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
C367
C364
C362
C360
C358
C356
C354
C352
C350
C348
C346
C344
C342
C340
C337
C334
C332
TP28TP29
C369
C366
5
7
6
8
2
9
101
1143
VR1
R509C3
39
C336
TP32
TP31
TP30
C330
C328
C326
C324
C322
R506
23
1U98
54
23
1
S1
W27
R508
R507
DS2
DS1
C321
C320
W28W29
TP27
TP26
TP25
TP24
TP23
TP22
C319
C318
TP21
TP20
TP19TP18TP17
8
16
24
191817
15
7
5
3
20
14
9
232221
6
4
13
12
21
1110
J69
C317
C316
C315
8765
4321
J68
TP16
37
POWER CONNECTORS
PS_ENABLEN
0039301080
+12V3_PS
10UF
25V
22UF
47UF
0039291247
WHT
WHT
10UF
25V
10UF
25V
WHT
WHT
WHT
WHT
WHT
WHT
+12V2_PS
+12V1_PS
DNPDNP
22UF
25V
47UF
GRN
GRN
330
150
+12V3_PS
+5V0_PS
+12V3_PS
+3V3_PS
0603 5%1K
+5V0_PS
+3V3_PS
47UF
47UF
47UF
0.1U
F
+3V3_PS
0.1U
FWH
T
WHT
WHT
25V
22UF
25V
22UF
0603
1%1.
21K
47UF
10V
220U
F
YELYEL
+3V3
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
FIDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
PTH08T240WAD
SYNCVout
VO_SEN-
Vin VO_SEN+
TURBOTRANS
Track
GND2GND1Vo_Adj
Inhibit
OUT
MMBT3904C
EB
SPDT_TGLON
OFFB
A
MTG1MTG2
COM
POWER 8-PIN
P12V22P12V21P12V12P12V11
GND4GND3GND2GND1
+3.3V_4-12V_1
GND_4PS-ONGND_5
+3.3V_3+12V3_2+12V3_1+5VAB
GND_8+5V_5+5V_4
+5V_2GND_2+5V_1GND_1+3.3V_2+3.3V_1
GND_3PWROK
+5V_3-5V
GND_7GND_6
VDD_IO, 3.3V
PLACE CLOSE TO U1
PLACE R528 & R529 CLOSE TO U1, NOISE-FREE ROUTINGPLACE R526 & R527 CLOSE TO U57, NOISE-FREE ROUTING
ROUTE AS POWER NET OR ISLAND
8%
4%
2%
1%
PLACE W33 CLOSE TO J112
MARGINING CONTROL
------------------------------
MARG1 | MARG0 | MODE
HIGH | HIGH | NO MARGIN
------------------------------LOW | LOW | NO MARGIN
------------------------------LOW | HIGH | MARGIN UPHIGH | LOW | MARGIN DOWN
------------------------------
Tue Apr 20 12:38:23 2010 SHEET 22 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
1
J78
1
J79
C396
C395
FB5
C394
C392C3
91
C390
C389
C388
C387
R528R529R527
R526
C386
R525
C385
C384
R524
R523
TP37
R516
R515
W33
C381
C380
TP38
C383
R519
R518R517
R522
R521R520
R139
0R1
389
768594103112121
S9
L12
J9J8J7J6J5
M11M10M9M8
J4
M7M6M5M4M3M2M1L11L10L9
J3
L8L7L6L5L4L3L2L1K11K10
J2
K9K8K7K6K5K4K3K2K1J10
J1
J12M12
B3B2B1A6A5A4A3A2
C6C5C4C3C2C1B6B5B4
A1
F12
A9
H12
A10
A8
G12
A12
D12C12
A7
E3E2E1D6D5
H9
D4
H8H7H6H5H4H3H2H1G9G8
D3
G7G6G5G4
G3G2G1F9F8F7
D2
F6F5F4F3F2F1E7E6E5E4
D1
B12
E12
K12
A11
U56 POWER REGULATOR - VDDIO
PS_IO_CTRL0PS_IO_CTRL1PS_IO_CTRL2PS_IO_CTRL3PS_IO_MARG1PS_IO_MARG0
REG_2V5_VDDIO
1.96M
1.96M
1.96M
487K
487K487K
10K
10K
+3V310
UF
10UF
100K
100K
+3V3
0.01
UF
DNP
DNP
DNP
18.2
K
51.1
K
191K
16V
100U
F
100P
F
+12V3_PS
00
47UF
47UF
47UF
47UF
00
1.0U
F
1.0U
F
0.1U
F
10UF
1.0U
F
6.5A26NH
BLK
RED
+3V3_IO
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
SM_SW6S1A
S6BS5BS4BS3BS2BS1B
S6AS5AS4AS3AS2A
LTM4603
GND40GND39GND38
VIN18VIN17VIN16VIN15VIN14VIN13
VOSNSN
VOUT43VOUT42VOUT41VOUT40VOUT39VOUT38VOUT37VOUT36VOUT35VOUT34VOUT33
VOUT_LCL
VOUT32VOUT31VOUT30VOUT29VOUT28VOUT27VOUT26VOUT25VOUT24VOUT23VOUT22
DIFFVOUT
VOUT21VOUT20VOUT19VOUT18VOUT17VOUT16VOUT15VOUT14VOUT13VOUT12VOUT11
VOSNSP
VOUT10VOUT9VOUT8VOUT7VOUT6VOUT5VOUT4VOUT3VOUT2VOUT1
SGND
GND37GND36GND35GND34GND33GND32GND31GND30
PGOOD
GND29GND28GND27GND26
GND25GND24GND23GND22
VFB
GND21GND20GND19GND18GND17GND16GND15GND14
DRVCC
GND13GND12GND11GND10GND9GND8GND7
MARG1
GND6GND5GND4GND3GND2GND1
MARG0
FSET
VIN12VIN11VIN10VIN9VIN8VIN7
MPGM
COMP
RUN
TRACK/SS
PLLIN
INTVCC
VIN6VIN5VIN4VIN3VIN2VIN1
CONN BANANA
CONN BANANA
VDD_CORE, 1.0V
PLACE CLOSE TO U1
PLACE R544 & R545 CLOSE TO U57, NOISE-FREE ROUTING
ROUTE AS POWER NET OR ISLAND
PLACE R546 & R547 CLOSE TO U1, NOISE-FREE ROUTING
PLACE W34 CLOSE TO J114
HIGH | HIGH | NO MARGIN
MARG1 | MARG0 | MODE------------------------------------------------------------------------------------------------------------------------
LOW | LOW | NO MARGINLOW | HIGH | MARGIN UPHIGH | LOW | MARGIN DOWN
8%
4%
2%
1%MARGINING CONTROL
Tue Apr 20 12:38:23 2010 SHEET 23 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
1
J114
1
J113
FB6
C413
C412
C411
C409C4
08
C407
R546R547
C406
C405
C404
R544R545
R534
R533
C398
C397
C403
C401
R543R5
42
R541
TP41
TP42
C400
C402
L12
J9J8J7J6J5
M11M10M9M8
J4
M7M6M5M4M3M2M1L11L10L9
J3
L8L7L6L5L4L3L2L1K11K10
J2
K9K8K7K6K5K4K3K2K1J10
J1
J12M12
B3B2B1A6A5A4A3A2
C6C5C4C3C2C1B6B5B4
A1
F12
A9
H12
A10
A8
G12
A12
D12C12
A7
E3E2E1D6D5
H9
D4
H8H7H6H5H4H3H2H1G9G8
D3
G7G6G5G4
G3G2G1F9F8F7
D2
F6F5F4F3F2F1E7E6E5E4
D1
B12
E12
K12
A11
U59
W34
R139
1R1
392
R535R536
R537
R539R538
768594103112121
S6
R540
POWER REGULATOR - VDDCORE
PS_CORE_CTRL0PS_CORE_CTRL1PS_CORE_CTRL2PS_CORE_CTRL3PS_CORE_MARG1PS_CORE_MARG0
REG_1V0_CORE
1.96M
1.96M1.96M
487K
487K487K
10K
10K
+3V3
DNP
DNP
DNP
10UF
10UF
100K
+3V3
100K
+12V3_PS
127K
1%31
6K1%
0.01
UF19
1K
100P
F
00
16V
100U
F
47UF
47UF
47UF
00
47UF
1.0U
F
1.0U
F
0.1U
F
26NH6.5A
BLK
RED
10UF
1.0U
F
+1V0_CORE
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
CONN BANANA
CONN BANANA
SM_SW6S1A
S6BS5BS4BS3BS2BS1B
S6AS5AS4AS3AS2A
LTM4603
GND40GND39GND38
VIN18VIN17VIN16VIN15VIN14VIN13
VOSNSN
VOUT43VOUT42VOUT41VOUT40VOUT39VOUT38VOUT37VOUT36VOUT35VOUT34VOUT33
VOUT_LCL
VOUT32VOUT31VOUT30VOUT29VOUT28VOUT27VOUT26VOUT25VOUT24VOUT23VOUT22
DIFFVOUT
VOUT21VOUT20VOUT19VOUT18VOUT17VOUT16VOUT15VOUT14VOUT13VOUT12VOUT11
VOSNSP
VOUT10VOUT9VOUT8VOUT7VOUT6VOUT5VOUT4VOUT3VOUT2VOUT1
SGND
GND37GND36GND35GND34GND33GND32GND31GND30
PGOOD
GND29GND28GND27GND26
GND25GND24GND23GND22
VFB
GND21GND20GND19GND18GND17GND16GND15GND14
DRVCC
GND13GND12GND11GND10GND9GND8GND7
MARG1
GND6GND5GND4GND3GND2GND1
MARG0
FSET
VIN12VIN11VIN10VIN9VIN8VIN7
MPGM
COMP
RUN
TRACK/SS
PLLIN
INTVCC
VIN6VIN5VIN4VIN3VIN2VIN1
VDD_PEA, 1.0V
PLACE CLOSE TO U1
ROUTE AS POWER NET OR ISLAND
PLACE R562 & R563 CLOSE TO U60, NOISE-FREE ROUTINGPLACE R564 & R565 CLOSE TO U1, NOISE-FREE ROUTING
8%
4%
2%
1%
PLACE W35 CLOSE TO J115
MARGINING CONTROL
------------------------------
HIGH | HIGH | NO MARGIN
------------------------------------------------------------
------------------------------
LOW | LOW | NO MARGIN
HIGH | LOW | MARGIN DOWN
MARG1 | MARG0 | MODE
LOW | HIGH | MARGIN UP
Tue Apr 20 12:38:24 2010 SHEET 24 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
1
J115
FB7
C429
C430
C428
C426C4
25
C424
C423
C422
C421
R564R565
C420
R562R563
R561
C419
R560
TP45
R552
R551
C418
R559
TP46W3
5
C417
R553
R555
R554
R556R557
C415
C414
R139
4R1
393
768594103112121
S7
R558
L12
J9J8J7J6J5
M11M10M9M8
J4
M7M6M5M4M3M2M1L11L10L9
J3
L8L7L6L5L4L3L2L1K11K10
J2
K9K8K7K6K5K4K3K2K1J10
J1
J12M12
B3B2B1A6A5A4A3A2
C6C5C4C3C2C1B6B5B4
A1
F12
A9
H12
A10
A8
G12
A12
D12C12
A7
E3E2E1D6D5
H9
D4
H8H7H6H5H4H3H2H1G9G8
D3
G7G6G5G4
G3G2G1F9F8F7
D2
F6F5F4F3F2F1E7E6E5E4
D1
B12
E12
K12
A11
U62 POWER REGULATOR - VDDPEA
PS_PEA_CTRL3
PS_PEA_CTRL0PS_PEA_CTRL1PS_PEA_CTRL2
PS_PEA_MARG1PS_PEA_MARG0
REG_1V0_PEA
1.96M
1.96M1.96M
487K
487K487K
DNP
10K
10K DNP
+3V3
100K
100K
10UF
10UF
+3V3
DNP
+12V3_PS
1%12
7K
0.01
UF
1%31
6K
191K
100P
F
16V
100U
F
00
47UF
47UF
47UF
47UF
1.0U
F
00
1.0U
F
0.1U
F
26NH6.5A
10UF
1.0U
F
+1V0_PEA
RED
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
SM_SW6S1A
S6BS5BS4BS3BS2BS1B
S6AS5AS4AS3AS2A
CONN BANANA
LTM4603
GND40GND39GND38
VIN18VIN17VIN16VIN15VIN14VIN13
VOSNSN
VOUT43VOUT42VOUT41VOUT40VOUT39VOUT38VOUT37VOUT36VOUT35VOUT34VOUT33
VOUT_LCL
VOUT32VOUT31VOUT30VOUT29VOUT28VOUT27VOUT26VOUT25VOUT24VOUT23VOUT22
DIFFVOUT
VOUT21VOUT20VOUT19VOUT18VOUT17VOUT16VOUT15VOUT14VOUT13VOUT12VOUT11
VOSNSP
VOUT10VOUT9VOUT8VOUT7VOUT6VOUT5VOUT4VOUT3VOUT2VOUT1
SGND
GND37GND36GND35GND34GND33GND32GND31GND30
PGOOD
GND29GND28GND27GND26
GND25GND24GND23GND22
VFB
GND21GND20GND19GND18GND17GND16GND15GND14
DRVCC
GND13GND12GND11GND10GND9GND8GND7
MARG1
GND6GND5GND4GND3GND2GND1
MARG0
FSET
VIN12VIN11VIN10VIN9VIN8VIN7
MPGM
COMP
RUN
TRACK/SS
PLLIN
INTVCC
VIN6VIN5VIN4VIN3VIN2VIN1
VDD_PEHA, 2.5V
PLACE CLOSE TO U1
ROUTE AS POWER NET OR ISLAND
PLACE R580 & R581 CLOSE TO U63, NOISE-FREE ROUTINGPLACE R582 & R583 CLOSE TO U1, NOISE-FREE ROUTING
PLACE W36 CLOSE TO J116
------------------------------------------------------------
LOW | LOW | NO MARGINMARG1 | MARG0 | MODE
LOW | HIGH | MARGIN UP
8%
4%
2%
1%
HIGH | HIGH | NO MARGIN
------------------------------------------------------------
HIGH | LOW | MARGIN DOWN
MARGINING CONTROL
Tue Apr 20 12:38:24 2010 SHEET 25 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
C447
1J116
C446
FB8
C445
C443C4
42
C441
C440
C439
C438
TP49
R582R583R581
R580
C435
C437
R579R5
78
R577
C436
TP50
C434
L12
J9J8J7J6J5
M11M10M9M8
J4
M7M6M5M4M3M2M1L11L10L9
J3
L8L7L6L5L4L3L2L1K11K10
J2
K9K8K7K6K5K4K3K2K1J10
J1
J12M12
B3B2B1A6A5A4A3A2
C6C5C4C3C2C1B6B5B4
A1
F12
A9
H12
A10
A8
G12
A12
D12C12
A7
E3E2E1D6D5
H9
D4
H8H7H6H5H4H3H2H1G9G8
D3
G7G6G5G4
G3G2G1F9F8F7
D2
F6F5F4F3F2F1E7E6E5E4
D1
B12
E12
K12
A11
U65
C432
C431
R570
R569
W36
R139
6R1
395
R571R572
R573
R574R575
R576
768594103112121
S8
POWER REGULATOR - VDDPEHA
PS_PEHA_CTRL0PS_PEHA_CTRL1PS_PEHA_CTRL2PS_PEHA_CTRL3PS_PEHA_MARG1PS_PEHA_MARG0
REG_2V5_PEHA
1.96M
1.96M1.96M
487K
487K487K
DNP
10K
10K
+3V310
UF
10UF
100K
100K
DNP
DNP
+3V3
+12V3_PS
42.2
K
0.01
UF
34.8
K
DNP
00
00
100P
F
16V
100U
F
47UF
47UF
47UF
47UF
1.0U
F
1.0U
F
0.1U
F
10UF
1.0U
F
26NH6.5A
RED
+2V5_PEHA
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
CONN BANANA
LTM4603
GND40GND39GND38
VIN18VIN17VIN16VIN15VIN14VIN13
VOSNSN
VOUT43VOUT42VOUT41VOUT40VOUT39VOUT38VOUT37VOUT36VOUT35VOUT34VOUT33
VOUT_LCL
VOUT32VOUT31VOUT30VOUT29VOUT28VOUT27VOUT26VOUT25VOUT24VOUT23VOUT22
DIFFVOUT
VOUT21VOUT20VOUT19VOUT18VOUT17VOUT16VOUT15VOUT14VOUT13VOUT12VOUT11
VOSNSP
VOUT10VOUT9VOUT8VOUT7VOUT6VOUT5VOUT4VOUT3VOUT2VOUT1
SGND
GND37GND36GND35GND34GND33GND32GND31GND30
PGOOD
GND29GND28GND27GND26
GND25GND24GND23GND22
VFB
GND21GND20GND19GND18GND17GND16GND15GND14
DRVCC
GND13GND12GND11GND10GND9GND8GND7
MARG1
GND6GND5GND4GND3GND2GND1
MARG0
FSET
VIN12VIN11VIN10VIN9VIN8VIN7
MPGM
COMP
RUN
TRACK/SS
PLLIN
INTVCC
VIN6VIN5VIN4VIN3VIN2VIN1
SM_SW6S1A
S6BS5BS4BS3BS2BS1B
S6AS5AS4AS3AS2A
PLACE CLOSE TO U1
VDD_PETA, 1.0V
ROUTE AS POWER NET OR ISLAND
PLACE R598 & R599 CLOSE TO U66, NOISE-FREE ROUTINGPLACE R600 & R601 CLOSE TO U1, NOISE-FREE ROUTING
PLACE W37 CLOSE TO J117
4%
8%
1%
2%
MARGINING CONTROL
------------------------------------------------------------------------------------------------------------------------
LOW | HIGH | MARGIN UP
HIGH | HIGH | NO MARGIN
MARG1 | MARG0 | MODELOW | LOW | NO MARGIN
HIGH | LOW | MARGIN DOWN
Tue Apr 20 12:38:24 2010 SHEET 26 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
1J117
C463
C464
FB9
C462
C460
R588
R587
C449
C448
C459
C458
C457
R600R601
C456
C455
C454
R598R599
C452
TP53
TP54W3
7
C451
R597R5
96
C453
R595
L12
J9J8J7J6J5
M11M10M9M8
J4
M7M6M5M4M3M2M1L11L10L9
J3
L8L7L6L5L4L3L2L1K11K10
J2
K9K8K7K6K5K4K3K2K1J10
J1
J12M12
B3B2B1A6A5A4A3A2
C6C5C4C3C2C1B6B5B4
A1
F12
A9
H12
A10
A8
G12
A12
D12C12
A7
E3E2E1D6D5
H9
D4
H8H7H6H5H4H3H2H1G9G8
D3
G7G6G5G4
G3G2G1F9F8F7
D2
F6F5F4F3F2F1E7E6E5E4
D1
B12
E12
K12
A11
U68
R590R589
R591
R592R593
R594
R139
8R1
397
768594103112121
S10
POWER REGULATOR - VDDPETA
PS_PETA_CTRL0PS_PETA_CTRL1PS_PETA_CTRL2PS_PETA_CTRL3PS_PETA_MARG1PS_PETA_MARG0
REG_1V0_PETA
1.96M
1.96M1.96M
487K
487K487K
DNP
10K
10K
+3V3
10UF
10UF
DNP
DNP
100K
100K
+3V3
127K
1%
0.01
UF19
1K316K
1%
100U
F16
V
00 0
0
100P
F
47UF
47UF
47UF
47UF
1.0U
F
1.0U
F
0.1U
F
26NH6.5A
RED
10UF
1.0U
F
+1V0_PETA
+12V3_PS
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
CONN BANANA
SM_SW6S1A
S6BS5BS4BS3BS2BS1B
S6AS5AS4AS3AS2A
LTM4603
GND40GND39GND38
VIN18VIN17VIN16VIN15VIN14VIN13
VOSNSN
VOUT43VOUT42VOUT41VOUT40VOUT39VOUT38VOUT37VOUT36VOUT35VOUT34VOUT33
VOUT_LCL
VOUT32VOUT31VOUT30VOUT29VOUT28VOUT27VOUT26VOUT25VOUT24VOUT23VOUT22
DIFFVOUT
VOUT21VOUT20VOUT19VOUT18VOUT17VOUT16VOUT15VOUT14VOUT13VOUT12VOUT11
VOSNSP
VOUT10VOUT9VOUT8VOUT7VOUT6VOUT5VOUT4VOUT3VOUT2VOUT1
SGND
GND37GND36GND35GND34GND33GND32GND31GND30
PGOOD
GND29GND28GND27GND26
GND25GND24GND23GND22
VFB
GND21GND20GND19GND18GND17GND16GND15GND14
DRVCC
GND13GND12GND11GND10GND9GND8GND7
MARG1
GND6GND5GND4GND3GND2GND1
MARG0
FSET
VIN12VIN11VIN10VIN9VIN8VIN7
MPGM
COMP
RUN
TRACK/SS
PLLIN
INTVCC
VIN6VIN5VIN4VIN3VIN2VIN1
JTAG
BOOT EEPROMSOCKETED (52-298-000)
FUNDAMENTALRESET
A0-2 INTERNALLY PULLED DOWN
Tue Apr 20 12:38:25 2010 SHEET 27 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
TP61R6
46
R644
DS3
C491
R662R6
60
98765432
1413121110
1
J73
R661
872
56
431
U73
R642
C487
C489
R659
C499R6
58
4
51
3
2
U72
TP60
54
12
3
S3
R641
7
856
4
321
U77
R133
5
R133
3
R133
4
R651
R649
J71 6
6
6891011121368910111213
17
666
66
6 39
SSMBCLKSSMBDAT
MSMBCLKMSMBDAT
SATAIN_RSTN
MOMSW_RSTN
DUT_JTAG_TRST_NDUT_JTAG_TDIDUT_JTAG_TDODUT_JTAG_TMSDUT_JTAG_TCK
MAIN_RSTN1K
0603
5%
1K06
035%
+3V3
DNP
DNP
DNP
+3V3
+3V3
5%10
.0K
0603
+3V3
YEL
0603
1%DN
P
0.1U
F
06031K
5%
0.1U
F
0.1U
F
+3V3 +3V3
0603
5%1K
+3V3
0603
5%1K
SHROUDVERT-TH 2.54MM
1K06
035%
+3V3
1K5%
0603
+3V3
0.1U
F
RED
1K5%0603
+3V3
040210
K5%
YEL
+3V3
RESET, SMBUS, EEPROM, JTAG
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
INBI
OUT
OUT
BI
HDR_2x7
14131211109
8765
1 23 4
TLC7733D
GNDRESETN
RESETVCC
CTCONTROLSENSERESINN
OUTOUTINBIBI
SN74LVC1G125
OE_N VCC
YGND
A
NCSPDT_MOM
NO
COM
MTG2MTG1
A
B
24LC512SCL
A2A1A0
SDA
WP
GND
VCC
(GREEN) ACTIVE HIGH - DIP CLOCK
CLOCK
(GREEN) ACTIVE HIGH - DIP STK12CFG
(GREEN) ACTIVE HIGH - DIP STK03CFG
MODE
STK03CFG
(GREEN) ACTIVE HIGH - DIP MODE
STK12CFG
Tue Apr 20 12:38:26 2010 SHEET 28 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
TP8TP7
TP6TP4
TP3
DS126
DS125R819
R820
R821 DS127
DS129
DS130
DS131
DS132
R823
R824
R825
R826
R135
9R1
356
R135
3R1
350
R134
7R1
344
R134
1R1
338
54637281
S4
54637281
S5
R136
5R1
364
R136
6R1
367
DS109
R136
3R1
362
R136
1R1
360
R803
DS103
DS102R796
R797
910111213141516
87654321
SW10
DS104
DS105
DS106
R798
R799
R800
DS118
DS119
DS120
DS121
DS122
R812
R813
R814
R815
R816
DS110
DS111
DS112
DS114
DS113
DS116
DS115
R804
R805
R806
R807
R808
R809
R810
R135
7R1
354
R135
1
TP106
TP107
R135
8R1
355
R135
2
R134
2R1
345
R134
8
R133
6R1
339
R134
9R1
346
R134
3R1
340
R133
7
910111213141516
87654321
SW8
910111213141516
87654321
SW9
628
628
4 6 28
3 6 28
6 28
3 6 286 286 286 28
6 286 286 286 28
6 28
6 28
6 286 284 6 28
628
6 28
628
628
628
628
628
628
628
4628
4628
3628
3628
628
628
628
628
1728
628
628
628
628
628
1728
6 2817 286 28
17 28
6 286 286 286 28
DIP SWITCHES
150
STK2CFG2
STK2CFG3
1K1K1K1K1K1K1K1K
1K1K1K1K1K1K1K1K1K 1K 1K 1K 1K 1K 1K 1K
1K1K1K1K1K1K1K1K
DNPDNPDNP
SPARE6SPARE5SPARE4
STK3CFG0
DNPDNPDNP
SPARE3SPARE2
+3V3
SPARE1
STK2CFG0
STK3CFG4
+3V3
STK2CFG1STK2CFG2STK2CFG3STK2CFG4
150
SWMODE3SWMODE2SWMODE1SWMODE0
G3
G1
STK3CFG3STK3CFG2STK3CFG1
SPARE7 DNP SWMODE3
150
G2
G3
SWMODE0
SWMODE1
G1
SWMODE2
G2
150
150
150
GRN
GRN
GRN
GRN
YEL
150
150 YEL
YEL
STK3CFG4
STK3CFG0
STK3CFG1
STK2CFG1
STK2CFG0
STK3CFG2
STK3CFG3
STK2CFG4
GCLKFSEL
ICS_SSM
RSTHALT
SSMBADDR2
SSMBADDR1
CLKMODE1
CLKMODE0
ICS_FS
GCLKFSELICS_SSMRSTHALT
ICS_FS
SSMBADDR2SSMBADDR1CLKMODE1CLKMODE0
+3V3
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
150
150
GRN
GRN
GRN
150
150 GRN
GRN
150 GRN
+3V3
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUTOUTOUTOUT
OUTOUTOUT
OUT
DIPSW8
ONOFF
A1
A5A6A7A8
B1B2B3B4B5B6B7B8
A4A3A2
DIPSW8
ONOFF
A1
A5A6A7A8
B1B2B3B4B5B6B7B8
A4A3A2
OUT
OUT
OUTOUT
IN
IN
IN
IN
IN
IN
IN
OUTOUTOUT
OUTOUT
SM_SW4S1A
S4BS3BS2BS1B
S4AS3AS2A
SM_SW4S1A
S4BS3BS2BS1B
S4AS3AS2A
OUT
OUTOUT
OUT
OUTOUT
OUTOUT
DIPSW8
ONOFF
A1
A5A6A7A8
B1B2B3B4B5B6B7B8
A4A3A2
IN
IN
IN
IN
IN
IN
(GREEN) ACTIVE LOW - ATTENTION INPUT
(YELLOW) ACTIVE LOW - GPIO
PORT 0PORT 1
PORT 5PORT 4PORT 3PORT 2
PORT 6PORT 7PORT 8PORT 9PORT 10
PORT 0PORT 1
PORT 3PORT 4
PORT 2
PORT 5PORT 11 PORT 6PORT 12PORT 13
PORT 16PORT 15PORT 14
PORT 17PORT 18PORT 10PORT 20PORT 21PORT 22PORT 23
-----------------------------------8 | IOEXPINTN | P8ACTIVEN7 | FAILOVER2 | P8LINKUPN-----------------------------------5 | GPEN | P0ACTIVEN
-----------------------------------GPIO | ALT0 | ALT10 | PART0PERSTN | P16LINKUPN-----------------------------------1 | PART1PERSTN | P16ACTIVEN-----------------------------------2 | PART2PERSTN | P4LINKUPN-----------------------------------3 | PART3PERSTN | P4ACTIVEN----------------------------------------------------------------------4 | FAILOVER0 | P0LINKUPN
(YELLOW) ACTIVE LOW - PRESENCE DETECT
PORT 9PORT 8PORT 7
PORT 14PORT 13PORT 12PORT 11PORT 10
PORT 15PORT 16
PORT 23
PORT 21
PORT 19PORT 20
PORT 18PORT 17
PORT 22
Tue Apr 20 12:38:26 2010 SHEET 29 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
DS183
DS182
DS184
DS185
DS186
DS187
DS188
R876
R877
R878
R879
R880
R881
R882
DS189
DS190
DS191
DS192
DS193
DS194
DS195
DS196
DS197
DS198
R883
R884
R885
R886
R887
R888
R889
R890
R891
R892
TP88
TP87
DS406
DS409
DS408
DS407
DS411
DS410
DS414
DS413
R1368
R1371
R1370
R1369
R1373
R1372
R1376
R1375
DS159
DS158
DS162
DS161
DS160
DS163
DS164
DS167
DS165
DS166
DS168
DS169
R893 DS199DS170
DS200
DS201
DS202
DS203
DS204
DS205
R894
R895
R896
R897
R898
R899
DS172
DS171
DS173
DS174
DS175
DS176
DS177
DS178
DS179
DS180
DS181
TP86
TP85
TP84
TP83
TP82
TP81
TP80
R852
R853
R854
R855
R856
R857
R858
R859
R860
R861
R862
R863
R864
R865
R866
R867
R868
R869
R870
R871
R872
R873
R874
R875
8
9
8
9
8
8
9
8
9
10
9
10
10
9
10
10
10
9
10
8
8
10
9
8
6
6
6
6
6
6
6
68910111213
6
837
937
837
937
837
937
837
3837
1037
1037
937
1037
4837
1037
937
4837
1037
937
1037
3837
1037
937
1037
937
P2_APNP1_APNP0_APN
P3_APNP4_APN
P6_APNP5_APN
P8_APNP7_APN
P9_APNP10_APNP11_APN
P21_APN
P18_APNP19_APN
P17_APN
P13_APNP14_APNP15_APNP16_APN
P12_APN
P23_APNP22_APN
P20_APN
GPIO4
GPIO1
GPIO2
GPIO0
GPIO3
GPIO5
GPIO6
GPIO8_IOEXPINTN
GPIO7
P0_PDNP1_PDNP2_PDNP3_PDNP4_PDNP5_PDNP6_PDN
P8_PDN
P19_PDN
P13_PDNP14_PDNP15_PDNP16_PDNP17_PDNP18_PDN
P20_PDNP21_PDNP22_PDNP23_PDN
P12_PDN
P9_PDNP10_PDNP11_PDN
P7_PDN
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
YEL
YEL
YEL
YEL
YEL
YEL
YEL
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
150
150
150
150
150
150
YEL
YEL
YEL
YEL
YEL
YEL
ORG YEL150
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
+3V3
150
150
150
150
150
150
150
150
YEL
YEL
YEL
YEL
YEL
YEL
YEL
YEL
YEL
YEL +3V3
150
150
150
150
150
150
150
150
150
150
YEL
YEL
YEL
YEL
YEL
YEL
YEL
YEL
YEL
YEL
150
150
150
150
150
150
150
YEL
YEL
YEL
YEL
YEL
YEL
YEL
+3V3
LED - PORT STATUS (1 OF 7)
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
(RED) ACTIVE LOW - POWER FAULT
PORT 22PORT 23
PORT 21
PORT 1PORT 2
PORT 6PORT 7
PORT 5PORT 4
PORT 8
PORT 10
PORT 3
PORT 18
PORT 9
PORT 11PORT 12PORT 13PORT 14PORT 15PORT 16
PORT 20PORT 10
PORT 17
PORT 0
PORT 6
PORT 3PORT 2
PORT 4
PORT 1
PORT 5
PORT 0
PORT 7
(GREEN) ACTIVE LOW - POWER GOOD
PORT 22PORT 23
PORT 10PORT 18PORT 17
PORT 20PORT 21
PORT 16PORT 15PORT 14PORT 13PORT 12
PORT 8PORT 9PORT 10PORT 11
Tue Apr 20 12:38:27 2010 SHEET 30 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
DS29
DS31
DS30
DS32
DS34
DS33
DS37
DS36
DS35
DS39
DS38
DS42
DS41
DS40
DS44
DS43
R687
R688
R689
R690
R691
R692
R695
R694
R693
R696
R697
R700
R698
R699
R701
R702
R703 DS45
DS47
DS46
DS49
DS48
DS50
DS51
DS52
R704
R705
R706
R707
R708
R710
R709
DS5
DS7
DS6
DS8
DS10
DS9
DS13
DS12
DS11
DS15
DS14
DS18
DS16
DS17
DS19
DS20
R663
R664
R665
R666
R667
R668
R669
R670
R671
R672
R673
R675
R674
R676
R677
R678
R679 DS21
DS23
DS22
DS25
DS24
DS26
DS28
DS27
R680
R681
R682
R683
R684
R685
R686837
937
837
837
937
837
937
937
81437
1037
937
1037
1037
81437
1037
937
81537
1037
937
1037
81537
937
1037
1037
837
937
837
937
837
937
837
937
81537
1037
81437
1037
937
81437
1037
937
1037
1037
81537
937
1037
1037
937
1037
P0_PFN
P5_PFNP6_PFN
P4_PFN
P1_PFNP2_PFNP3_PFN
P7_PFNP8_PFNP9_PFNP10_PFNP11_PFN
P13_PFNP12_PFN
P15_PFNP14_PFN
P20_PFNP19_PFNP18_PFNP17_PFNP16_PFN
P22_PFNP23_PFN
P21_PFN
P0_PWRGDN
P3_PWRGDNP4_PWRGDNP5_PWRGDNP6_PWRGDN
P1_PWRGDNP2_PWRGDN
P7_PWRGDN
P16_PWRGDN
P11_PWRGDN
P8_PWRGDNP9_PWRGDNP10_PWRGDN
P12_PWRGDNP13_PWRGDNP14_PWRGDNP15_PWRGDN
P17_PWRGDN
P20_PWRGDN
P18_PWRGDNP19_PWRGDN
P23_PWRGDNP22_PWRGDNP21_PWRGDN
1K
1K
1K
1K
1K
1K
1K
RED
RED
RED
RED
RED
RED
RED
RED1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
+3V3
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
+3V3
LED - PORT STATUS (2 OF 7)
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
(ORANGE) ACTIVE LOW - ATTENTION OUTPUT
PORT 1PORT 2
PORT 0
PORT 3
PORT 11
PORT 7
PORT 12
PORT 10PORT 9
PORT 6PORT 5
PORT 8
PORT 4
PORT 13
PORT 15PORT 14
PORT 16
PORT 20
PORT 17PORT 18PORT 10
PORT 21
PORT 23PORT 22
PORT 1PORT 0
PORT 2PORT 3PORT 4
PORT 6PORT 5
PORT 7PORT 8
(GREEN) ACTIVE LOW - POWER INDICATOR
PORT 11
PORT 9PORT 10
PORT 12PORT 13
PORT 15PORT 14
PORT 16PORT 17PORT 18
PORT 22PORT 23
PORT 20PORT 10
PORT 21
Tue Apr 20 12:38:27 2010 SHEET 31 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
DS231
DS230
DS232
DS233
DS234
DS237
DS235
DS236
DS238
DS239
DS240
DS241
DS242
DS243
DS244
R924
R926
R925
R927
R928
R929
R930
R931
R932
R933
R934
R935
R936
R937
R938
R939 DS245
DS247
DS246
DS250
DS249
DS248
DS252
DS251
DS253
R940
R941
R942
R944
R943
R945
R946
R947
DS206
DS207
DS208
DS209
DS210
DS213
DS211
DS212
DS215
DS214
DS216
DS218
DS217
DS220
DS219
R900
R901
R902
R903
R904
R905
R906
R907
R908
R909
R910
R911
R912
R913
R914
R915 DS221
DS223
DS222
DS224
DS225
DS226
DS228
DS227
DS229
R916
R917
R918
R919
R920
R921
R922
R923
8
9
8
9
9
8
9
8
8
9
10
10
9
9
10
10
10
8
10
8
10
8
9
10
8
9
8
9
9
8
8
9
8
8
10
9
8
10
9
10
10
9
10
8
10
9
10
10
P4_AINP5_AINP6_AINP7_AIN
P3_AINP2_AINP1_AINP0_AIN
P8_AIN
P10_AIN
P23_AIN
P21_AINP22_AIN
P14_AINP13_AIN
P15_AIN
P17_AINP16_AIN
P19_AIN
P12_AINP11_AIN
P20_AIN
P18_AIN
P9_AIN
P6_PINP7_PIN
P4_PINP5_PIN
P3_PIN
P0_PIN
P2_PINP1_PIN
P8_PIN
P16_PINP17_PINP18_PIN
P12_PINP13_PINP14_PINP15_PIN
P11_PINP10_PINP9_PIN
P20_PINP21_PINP22_PINP23_PIN
P19_PIN
1K
1K
1K
1K
1K
1K
1K
1K
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
ORG
+3V3
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
+3V3
LED - PORT STATUS (3 OF 7)
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PORT 23
PORT 10
PORT 22
PORT 20PORT 21
PORT 18
PORT 13PORT 12
PORT 10
PORT 14PORT 15PORT 16PORT 17
PORT 11
PORT 9PORT 8
PORT 3PORT 4PORT 5
PORT 7PORT 6
(RED) ACTIVE LOW - HP SLOT RST
PORT 2
PORT 0PORT 1
PORT 20PORT 10
PORT 22PORT 23
PORT 21
PORT 18
PORT 9PORT 10
PORT 12PORT 11
PORT 15PORT 14
PORT 16PORT 17
PORT 13
PORT 8
PORT 3
PORT 5PORT 4
PORT 6
PORT 0
PORT 7
PORT 1PORT 2
(GREEN) ACTIVE HIGH - POWER ENABLE
Tue Apr 20 12:38:28 2010 SHEET 32 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
DS77
DS78
DS79
DS80
DS81
DS82
DS83
DS84
DS85
DS86
DS87
DS89
DS88
DS90
DS92
DS91
DS94
DS93
DS95
DS96
DS97
R735
R736
R737
R738
R739
R740
R741
R742
R743
R744
R745
R746
R747
R748
R749
R750
R751
R752
R753
R754
R755
R756 DS98
DS100
DS99R757
R758
DS53R711
DS54
DS55
DS56
DS57
DS58
DS61
DS60
DS59
DS62
DS63
DS66
DS65
DS64
DS68
DS67
DS71
DS70
DS69
DS73
DS72
R712
R713
R714
R715
R716
R717
R718
R719
R720
R721
R722
R723
R724
R725
R726
R728
R727
R729
R730
R731
R732 DS74
DS76
DS75
R734
R733937
837
837
1037
837
937
937
837
81537
1037
1037
937
937
1037
1037
81537
81437
81437
1037
937
937
1037
1037
937
91316
81316
81316
91316
81316
101316
101316
91316
81316
101316
91316
101316
101316
101316
81316
101316
91316
81316
91316
81316
91316
81316
91316
101316
P1_PEPP0_PEP
P2_PEP
P9_PEP
P4_PEPP5_PEP
P7_PEPP6_PEP
P16_PEPP17_PEP
P19_PEPP18_PEP
P22_PEPP23_PEP
P21_PEPP20_PEP
P12_PEP
P8_PEP
P11_PEPP10_PEP
P14_PEPP15_PEP
P13_PEP
P3_PEP
P1_RSTNP0_RSTN
P2_RSTN
P10_RSTN
P16_RSTNP17_RSTN
P19_RSTNP18_RSTN
P20_RSTNP21_RSTNP22_RSTN
P15_RSTN
P9_RSTN
P11_RSTNP12_RSTNP13_RSTNP14_RSTN
P8_RSTNP7_RSTNP6_RSTNP5_RSTNP4_RSTNP3_RSTN
P23_RSTN
150
150
GRN
GRN
GRN150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
150 GRN
1K
1K RED
RED
RED1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
+3V3
LED - PORT STATUS (4 OF 7)
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PORT 23
PORT 21PORT 20
PORT 22
PORT 10PORT 18PORT 17PORT 16PORT 15
PORT 11PORT 12
PORT 14PORT 13
PORT 10PORT 9
PORT 6PORT 7PORT 8
PORT 5
(RED) ACTIVE LOW - MRL
PORT 1PORT 0
PORT 2PORT 3PORT 4
PORT 20PORT 21
PORT 23PORT 22
PORT 15PORT 16PORT 17PORT 18PORT 10
PORT 13PORT 14
PORT 11PORT 12
PORT 10PORT 9
PORT 7
PORT 5
PORT 8
PORT 6
(GREEN) ACTIVE HIGH - INTERLOCK INPUT
PORT 3PORT 2PORT 1PORT 0
PORT 4
Tue Apr 20 12:38:28 2010 SHEET 33 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
DS278
DS279
DS280
DS281
DS282
DS283
DS284
DS286
DS285
DS287
DS288
DS289
DS290
DS291
DS292
DS293
DS294
DS295
DS296
R972
R973
R974
R975
R976
R977
R978
R979
R980
R981
R982
R983
R984
R985
R986
R987
R988
R989
R990
DS297
DS298
DS299
DS300
DS301
R991
R992
R993
R994
R995
DS254
DS255
DS256
DS257
DS259
DS258
DS262
DS261
DS260
DS264
DS263
DS267
DS265
DS266
DS268
DS269
DS272
DS270
DS271
R948
R949
R950
R951
R952
R953
R954
R955
R956
R957
R958
R959
R960
R961
R962
R963
R964
R965
R966
DS273
DS274
DS275
DS277
DS276
R967
R968
R969
R970
R97111
11
11
11
11
12
11
12
11
12
11
12
11
12
12
11
11
12
11
12
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
P0_ILOCKST
P4_ILOCKSTP3_ILOCKSTP2_ILOCKSTP1_ILOCKST
P23_ILOCKSTP22_ILOCKSTP21_ILOCKSTP20_ILOCKST
P17_ILOCKSTP16_ILOCKSTP15_ILOCKSTP14_ILOCKSTP13_ILOCKST
P19_ILOCKSTP18_ILOCKST
P12_ILOCKSTP11_ILOCKSTP10_ILOCKSTP9_ILOCKSTP8_ILOCKSTP7_ILOCKSTP6_ILOCKSTP5_ILOCKST
P0_MRLN
P3_MRLNP2_MRLNP1_MRLN
P4_MRLN
P10_MRLNP11_MRLN
P15_MRLN
P20_MRLNP21_MRLNP22_MRLNP23_MRLN
P16_MRLNP17_MRLNP18_MRLNP19_MRLN
P14_MRLNP13_MRLNP12_MRLN
P8_MRLNP9_MRLN
P5_MRLNP6_MRLNP7_MRLN
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
1K
1K
1K
1K
1K
RED
RED
RED
RED
RED
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
RED
+3V3
LED - PORT STATUS (5 OF 7)
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PORT 0PORT 1
(GREEN) ACTIVE HIGH - INTERLOCK OUTPUT
(RED) ACTIVE LOW - PARTITION FUND. RESET
PORT 4
PORT 2PORT 3
PORT 5PORT 6
PORT 8
PORT 10PORT 9
PORT 7
PORT 11
PORT 13PORT 14
PORT 12
PORT 15PORT 16
PORT 18
PORT 21PORT 20PORT 10
PORT 17
PORT 22PORT 23
PART 0
PART 2PART 1
PART 3
PART 7PART 6PART 5PART 4
(RED) ACTIVE LOW - SLOT HEADER RESET
SLOT 8SLOT 12SLOT 16SLOT 20
Tue Apr 20 12:38:28 2010 SHEET 34 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
DS415
DS416
DS417
DS418
R1651
R1650
R1652
R1653
DS326
DS327
DS328
DS329
R1021
R1020
R1022
R1023
DS330
DS331
DS332
DS333
DS302
DS303
R1024
R1025
R1026
R1027
R996
R997
DS304
DS305
DS306
DS307
DS308
DS309
DS310
DS311
DS312
DS313
R998
R999
R1000
R1001
R1002
R1003
R1004
R1005
R1006
R1007
DS314
DS315
DS316
DS317
DS318
DS319
DS320
DS321
DS322
DS323
R1008
R1009
R1010
R1011
R1012
R1013
R1014
R1015
R1016
R1017
DS324R1018
DS325R101911
11
363839
11
1338
1338
1338
1338
1338
1338
1338
1338
11
11
12
12
11
11
11
11
11
12
11
12
11
12
11
12
11
12
12
11
11
463839
363839
463839
P0_ILOCKP
P3_ILOCKP
SLOT_HDR_RSTN8
P1_ILOCKP
PART3_PERSTNPART2_PERSTN
PART6_PERSTNPART7_PERSTN
PART1_PERSTNPART0_PERSTN
PART4_PERSTNPART5_PERSTN
P4_ILOCKP
P10_ILOCKPP9_ILOCKP
P11_ILOCKP
P8_ILOCKPP7_ILOCKPP6_ILOCKPP5_ILOCKP
P12_ILOCKPP13_ILOCKPP14_ILOCKPP15_ILOCKP
P20_ILOCKPP21_ILOCKPP22_ILOCKPP23_ILOCKP
P18_ILOCKPP17_ILOCKP
P19_ILOCKP
P16_ILOCKP
P2_ILOCKP
SLOT_HDR_RSTN16SLOT_HDR_RSTN12
SLOT_HDR_RSTN20
150 GRN
150 GRN
150
150
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
150
150
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
150
150
1K
1K
1K
1K
GRN
GRN
RED
RED
RED
RED
1K
1K
1K
1K
RED
RED
RED
RED
+3V3
1K
1K
1K
1K
RED
RED
RED
RED
+3V3
LED - PORT STATUS (6 OF 7)
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
(GREEN) ACTIVE LOW - LINK UP
PORT 10PORT 18PORT 17
PORT 20PORT 21
PORT 23PORT 22
PORT 16PORT 15PORT 14
PORT 12PORT 13
PORT 11PORT 10PORT 9PORT 8PORT 7
PORT 5PORT 6
PORT 4PORT 3PORT 2PORT 1PORT 0
PORT 7PORT 6PORT 5PORT 4
PORT 2PORT 3
PORT 0PORT 1
PORT 8
(BLUE) ACTIVE LOW - LINK ACTIVITY
PORT 15PORT 16PORT 17PORT 18PORT 10PORT 20PORT 21PORT 22PORT 23
PORT 14
PORT 11PORT 10PORT 9
PORT 13PORT 12
Tue Apr 20 12:38:29 2010 SHEET 35 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
DS358
DS359
DS360
DS361
DS362
R1196
R1197
R1198
R1199
R1200
DS363
DS364
DS365
DS366
DS367
R1201
R1202
R1203
R1204
R1205
DS370
DS369
DS368
DS372
DS371
R1206
R1207
R1208
R1209
R1210
R1211 DS373
DS374
DS375
DS377
DS378
DS376
R1212
R1213
R1214
R1215
R1216
DS379
DS380
DS381
R1217
R1218
R1219
DS334
DS335
DS336
DS337
DS338
DS339
DS340
DS341
DS342
DS343
DS344
DS345
DS346
DS347
DS348
R1172
R1173
R1174
R1175
R1176
R1177
R1178
R1179
R1180
R1181
R1182
R1183
R1184
R1185
R1186
R1187 DS349
DS350
DS351
DS352
DS353
DS354
DS355
DS356
DS357
R1188
R1189
R1190
R1191
R1192
R1193
R1194
R1195
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
P1_LINKUPN
P3_LINKUPNP2_LINKUPN
P7_LINKUPNP6_LINKUPNP5_LINKUPNP4_LINKUPN
P0_LINKUPN
P8_LINKUPN
P10_LINKUPNP9_LINKUPN
P18_LINKUPN
P16_LINKUPNP15_LINKUPNP14_LINKUPN
P11_LINKUPN
P17_LINKUPN
P12_LINKUPNP13_LINKUPN
P19_LINKUPNP20_LINKUPNP21_LINKUPNP22_LINKUPNP23_LINKUPN
P0_ACTIVENP1_ACTIVENP2_ACTIVENP3_ACTIVENP4_ACTIVENP5_ACTIVENP6_ACTIVENP7_ACTIVENP8_ACTIVEN
P23_ACTIVENP22_ACTIVENP21_ACTIVENP20_ACTIVENP19_ACTIVENP18_ACTIVENP17_ACTIVENP16_ACTIVENP15_ACTIVENP14_ACTIVEN
P12_ACTIVENP11_ACTIVENP10_ACTIVENP9_ACTIVEN
P13_ACTIVEN
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
GRN
+3V3
549R
549R
549R
BLUE
BLUE
BLUE
549R
549R
549R
549R
549R
BLUE
BLUE
BLUE
BLUE
BLUE
BLUE549R
549R
549R
549R
549R
549R
BLUE
BLUE
BLUE
BLUE
BLUE
549R
549R
549R
549R
549R
BLUE
BLUE
BLUE
BLUE
BLUE
549R
549R
549R
549R
549R
BLUE
BLUE
BLUE
BLUE
BLUE
+3V3
LED - PORT STATUS (7 OF 7)
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
MINIMUM POWER SUPPLY LOADS
Tue Apr 20 12:38:35 2010 SHEET 36 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R112
0
R111
6
R111
2
R110
8
R112
1
R111
7
R111
3
R110
9
R110
4
R110
0
R109
6
R109
2
R110
5
R110
1
R109
7
R109
3
R108
8
R108
4
R108
0
R107
6
R107
3
R108
9
R108
5
R108
1
R107
7
R107
4
R112
3
R112
2
R111
8
R111
4
R111
0
R110
6
R110
2
R109
8
R109
4
R109
0
R108
6
R108
2
R107
8
R103
8
R104
2
R103
4
R103
0
R107
0
R106
7
R106
4
R105
9
R105
5
R105
1
R107
1
R106
8
R106
5
R106
0
R105
6
R105
2
R104
7
R104
3
R103
9
R103
5
R103
1
R104
8
R104
4
R104
0
R103
6
R103
2
R106
2
R106
1
R105
7
R105
3
R104
9
R104
5
R104
1
R103
7
R103
3
MIN LOAD RESISTORS
1206
1%53
.612
06
1%53
.612
06
1206
53.6
1% 1%53
.612
06
1206
1%53
.6
1%12
0653
.6
1%12
0653
.6
1%53
.612
06
1%53
.612
06
+3V3_PS
+12V3_PS
+12V2_PS
+12V1_PS
715
1206
1% 1%71
512
06
1%71
512
06
1206
1%71
5
+3V3_PS
1%12
06715
1%71
512
06
1%71
512
06
1206715
1% 1%12
06715
+12V3_PS
715
1%12
06
1%12
06715
1%71
512
06
1%71
512
06
1%71
512
06 715
1%12
06
1%12
06715
+12V3_PS
1%12
06715
715
1206
1%
1206
1%71
5
715
1206
1%71
51%
1206 715
1206
1%
715
1%12
06
1%71
512
06 715
1206
1%1%71
512
06
+12V2_PS +12V2_PS
120612
41%
1206
1%12
4
124
1%12
06
1206
1%12
4
120612
41% 1%
124
1206 12
41%
1206
1206
1%12
4
120612
41%
120612
41%
120612
41% 1%
120612
4
1%12
412
06
+5V0_PS
715
1%12
06
+5V0_PS
120671
51%
120671
51%
120671
51%
715
1206
1%
+12V3_PS
715
1206
1%
+12V3_PS
1%12
06715
1%71
512
06
1%12
06715
1%71
512
06
1206
1%71
5
120671
51%
715
1206
1%
+5V0_PS
715
1%
1206
1%71
5
1%12
06715
1%12
06715
+12V3_PS
1%71
512
06
+12V2_PS +12V2_PS +12V2_PS
1%71
512
06
1%71
512
06
120671
51% 1%
120671
5
1%12
06715
1%71
512
06
1206
1%71
5
1%71
512
06IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
PLACE SWITCHES NEAR J43-J48 CONNECTORS
PORTS 4,5,6,7
PORTS 19,18,17,16
PORTS 8,9,10,11
WAKEN
PWR_FLTN
WAKEN
CLOCK_ENABLEN
SLOT_RESETNCARD_PRESENTN
POWERGOOD
CABLE SENSEPS_ENABLEN
CLOCK_ENABLEN
PWR_FLTNPWR_ENABLE
PWR_ENABLE
POWERGOOD
CARD_PRESENTNSLOT_RESETN
CABLE SENSEPS_ENABLEN
PORTS 23,22,21,20 PORTS 3,2,1,0
PORTS 12,13,14,15
Tue Apr 20 12:38:30 2010 SHEET 37 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R1237
98107116125134143152161
S13
R1261
R1260
R1262
R1263
R1264
R1265
R1267
R1266
R1268
R1269
987
60
6
59585756555453525150
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J47
R1270
R1271
R1272
R1273
R1274
R1275
R1240
R1241
R1242
R1243
R1244
R1245
R1247
R1246
R1248
987
60
6
59585756555453525150
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J45
R1249
R1250
R1251
R1252
R1254
R1253
R1255
R1276
R1277
987
60
6
59585756555453525150
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J48
R1256
R1257
987
60
6
59585756555453525150
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J46
98107116125134143152161
S15
R1220
R1221
R1223
R1222
R1224
R1225
R1227
R1226
R1228
R1229
R1230
R1231
R1232
R1234
R1233
R1235
987
60
6
59585756555453525150
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J43
R1236
987
60
6
59585756555453525150
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J44
98107116125134143152161
S14
10 3010 30
16
16 38 39
169 309 309 32
4 8 29
8 15 30
4 8 29
10 3210 3010 30
10 29
9 329 309 30
9 29
10 29
10 3010 3010 32
4 16
10 3210 3010 30
10 29
9 329 309 30
9 29
10 3210 3010 30
10 29
3 8 29
8 14 308 14 308 14 32
16 39
16 38 39
16
16
16 38 39
16
16 38 39
21 37
16 38 39
16
16
16 38 39
16 38 39
16
3 16
16 39
8 15 328 15 308 15 30
10 32
10 29
9 29
10 29
10 3010 3010 32
21 37
4 16
8 328 308 30
8 29
9 329 309 30
9 29
8 328 308 30
8 29
9 29
9 309 309 32
21 37
16
16 39
16 38 39
16
16 38 39
10 3210 3010 30
10 29
9 329 309 30
9 29
10 3210 3010 30
10 29
3 8 29
8 14 308 14 308 14 32
21 37
16 38 39
16
16
16 38 39
16
16 38 39
3 16
16 39
16 38 39
16
16 38 39
16
16 38 39
16
9 329 309 30
9 29
8 328 308 30
8 29
9 329 309 30
9 29
8 29
8 308 308 32
16 38 39
21 37
16 38 39
16
16
16 38 39
16
16 38 39
16 38 39
16
21 37
8 15 328 15 30
SIDEBAND CONNECTORS
P17_PFNP17_PWRGDN
SLOT_WAKEN17
SLOT_RSTN17
SLOT_WAKEN18P18_PWRGDN
P18_PFNP18_PEP
VERT
P16_PDN
P7_CLK_ENP6_CLK_ENP5_CLK_ENP4_CLK_ENP3_CLK_ENP2_CLK_ENP1_CLK_EN
P15_CLK_ENP14_CLK_ENP13_CLK_ENP12_CLK_ENP11_CLK_ENP10_CLK_EN
P9_CLK_ENP8_CLK_EN
P20_PWRGDN
P20_PDN
P21_CLK_ENP21_PEPP21_PFN
P21_PWRGDN
P21_PDN
P22_CLK_ENP22_PEPP22_PFN
P22_PWRGDN
P22_PDN
P23_PDN
P23_PWRGDNP23_PFNP23_PEP
P23_CLK_EN
SLOT_WAKEN20
P11_CLK_ENP11_PEPP11_PFN
P11_PWRGDN
P11_PDN
P10_CLK_ENP10_PEPP10_PFN
P10_PWRGDN
P10_PDN
P9_CLK_ENP9_PEPP9_PFN
P9_PWRGDN
P9_PDN
P8_PDN
P8_PWRGDNP8_PFNP8_PEP
P8_CLK_EN
SLOT_RSTN20
SLOT_RSTN21
SLOT_WAKEN21
SLOT_WAKEN22
SLOT_RSTN22
SLOT_WAKEN23
SLOT_RSTN23
PS_ENABLEN
SLOT_RSTN11
SLOT_WAKEN11
SLOT_WAKEN10
SLOT_RSTN10
SLOT_RSTN9
SLOT_WAKEN9
SLOT_WAKEN8
SLOT_RSTN8
P23_CLK_ENP22_CLK_ENP21_CLK_ENP20_CLK_ENP19_CLK_ENP18_CLK_ENP17_CLK_ENP16_CLK_EN
P16_CLK_ENP16_PEPP16_PFN
P16_PWRGDN
P17_CLK_ENP17_PEP
P17_PDN
P18_CLK_EN
P18_PDN
P19_PDN
P19_PWRGDNP19_PFNP19_PEP
P19_CLK_EN
PS_ENABLEN
SLOT_WAKEN16
P0_CLK_ENP0_PEPP0_PFN
P0_PWRGDN
P0_PDN
P1_CLK_ENP1_PEPP1_PFN
P1_PWRGDN
P1_PDN
P2_CLK_ENP2_PEPP2_PFN
P2_PWRGDN
P2_PDN
P3_PDN
P3_PWRGDNP3_PFNP3_PEP
P3_CLK_EN
PS_ENABLEN
SLOT_WAKEN0
SLOT_RSTN16
SLOT_RSTN18
SLOT_WAKEN19
SLOT_RSTN19
P15_CLK_ENP15_PEPP15_PFN
P15_PWRGDN
P15_PDN
P14_CLK_ENP14_PEPP14_PFN
P14_PWRGDN
P14_PDN
P13_CLK_ENP13_PEPP13_PFN
P13_PWRGDN
P13_PDN
P12_PDN
P12_PWRGDNP12_PFNP12_PEP
P12_CLK_EN
PS_ENABLEN
SLOT_RSTN15
SLOT_WAKEN15
SLOT_WAKEN14
SLOT_RSTN14
SLOT_WAKEN13
SLOT_RSTN13
SLOT_WAKEN12
SLOT_RSTN12
SLOT_RSTN0
SLOT_WAKEN1
SLOT_RSTN1
SLOT_WAKEN2
SLOT_RSTN2
SLOT_WAKEN3
P7_CLK_ENP7_PEPP7_PFN
P7_PWRGDN
P7_PDN
P6_CLK_ENP6_PEPP6_PFN
P6_PWRGDN
P6_PDN
P5_CLK_ENP5_PEPP5_PFN
P5_PWRGDN
P5_PDN
P4_PDN
P4_PWRGDNP4_PFNP4_PEP
P4_CLK_EN
SLOT_RSTN3
PS_ENABLEN
SLOT_RSTN7
SLOT_WAKEN7
SLOT_WAKEN6
SLOT_RSTN6
SLOT_WAKEN5
SLOT_RSTN5
SLOT_RSTN4
SLOT_WAKEN4
P0_CLK_EN
PS_ENABLENP20_CLK_EN
P20_PEPP20_PFN
VERTSHROUD0.050X0.1
100
VERTSHROUD0.050X0.1
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
VERT 0.050X0.1SHROUD
100
100
SHROUD0.050X0.1
100
100
100
100
100
100
100
100
100
0.050X0.1SHROUD
VERT
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
VERTSHROUD0.050X0.1
100
100
100
100
100
100
100
100
100
100
100
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
HDR_2x30
60585654525048464442403836343230282624222018
2468
10121416
59575553514947454341393735333129272523211917
13579
1311
15
INBI
OUTBI
OUTOUT
IN
HDR_2x30
60585654525048464442403836343230282624222018
2468
10121416
59575553514947454341393735333129272523211917
13579
1311
15
ININ
BIOUT
OUTBI
OUT
ININ
BIOUT
BIOUTOUT
ININ
BI
BIOUT
OUTOUT
IN
BIIN
OUT
OUTIN
OUTBI
ININ
HDR_2x30
60585654525048464442403836343230282624222018
2468
10121416
59575553514947454341393735333129272523211917
13579
1311
15
OUT
OUT
ININ
HDR_2x30
60585654525048464442403836343230282624222018
2468
10121416
59575553514947454341393735333129272523211917
13579
1311
15
OUTIN
BI
HDR_2x30
60585654525048464442403836343230282624222018
2468
10121416
59575553514947454341393735333129272523211917
13579
1311
15
OUTBI
OUT
INOUT
ININ
SM_SW8S1A
S8BS7BS6BS5BS4BS3BS2BS1B
S8AS7AS6AS5AS4AS3AS2A
SM_SW8S1A
S8BS7BS6BS5BS4BS3BS2BS1B
S8AS7AS6AS5AS4AS3AS2A
OUTOUT
BIOUT
BI
OUTBI
BIININ
INBI
IN
OUTOUT
OUT
OUTBI
INOUT
IN
OUTBI
OUTBI
OUT
INININ
BIOUT
IN
OUTIN
BIOUT
OUTOUT
BIOUT
BI
OUTBI
BI
IN
SM_SW8S1A
S8BS7BS6BS5BS4BS3BS2BS1B
S8AS7AS6AS5AS4AS3AS2A
IN
BIININ
OUTOUT
OUTOUT
BIOUT
BI
OUTBI
BIININ
INBI
INOUTOUT
OUT
OUTBI
INOUT
HDR_2x30
60585654525048464442403836343230282624222018
2468
10121416
59575553514947454341393735333129272523211917
13579
1311
15
IN
OUTOUT
BIOUT
BI
INININ
BIOUT
BIOUTOUT
ININBI
OUTBI
OUTOUT
ININBI
OUTBI
INBI
OUTOUT
IN
OUTBI
BIOUTOUT
ININBI
BIOUT
OUTOUT
IN
BIIN
OUTBI
OUTOUT
Tue Apr 20 12:38:35 2010 SHEET 38 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
TP143
TP144
TP145
TP146
TP147
TP148
TP149
TP11
3
9876543
20
2
19181716151413121110
1
J84
TP11
4
9876543
20
2
19181716151413121110
1
J85
TP11
5
9876543
20
2
19181716151413121110
1
J86
TP11
6
9876543
20
2
19181716151413121110
1
J87
TP150
TP135
TP136
TP10
9
9876543
20
2
19181716151413121110
1
J80
TP11
0
9876543
20
2
19181716151413121110
1
J81TP137
TP138
TP139
TP140
TP141
TP11
1
9876543
20
2
19181716151413121110
1
J82
TP11
2
9876543
20
2
19181716151413121110
1
J83
TP142
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 38 3916 37 38 3916 37 38 3916 37 38 39
16 37 3916 37 39
16 37 3916 37 394 6 34 38 394 6 34 38 393 6 34 38 393 6 34 38 39
16 37 3916 37 394 6 34 38 394 6 34 38 393 6 34 38 393 6 34 38 39
1334
1334
16 37 3916 37 394 6 34 38 394 6 34 38 393 6 34 38 393 6 34 38 39
16 37 3916 37 394 6 34 38 394 6 34 38 393 6 34 38 393 6 34 38 39
1334
1334
16 37 3916 37 394 6 34 38 394 6 34 38 393 6 34 38 393 6 34 38 39
4 6 34 38 39
3 6 34 38 39
4 6 34 38 39
1334
1334
1334
1334
4 6 34 38 39
3 6 34 38 393 6 34 38 39
4 6 34 38 393 6 34 38 39
16 37 3916 37 39
16 37 3916 37 39
3 6 34 38 39
4 6 34 38 39
3 6 34 38 39
4 6 34 38 39
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN6SLOT_RSTN4SLOT_RSTN2SLOT_RSTN0
SLOT_RSTN3SLOT_RSTN1
SLOT_RSTN7SLOT_RSTN5SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8
YEL
SLOT_RSTN23SLOT_RSTN22SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8
PART7_PERSTN
PART6_PERSTN
SLOT_RSTN21SLOT_RSTN19SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8
SLOT_RSTN18SLOT_RSTN17SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8
PART5_PERSTN
PART4_PERSTN
SLOT_RSTN15SLOT_RSTN14SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8
YEL
YEL
NO-SHROUDVERT_SM 2.0MM
YEL
NO-SHROUDVERT_SM 2.0MM
YEL
NO-SHROUDVERT_SM 2.0MM
YEL
NO-SHROUDVERT_SM 2.0MM
YEL
YEL
YEL
YEL
YEL
YEL
YEL
SLOT_HDR_RSTN20
SLOT_HDR_RSTN8
SLOT_HDR_RSTN16
PART1_PERSTN
PART2_PERSTN
PART3_PERSTN
PART0_PERSTN
SLOT_HDR_RSTN20
SLOT_HDR_RSTN12SLOT_HDR_RSTN8
SLOT_HDR_RSTN16SLOT_HDR_RSTN12
SLOT_RSTN9SLOT_RSTN10
SLOT_RSTN11SLOT_RSTN13
SLOT_HDR_RSTN12
SLOT_HDR_RSTN20
SLOT_HDR_RSTN8
SLOT_HDR_RSTN16
YEL
2.0MMVERT_SMNO-SHROUD
YEL
2.0MMVERT_SMNO-SHROUD
YEL
YEL
YEL
YEL
YEL
YEL2.0MMVERT_SMNO-SHROUD
YEL
2.0MMVERT_SMNO-SHROUD
YEL
YEL
PARTITION RESET SELECT HEADERS
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
IN
ININ
ININININ
INININ
ININ
IN
ININ
HDR_2x10
20191817161514131211109
8765
1 23 4
IN
INININ
IN
IN
HDR_2x10
20191817161514131211109
8765
1 23 4
HDR_2x10
20191817161514131211109
8765
1 23 4
OUT
OUT
HDR_2x10
20191817161514131211109
8765
1 23 4
HDR_2x10
20191817161514131211109
8765
1 23 4
OUT
OUT
IN
HDR_2x10
20191817161514131211109
8765
1 23 4
INININ
INININININ
OUT
IN
INININININ
IN
INININ
OUT
IN
HDR_2x10
20191817161514131211109
8765
1 23 4
HDR_2x10
20191817161514131211109
8765
1 23 4
ININ
OUT
INININININ
ININ
IN
OUT INININININININ
INININ
ININININ
ININ
INININ
IN
IN
INININ
ININ
ININ
IN
NOTE: DNP JUMPERS WHEN IOEXPANDER IS ENABLED
Tue Apr 20 12:38:36 2010 SHEET 39 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
TP13
3
9876543
2423222120
2
19181716151413121110
1
J133
9876543
2423222120
2
19181716151413121110
1
J134
TP12
1
98765432
121110
1
J129
TP12
2
98765432
121110
1
J130
TP12
3
98765432
121110
1
J131
TP12
4
98765432
121110
1
J132
16 37 3816 37 3816 37 3816 37 3916 37 3816 37 3816 37 3816 37 3916 37 3816 37 38
16 37 3916 37 38
16 37 3816 37 3816 37 3816 37 3916 37 3816 37 3816 37 3816 37 3816 37 3816 37 38
16 37 3816 37 38
62739 62739
204 6 34 38 393 6 34 38 393 6 34 38 39
6 27 3916 37 39
204 6 34 38 393 6 34 38 393 6 34 38 39
6 27 3916 37 39
204 6 34 38 394 6 34 38 393 6 34 38 39
6 27 3916 37 39
204 6 34 38 394 6 34 38 393 6 34 38 39
6 27 3916 37 39
62739 62739
46343839
36343839
46343839
36343839
SLOT RESET SELECT HEADERS
VERTNO
NOVERT 2.54MM
SLOT_RSTN23SLOT_RSTN22SLOT_RSTN21SLOT_RSTN20SLOT_RSTN19SLOT_RSTN18SLOT_RSTN17SLOT_RSTN16SLOT_RSTN15SLOT_RSTN14
SLOT_RSTN12SLOT_RSTN13
2.54MM
SLOT_RSTN11SLOT_RSTN10SLOT_RSTN9SLOT_RSTN8SLOT_RSTN7SLOT_RSTN6SLOT_RSTN5SLOT_RSTN4SLOT_RSTN3SLOT_RSTN2
SLOT_RSTN0SLOT_RSTN1
MAIN_RSTN
NO-SHROUDVERT-TH 2.54MM
S20_SATA_RSTNSLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8
MAIN_RSTNSLOT_RSTN20
NO-SHROUDVERT-TH 2.54MM
S16_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN12SLOT_HDR_RSTN8
MAIN_RSTNSLOT_RSTN16
NO-SHROUDVERT-TH 2.54MM
S12_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN8
MAIN_RSTNSLOT_RSTN12
NO-SHROUDVERT-TH 2.54MM
S8_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12
MAIN_RSTNSLOT_RSTN8
MAIN_RSTN
YEL
SLOT_HDR_RSTN16
SLOT_HDR_RSTN8
SLOT_HDR_RSTN20
SLOT_HDR_RSTN12
YEL
YEL
YEL
YEL
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUTOUTOUTOUT
OUTOUTOUTOUTOUTOUT
HDR_2x6
1211109
8765
1 23 4
HDR_2x6
1211109
8765
1 23 4
OUTOUT
OUTOUTOUTOUT
OUTOUT
OUTOUTOUTOUT
HDR_2x6
1211109
8765
1 23 4
HDR_2x6
1211109
8765
1 23 4
BI
BI
BI
BI
OUTOUT
OUTOUTOUTOUTOUTOUT
OUTOUT
OUT
OUTOUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
HDR_2x12
2423222120191817161514131211109
8765
1 23 4
IN
HDR_2x12
2423222120191817161514131211109
8765
1 23 4
IN
OUTOUT
NCNCNC
NC
Tue Apr 20 12:38:30 2010 SHEET 40 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
R143
0R1
427
R142
4
54637281
SW1
5 4
32
1
J95
5 4
32
1
J96
FB12
C702
C701
R1471
R146
4
R146
2
C700
C699
C698
C697
C696
TP99
R1472
R1475
R1474
R1473
R1466
R1467
R1468
R1469
R1470
C695
C694
R146
3
R146
1
9
8765
4
3332
31
30
3
29
28
27
2625
24
2322
21
20
2
19
18171615
14
13121110
1
U118
21
X4
C692
C693
R146
0
MTG2MTG1
7654321
J94
R148
2
R148
0
R147
8
R148
3
R148
1
R147
9
R147
7R1
476
R146
5
192020
4040
40
40
40
40
19
+3V3
+3V3
PORT 8 CLOCK GENERATOR
49.9
400MA120OHM
0805
1.0U
F
0.1U
F
5%10
0603
DNP
0402
1%1%DN
P04
02
10UF
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
10UF
16V
0402DN
P1%
1%
LP8_CLKNLS8_CLKPLS8_CLKN
22PF
22PF
P8_ICS_SSMP8_ICS_MR
4.7K
4.7K
4.7K
221789-0
CONNSMA
221789-0
CONNSMA
LSATA8_CLKPLSATA8_CLKNLSMA8_CLKPLSMA8_CLKN
475
DNP
10K
P8_ICS_SSM
P8_ICS_MR
P8_ICS_FSEL0
P8_ICS_FSEL0
LP8_CLKP
YEL33.2
33.2
33.233.2
33.2
33.2
33.233.2
33.2
49.9
49.9
49.9
49.9
49.9
49.9
49.9
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
SM_SW4S1A
S4BS3BS2BS1B
S4AS3AS2A
OUTOUTOUTOUT
ICS841484
REF_IN
XTAL_OUT
XTAL_IN
REF_SEL
FSEL0FSEL1
OE_REFOUTMR_nOEIREFSSM
GND
PGNDGNDGND
VDDVDDVDDVDD
REF_OUT
NC
VDDA
Q2
nQ0
BYPASS
NCNCNC
nQ3Q3
nQ2
nQ1Q1
Q0
12
IN
IN
IN
678005005
MTG2MTG1
7654321
OUTOUT
OUT
NCNCNC
NC
Tue Apr 20 12:38:31 2010 SHEET 41 OF 41
1.118-692-000
Derek Huang2010
Tony Tran
SCH-PESEB-002
EB-LOGAN-19
B
MTG2MTG1
7654321
J100
5 4
32
1
J101
5 4
32
1
J102
C724
C723
FB14
TP101
R153
0R1
531
R152
8
R152
6
R152
4
R152
9
R152
7
R152
5
C722
R1519
C721
C720
C719
C718
C717
C716
R1521
R1520
R1514
R1516
R1515
R151
2
R151
0R1
511
R150
9
R1522
R1523
R1517
R1518
9
8765
4
3332
31
30
3
29
28
27
2625
24
2322
21
20
2
19
18171615
14
13121110
1
U120
R151
3
R150
8
C7142
1
X6
C715
R143
1R1
428
R142
5
54637281
SW2
19
41
41
41
41
192020
4141
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
33.2
33.233.2
33.2
33.2
33.233.2
33.2
33.2
LP16_CLKP
P16_ICS_FSEL0
P16_ICS_FSEL0
475
P16_ICS_MR
10K
P16_ICS_SSM
DNP
DNP
1%
PORT 16 CLOCK GENERATOR
LSMA16_CLKNLSMA16_CLKPLSATA16_CLKNLSATA16_CLKP
221789-0
CONNSMA
221789-0
CONNSMA
LP16_CLKNLS16_CLKPLS16_CLKN
P16_ICS_SSMP16_ICS_MR
4.7K
4.7K
4.7K
+3V3
22PF
22PF
1%
1%DN
P04
0204
02DNP
1%
0402 16
V10
UF
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
060310
5%
10UF
YEL
0805120OHM
400MA
0.1U
F
1.0U
F
+3V3
IDT
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C)
3
SIZE REV.FAB P/N
1
1
A A
B B
C C
DD
2
2
4
45
6
67
7
8
38 5
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUTOUTOUT
SM_SW4S1A
S4BS3BS2BS1B
S4AS3AS2A
678005005
MTG2MTG1
7654321
OUTOUTOUTOUT
ICS841484
REF_IN
XTAL_OUT
XTAL_IN
REF_SEL
FSEL0FSEL1
OE_REFOUTMR_nOEIREFSSM
GND
PGNDGNDGND
VDDVDDVDDVDD
REF_OUT
NC
VDDA
Q2
nQ0
BYPASS
NCNCNC
nQ3Q3
nQ2
nQ1Q1
Q0
12
IN
IN
IN
