Yi-Lin, Tu 2013

IEE5011 –Fall 2013Memory Systems

Wide I/O High Bandwidth DRAM

Yi-Lin, TuDepartment of Electronics Engineering

National Chiao Tung Universityb22531423@hotmail.com

NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Outline IntroductionProximity CommunicationA Wide I/O DRAM ArchitectureConclusionReference

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Introduction

Memory gap How to solve this problem? Other techniques?

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity CommunicationA wireless chip-to-chip communication technology.Two chips are placed face to face and their bonding

pads are allowed to come within close proximity of each other without touching.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity Communication

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity CommunicationAdvantages

Increase I/O densityRemove the on/off chip wiresRemove the on-die terminationEase of testabilityRemove the ESD structures

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity CommunicationParallel plate capacitance

、、Channel

50 fF200 signals/20 times greater than normal DRAM

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity CommunicationChallenges

Mechanical misalignmentSupplying power to chipsThermal removal

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity Communication

Mechanical misalignmentSix axisMultiple source

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity Communication

Electronic sensorChip to chip separation sensorVernier scale(translation)

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Proximity Communication

Electronic re-alignmentUse receiver and transmitter array.This array has the ability to electrically reposition the

transmitter pads to align the transmitter and receiver pads.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

Using 4Gb DRAM as the starting point for developing a wide I/O DRAM architecture.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

Pad movingMoving the I/O channel to

the edge.Data and comment signals

will need to be buffered at the center.

Allows the local column circuitry to be moved to the center.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

CentralizingLimit the bandwidth of the

column and row path.It’s possible by using proximity

communication.Increase the array efficiency.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

Conventional DRAM chips operate with eight internal memory bank.

Enable eight wordlines to be active at once, one of each bank.

Possible to perform sequential column access to each bank.

Remove the large row access latency.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

512Mb bank structure4 possible arrangements for

creating a 512Mb memory bank.

Keep the global I/O metal lines short allows for a higher bandwidth on an open page.

C and D are preferred.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM ArchitectureChallenges

Number of metal layersGlobal I/O routingLocal I/O routing

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM ArchitectureNumber of metal layers and global I/O routing

A wide I/O architecture with 64 data pins operating with burst length of eight, and therefore a pre-fetch of 8n, requires 512 bits to be accessed in parallel.

The highest level of metal is used for global I/O routing and metal one is for global wordlines.

Increase the parasitic of each wordline.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

Divide the 8k page256 bits per half-bankThis enables a possibility of increasing the number of global

I/O tracks from 512 to 1024 or higher.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM Architecture

Local I/O routingThe large number of global I/O tracks requires 32 data

signals from each 256 kb memory array.Moving 32 data signals from the bitline sense amplifiers to

the global I/O track is a major challenge due to the limited routing space above the bitline sense amplifiers.

Signals can be routed to the top and bottom of each 256kb memory segment.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

A Wide I/O DRAM ArchitectureSummary

Developing a wide I/O DRAM architecture that is suitable for Proximity Communication requires the communication channel to be moved to the side of the DRAM chip.

A distributed page and bank structure was developed to enable the possibility of using Proximity Communication with 32 data pins.

Reaching the use of 64 data pins required architectural changes that would not increase the manufacturing cost compared to current DRAM architectures.

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NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Conclusion

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A DRAM architecture that uses proximity communication to increase the off-chip bandwidth while scaling the number of data pins.

Proximity communication allows for an increase of I/O density, ease of testability, removal of ESD structures and resistive termination.

Electrical sensors and electrical re-alignment techniques has enabled proximity communication to become a viable I/O technology.

The challenges of creating a wide I/O architecture were found to be in the global and local I/O routing.

NCTU IEE5011 Memory Systems 2013Yi-Lin, Tu

Reference Q. Harvard, “Wide I/O DRAM architecture utilizing proximity

communication,” Master’s thesis, Boise State University, December 2009.

Q. Harvard, R. J. Baker, and R. Drost, “Main memory with proximity communication: A wide I/O DRAM architecture,” in Proc. IEEE Workshop Microelectron. Electron Devices, Apr. 2010, pp. 1–4.

Harvard, Q., Baker, R.J., “A scalable I/O architecture for wide I/O DRAM,” 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 7-10 Aug. 2011, Seoul, 2011

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Yi-Lin, Tu 2013

Thank you

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