IEE5328 Nanodevice Transport Theory and Computational Tools
Prof. Ming-Jer ChenDept. Electronics EngineeringNational Chiao-Tung UniversityFeb. 27, 2013
Lecture 1:
Threshold Roll-Off, DIBL, and Subthreshold Swing
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A working nanoFET must meet the two SCE criteria in advance: 1. DIBL 2. Subthreshold Swing
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Top Priority
This constitutes the so-called well-defined nanoFET.
Short channel effect
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Polysilicon Gate Bulk Planar Extension• Strained Silicon Channel• Substrate/Channel Orientation
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High-k Metal Gate Bulk Planar Extension• Strained Silicon Channel• Substrate/Channel Orientation
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• Strained Silicon/Germanium/GaAs Channel• Substrate/Channel Orientation• Rsd issue
High-k Metal Gate FinFETs or Multi-Gate FETs
PlanarStructure
VerticalStructure
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TSMC 10, 14, and 16 nm
TSMC 20 nm
N+
P
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• You may use the ITRS roadmap to help determine a well-defined nanoFET
Or
• you may want to explain how ITRS roadmap was established
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High-Performance NanoFETs projected by ITRS 2011 (http://www.itrs.net)
(Bulk and SOI)
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High-Performance FETs projected by ITRS 2011 (http://www.itrs.net)
(Bulk and SOI)
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High-Performance FETs projected by ITRS 2011 (http://www.itrs.net)
(Multi-Gates and SOI)
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High-Performance FETs projected by ITRS 2011 (http://www.itrs.net)
(Multi-Gates and SOI)
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Low-Power NanoFETs projected by ITRS 2011 (http://www.itrs.net)
(Bulk, SOI, and Multi-Gates)
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Low-Power NanoFETs projected by ITRS 2011 (http://www.itrs.net)
(Bulk, SOI, and Multi-Gates)
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You have to do in this lecture: -Capture Advanced Device Physics through Lecture Notes
-Read some Good Papers on the Natural Length , a universal parameter and a DIBL penetration length due to depletion from drain
-Derive models and do calculations, given TCAD and/or experimental data --- Homework.
-Then you can be clear about how to make or select a well-defined nanoFET. 14IEE5328 Prof. MJ Chen NCTU
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Universal Curve
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