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IEEE 1687An Introduction

Dr. Martin Keim

Engineering Manager

Silicon Test Solutions

[email protected]

November 2015

mailto:[email protected]

2© Mentor Graphics Corporation

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Outline

◼ What is IEEE 1687 (IJTAG)?

◼ Value Proposition

◼ Technical Primer on IEEE 1687

◼ Delivering on the Value Proposition

◼ Q & A

IJTAG Introduction - Nordic Test Forum 2015 - [email protected]


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1687

IEEE 1687 (IJTAG) in a Nutshell

◼ IEEE 1687-2014 is an IP and pattern reuse methodology

◼ Born from test access and reuse needs— IP, block, core, die, die stack, system, board...

◼ Today— A general access methodology to embedded IP from any level of hierarchy.

◼ No new design requirements needed— Borrows the test access methodology, principles, and design already

introduced with IEEE 1149.1 and IEEE 1500.— Minimizes impact to designers, test engineers, and diagnosis engineers.— No-Risk initial engagement with IEEE 1687 technology


15001149.1


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TAP Access to Test Features & Growing Number of Disparate IP Blocks

BSR B

SR

BSR

BSR

SRAM

MEMBIST

interface BIST

Core logicLBISTCNTL

Scan chain

Scan chain

wrapped core

clockcontrol

tristatesafety

signaturesSerDes

Vdd droop

ring osc

temperature

termination

Performance monitors

debug

fuses

logic analyzer

soft repair

alternate IDCODE

PLL test/obs/config

isolation

assertion checks

analog muxes

noise generation

current monitor

Mbist selects

Mbist background

Parallelscan

State dump

Unit enables

memlock

scanreconfig

Courtesy of Jeff Rearick, AMD; from ETS 2012 presentation

Test Access Port (TAP)



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Challenge: Handling IP Diversity

你好

CiaoHola

Guten Tag

안녕하세요

BonjourIPIP

IP

IP

IP

IP

IP

IP

IP

IPIP

IP

IP

Hello

Test ToolsTest Tools Standardized communication interfacesenable faster integration, test and debug

- flexible – scalable – non-intrusive – low cost -

IJTAG(IEEE 1687)

こんにちは

Hello

Hello

IPIP

IP

IP

IP

IP

IP

IP

IP

IPIP

IP

IP

CiaoHola

Guten Tag

안녕하세요

BonjourHello

HelloHello

HelloHello

你好

Helloこんにちは



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Value Proposition of IEEE 1687

1. Reduced hardware and pattern cost (over 1149.1/1500)

2. One methodology to access IP from any source

3. Standardized but flexible for many IP interfaces

4. Enables automation –faster development, fewer errors, better results



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Reduced Costs

Faster to Working Patterns


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TECHNICAL INTRODUCTION TO IEEE 1687

IJTAG Introduction - Nordic Test Forum 2015 [email protected]


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IEEE 1149.1 / 1500 Use Model

◼ Recognized problem of access to embedded IP from different level

◼ Companies have developed technical solutions— BIST based test— 1149.1 / 1500 based

access methods

◼ Companies have developed business solutions

◼ Companies have to carry the costs of ‘their’ solution

Position where to define care and control bits& pattern sequence

TAP

TDO

TDI

TCK

TRST

BLOCK1

TDR

TAP

BLOCK2

WSP

TMS

en

unstructuredaccess

network

UserIngenuity

control

data


1500 tool


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IEEE 1687 Use Model

SI

SO

IP

IP

TDR

SI

SO

IP

IP

WSP

TAP

IEEE 1687

access

network

RetargetingUser defined

care bits

Patterns

The process of moving IP-level patterns to higher design level is called ‘retargeting’An IP with an IJTAG compliant interface is called ‘instrument’.

1687 does not touch the IP itself.

Temperature Sensor

Enable

Temp[3:0]

TDR

SI

SO



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ICL

ICL

IEEE 1687 Use Model

IEEE 1687 defines:

◼ Procedural Description Language (PDL)

— Describes IP usage at a given level— Facilitates automatic retargeting to

any higher level

◼ Instrument Connectivity Language (ICL)

— Describes only the (test) access / interface view of IP

— Abstracts from IP implementation— Describes partial or complete

networks

◼ Rules for 1687 IP realizations— Port functions, timing, connection— IJTAG does not require any new

hardware— Follows 1149.1 hardware rules

SI

SO

IP

IP

TDR

SI

SO

IP

IP

WSP

TAP

IEEE 1687

access

network


care bits in PDL

System-level

Integration

Verification

ATE

.v

STIL

PDL

ICL

ICL


This is a EDA Tool feature

(not mandated by IJTAG rules)


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ICL

ICL

IEEE 1687 Use Model

SI

SO

IP

IP

TDR

SI

SO

IP

IP

WSP

TAP

IEEE 1687

access

network


care bits in PDL

System-level

Integration

Verification

ATE

.v

STIL

PDL

ICL

ICL


Instrument Interfaces

◼ Serial access— Follows 1149.1 protocol— TDR, WSP, TAP, etc.

◼ Parallel access:— Read/write from data ports

◼ Bus access:— Supports read/write enable— Address/Data— PDL implements protocol

Same applies to top level access:— Serial (with/without TAP)— Parallel— Bus

Optional

(Not mandated)


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iProcsForModule TDR

iProc write_to_tdr { value } {

iNote "Writing '$value' to register R of module TDR"

iWrite R $value

iApply

}

iProc run_testX { } {

iCall write_to_tdr 0b10010110

iRunLoop 1000 -tck

iRead R 0xff

iApply

}

Example: A Test Data Register Controlled IP

Module TDR {

ScanInPort SI ;

ScanOutPort SO { Source R[0] ; }

ShiftEnPort SE ;

CaptureEnPort CE ;

UpdateEnPort UE ;

SelectPort EN ;

TCKPort TCK;

ScanRegister R[7:0] {

ScanInSource SI ;

}

}ICL

PDL

SI

SOTDR

RIP

• Ports have semantic

• Relative timing of events at ports is defined by 1687

• Objects like registers have built-in properties

• The IP itself is not modeled

• Looks like TCL

• Procedures are bound to modules

• Reading and writing only of care bits

• 1687 tool adds control bits

• 1687 tool takes care of the execution



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An Implementation of PDL Retargeting

SIB = Segment Insertion Bit— Used to enable/disable the inclusion of a

scan segment into the TDI/TDO path— Reconfigures the scan path on-the-fly— SIBs are not mandated by the IEEE 1687

standard

Signals:csu : capture enable

scan enableupdate enable

The depicted logic shall only serve as an example.1687 does not require any particular implementation as long as the IO protocol is served correctly.

SIB1

SIB2

en1

en2

TDO

TDI

en

3TCK

TRST

SI

SOInst1

Instrument

Instrument

R

SI

SOInst2

Instrument

Instrument

R

TMS

rst

TAP


enx

si

SIB

LAT

csuenrsttck

fso

so

s


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An Implementation of PDL Retargeting(from the top - not using IP Level Reuse – not using Data Abstraction)


User PDL:iWrite Inst1.R 0xfiApply

Retargeted PDL:iWrite Tap.IR[2:0] 0b001iApply

iWrite Sib1.S 0b1iWrite Sib2.S 0b0iApply

iWrite Inst1.R[3:0] 0b1111iWrite Sib1.S 0b1iWrite Sib2.S 0b0iApply

SIB1

SIB2

en1

en2

TDO

TDI

en

3TCK

TRST

SI

SOInst1

Instrument

Instrument

R

SI

SOInst2

Instrument

Instrument

R

TMS

rst

TAP


enx

si

SIB

LAT

csuenrsttck

fso

so


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An Implementation of PDL Retargeting(from the top - not using IP Level Reuse – not using Data Abstraction)



User PDL:iWrite Inst1.R 0xfiApply

iWrite Inst2.R 0xaiApply

Retargeted PDL:iWrite Tap.IR[2:0] 0b001iApply

iWrite Sib1.S 0b1iWrite Sib2.S 0b0iApply

iWrite Inst1.R[3:0] 0b1111iWrite Sib1.S 0b0iWrite Sib2.S 0b1iApply

iWrite Sib1.S 0b0iWrite Inst2.R[3:0] 0b1010iWrite Sib2.S 0b1iApply

SIB1

SIB2

en1

en2

TDO

TDI

en

3TCK

TRST

SI

SOInst1

Instrument

Instrument

R

SI

SOInst2

Instrument

Instrument

R

TMS

rst

TAP

enx

si

SIB

LAT

csuenrsttck

fso

so


www.mentor.comIJTAG Introduction - Nordic Test Forum 2015 - [email protected]

Example of IJTAG IP Level Reuse


IP Level PDL

iProcsForModule MyIP ;iProc test { {setup 010} } {

iWrite in 0b$setup ;iRunLoop 10 –tck ;iRead out [compute_value($setup)];

}

Writing to parallel data ports ‘in’

Reading from parallel data ports ‘out’

(using level-1 PDL)

M

y

I

P

i

n

o

u

t

User data at instrument parallel data IO ports





3

TRST

TCK

TDO

TDI

TMS

rst

Inst1

M

y

I

P

SI

SO

i

n

o

u

t

RSib2

en

Sib1

en

TAP

en

IP Level PDL

iProcsForModule MyIP ;iProc test { {setup 010} } {

iWrite in 0b$setup ;iRunLoop 10 –tck ;iRead out [compute_value($setup)];

}

Product level usage

iCall Inst1.test





Product level usage

iCall Inst1.test

Retargeted PDL

iWrite Tap.IR[2:0] 0b001

iApply

[…]

iWrite Inst1.R[5:0] 0b010000

[…]

iRead Inst1.R[5:0] 0bxxx111

[…]

3

TRST

TCK

TDO

TDI

TMS

rst

Inst1

M

y

I

P

SI

SO

i

n

o

u

t

RSib2

en

Sib1

en

TAP

en

Parallel data to serial scan translation


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JTAG Architecture Instrument

o The Scan Path Network is documented as a TDR with a lengtho Decode for Operation Signals happens in the TAP Controller o No Scan Path Management Featureso No description of the Instrument or its Vectors

Reduced Hardware & Pattern Cost:The 1149.1 Network with Instruments


FromTDI

ToTDO

Instrument (e.g.

MBIST)

TDI

TDO

TMS

TCK

Instrument Target:Memory

TAPController

IR

o Embedded Instrument

o Generally one Instructionselects one instrument ora fixed set of instruments

o Instrument is not describedin the 1149.1 Standard

TDR

BSDL

ScanIn

UpdateEn

ShiftEn

CaptureEn

GlobalRst

TCK to TDR

ScanOut


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JTAG Architecture Instrument

o The Scan Path Network is documented as a TDR with a lengtho Decode for Operation Signals happens in the TAP Controller o No Scan Path Management Featureso No description of the Instrument or its Vectors

Reduced Hardware & Pattern Cost:The 1149.1 Network with Instruments


FromTDI

ToTDO

Instrument (e.g.

MBIST)

TDI

TDO

TMS

TCK

Instrument Target:Memory

TAPController

IR

o Embedded Instrument

o Generally one Instructionselects one instrument ora fixed set of instruments

o Instrument is not describedin the 1149.1 Standard

TDR

BSDL

ScanIn

UpdateEn

ShiftEn

CaptureEn

GlobalRst

TCK to TDR

ScanOut

Unique bundle of wires for each

Instruction


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Reduced Hardware & Pattern Cost:Complex 1687 Network with Instruments


FromTDI

ToTDO

TDR

Instrument A (MBIST)TAP

Controller

TDI

TDO

TMS

TCK

Instrument A’s

Target: Memory

SIBSelect

Decode for one 1687 network instruction

AccessLink


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TDR

Instrument B (AlgoPatGen)

Instrument B Target: SerDes

AdjustUpdateEn

ShiftEn

CaptureEn

GlobalReset Independent select of either TDRShift, Capture, Update,

and Reset control

signals are a bussed

across the chip to all

TDRs, SIBs

– to be gated locally

by local Selects

Reduced Hardware & Pattern Cost:Complex 1687 Network with Instruments


FromTDI

ToTDO

TDR

Instrument A (MBIST)TAP

Controller

TDI

TDO

TMS

TCK

Instrument A’s

Target: Memory

SIBSelect

SIBSelect

Decode for one 1687 network instruction

AccessLinkIndependent select of either TDR


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Customer Case

◼ Reference— “Industrial Application of IEEE P1687 for an Automotive Product”

M. Keim, T. Waayers, et.al— IEEE Euromicro Conference on Digital Systems Design, 2013

◼ Pilot project transition time from in-house tool & data structures to Tessent IJTAG: ~2 weeks

◼ Successful outcome— Tessent IJTAG improved on current in-house solution by

shift cycle count reduction > 56%— Tessent IJTAG allows a more flexible DFT methodology— More tasks done by the software— Less room for human error



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Cycle Count for one Selected Type of Test

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Current IJTAG Config 1 IJTAG Config 2 IJTAG Config 3



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Summary

◼ IEEE 1687 is an IP and pattern reuse methodology

◼ No new design requirements needed → No-Risk start!

◼ Goes well beyond 1149.1 / 1500 limitations— Reduced hardware and pattern cost over 1149.1/1500— Improved Ease-Of-Use

◼ Full EDA tool automation support

◼ Is being deployed at several big semiconductor players



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[email protected]

Thank You


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APPENDIX


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IEEE 1687 for …

◼ IP provider (internal and external)— Ensures compliance to the standard— Provides easy integration for IP, esp. mixed signal ones— Hide intellectual property behind IJTAG abstraction— Validate IP level pattern independent of embedding— The source of the re-use methodology

◼ Chip designer — Efficiently integrate IEEE 1687-compliant IP from various sources

into design— Plug & Play of IJTAG compliant IP— Automated generation of IJTAG Network files

– Can use EDA tool’s IJTAG Network Insertion feature– Generate though EDA tool’s IJTAG Network Extraction from design

files



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IEEE 1687 for …

◼ Test integrator — Allows for easy test assembly and implementation of design,

including all IP, BIST, and ATPG— No need to come up with proprietary solution— Shortening of test cycle times— Resilient against IP and design changes

◼ System & board test engineer— Reuse IP level test at system and board level— Easily arrange IP to IP interaction within die and across dice

◼ Diagnosis/failure analysis engineer — Allows direct access to embedded on-chip measurements— More efficient test diagnosis



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.v

IEEE 1687 Key Concept: PDL Retargeting

◼ Translating the PDL written for an instrument module …

◼ … from the boundary of the instrument’s instantiation in an ICL view of a design …

◼ … to a new PDL for the chosen level of ICL hierarchy

ICL

ICL

ICLICL PDL

Block-level PDL

Core-level PDL

Top-level PDLSTIL

Instrument

Block

Core

Top

Instrumentlevel PDL

PDLSystem-level

Integration

Verification

ATE


This is an EDA tool feature.

Not mandated by IJTAG


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IP Level Reuse of IJTAG “Patterns”

◼ PDL keyword: iProc— Defines a PDL procedure— Similar usage as Tcl proc— Can have parameters, parameters with default values— Can call other procedures— No recursive calls though

◼ PDL keyword: iProcsForModule— Bounds a series of iProcs to a particular ICL module— Each instance of the ICL module inherits all bound iProcs

◼ PDL keyword: iCall— Used to call a PDL iProc



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Applying IJTAG IP Level Reuse

◼ At IP level— Generate instrument ICL and PDL iProcs

– Make use of name space concept

— Validate correctnesse.g. using IP level test benches or pattern/silicon debugging

— Archive ICL and PDL files

◼ Usage in design— Load instrument ICL and PDL files— iCall selected iProc for chosen instance of ICL module

◼ IEEE 1687 ensures— Plug-and-play: IP will work in the design— PDL can be retargeted to chosen hierarchy level

(assuming design’s ICL network is correct)


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