A 1.0-V 15.6-dBm 39.5%-PAE CMOS Class-E Power Amplifier with On-Chip Transformer for

Q Enhancement

Ping Song [1] Howard, Cam Luong[2]

Department of Electrical and Electronics Engineering, Department of Electrical and Electronics Engineering, The Hong Kong University of Science and Technology, The Hong Kong University of Science and Technology,

Hong Kong Hong Kong eesophia@ee.ust.hk eeluong@ee.ust.hk Abstract- A 1-V fully-differential two-stage CMOS Class-E power amplifier operating at 2.4 GHz is presented. An on-chip transformer-feedback topology is applied in the pre-amplifier in order to provide a high swing to drive the second stage. Injection-mode-locking topology is employed in the second stage to achieve high output power and high efficiency. Implemented in a 0.18-µm CMOS process, the amplifier delivers an output power of 15.6dBm with 39.5% PAE at a 1-V supply and an output power of 20.3dBm with 43% PAE at a 1.8-V supply, respectively.

1. Introduction

In recent RF front-end IC designs, CMOS technology has become more and more attractive for its low cost and feasibility of single-chip solutions. Power amplifiers (PA), the most power-hungry building block in the RF transmitter front-end, are always designed with high efficiency as a critical design consideration. For non-constant envelop modulation schemes, linear PA topology is necessary but with trade-off of low power efficiency [1]. On the other hand, for constant-envelop modulation scheme, non-linear Class-E switching-mode PA is more suitable because of its high efficiency. This paper presents the design of a 2.4-GHz CMOS Class-E PA in a standard 0.18-µm CMOS process for Bluetooth applications that measures an output power of 15.6dBm with a 39.5% PAE at 1V and an output power of 20.3dBm with a 43% PAE at 1.8V.

II. Class-E Power Amplifier

The typical circuit structure of a Class-E power amplifier is shown in Fig 1.

L2 C2

LxL1

M1 Cx RL_optVin

Vout

Vdd

vs

Fig 1: Typical Class-E power amplifier

A. Switch-mode operation

In a switch-mode operation, all the parameters need to be properly designed so that VS = 0 and dVS/dt = 0 before

the switch is turned on and that VS only begins to rise from 0 right after the switch is fully turned off [2]. The L2 and C2 function as a resonant circuitry at the frequency of interest and suppress other harmonics, with an extra inductance Lx for optimization consideration. The optimum designed values are calculated as follows [3]:

out

ddoptL P

VR

2

_ 577.0= (1)

x

optLX

RL

ω_15.1

= (2)

optLxX R

C_*

1836.0ω

= (3)

B. Effects of technology scaling on Class-E PA

Since the output power Pout is proportional to (Vdd2/

RL_opt ), for a low supply voltage and for a high output power, RL_opt should be quite low, in the order of few ohms. Such a low optimum loading RL_opt is usually realized by a matching network transforming the loading to 50Ω. The loss from the matching network is square-root proportional to the transformation ratio (m = 50 Ω / RL_opt). For a simple low-pass L-section matching network, the loss is given by: [4]

outloss PQ

mP ×

−=

1 (4)

where Q is the quality factor of the reactive component in the matching network. Smaller RL_opt results in larger loss and lower efficiency. This is one of major causes of efficiency degradation. Another major loss is from the finite turn-on resistance ron of the switching transistors. In triode region, it is approximately given by:

)(*)(1

THGSoxnon VVLWC

r−

=µ

(5)

As technology is scaled down, the decrease of channel length and the increase of transconductance coefficient k’ help reduce ron. However, the reduction of ron is slower than the reduction of the optimum loading impedance RL_opt. As a result, the ratio ron /RL_opt increases, and the efficiency is degraded according to [4]

5-4

1410-7803-9162-4/05/$20.00 ©2005 IEEE

)_(*365.111

optLon RrDE

+≈ (6)

C. Limitations at gigahertz operation

For a simple amplifier topology with on-chip resonant LC tank, the gain is given by:

)*(*)]1*//()*//([ LQgCQLQrgA LmCLOmV ωωω ≈= (7)

Typically, the quality factor of on-chip inductors is limited to around 6, and that of the on-chip capacitors is higher than 20. Consequently, the maximum gain and the power efficiency are limited by the low Q of the on-chip inductors. Since a large switching signal is required to drive the second stage, a simple LC resonant circuit using low-Q on-chip inductors as the loading of the first stage is insufficient for the high-gain requirement. Moreover, in a Class-E PA, the second-stage switching transistor should have very large size to minimize the turn-on resistance, which in turn results in a large parasitic capacitor and limits the operation frequency. The loading inductance of the first stage could be reduced to increase the frequency, but such a solution would further decrease the gain of the first stage. III. Design and Implementation of Proposed PA

k

vin+

L1 L2

C1 M1

M2

k

vin-

L3L4

C3 M3

M4

Vdd

Vdd

L5 L6

M5 M6 M7 M8

50Ohm 50OhmLx Lx

Cx Cx

Vm+ Vm-

Pre-amplifier

Second stage injection-mode locking

Fig 2: Schematic of the proposed PA

The circuit topology for the PA proposed in this work is shown in Fig 2, which consists of a preamplifier stage and a second-stage switching amplifier. The preamplifier includes a main amplifier M1, its loading inductor L1, a Q-enhancement circuitry formed by M2 and L2. The second-stage switching Class-E amplifier employs an injection-mode locking topology. L1 and L2 are on-chip inductors coupling together to form a transformer. C1 is the loading capacitor designed to resonate with L1. Transistor M2 and its loading inductor L2 are designed to generate a negative impedance to enhance the Q of L1.

A. Preamplifier using Q-enhancement circuitry As mentioned earlier, the peak-to-peak output swing of the pre-amplifier should be large enough to drive the second-stage switching-mode transistors. To achieve such a high-swing requirement, two major topologies have been employed in existing PA designs [5]-[7]: (1) injection-mode locking amplifier and (2) positive feedback amplifier. Both of these two topologies use bondwire as loading inductors to overcome the problem with low Q of on-chip inductors. The major challenge with this solution is that it is very difficult to control the inductance value of bondwire. As a result, for injection-mode locking topology, the self-oscillating frequency shifts easily, and a large locking range is required, which in turn requires a large input signal swing. For positive feedback topology, the resonant frequency for the maximum gain also shifts easily, and many cycles of trials-and-errors need to be done to settle frequency response. These two topologies require bondwires with very accurate inductance values. To solve this problem, an on-chip transformer with Q-enhancement circuit, as shown in Fig. 2, is proposed as the loading for the pre-amplifier design. Due to the transformer feedback, the effective loading inductance and the effective quality factor are given as follows:

22

021 )*(1

)/*(1*Mg

QMgLL

m

meff ω

ω+

+= (8)

)**(1)/*(1*

02

020 QMg

QMgQQ

m

meff ω

ω−+

= (9)

)**(1

1

02 QMgQ

Qf

mO

eff

ω−≈= (10)

gm2 is the transconductance of the transistor M2. f is a factor that is defined to indicate enhancement of quality factor according to (10).Q0 is the original quality factor of inductor L1 which is around 5.5 (by testing). M is the mutual inductor of L1 and L2 which is equal to

21 ** LLk , while k is the coupling coefficient of L1 and L2. In Eq. (8), since (gm2*ωM/Q0) is much smaller than 1 (3% variation in this design) and (gm2*ωM)2 is much smaller than 1 (4% variation), the effective inductance Leff is very close to L1. On the other hand, the Q enhancement factor f can be much higher than 1 according to (10). This proposed topology effectively enhances the Q of on-chip inductor without changing the loading inductance value. In this design, the variation of inductance value is only 1%, and the achieved effective Q could be 7-10 times larger by tuning current consumption of Q-enhancement circuitry. The extra current consumption is very small compared with the total. So the efficiency degradation due to this extra current is negligible. With the transformer feedback, the effective Q of the inductor is much larger than that of the on-chip

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capacitors. As a consequence, as shown by Eq. (7), the gain of the pre-amplifier becomes:

)]1*//([* CQrgA ComV ω≈ (11)

which is much higher than before and is high enough to amplify the input signal to the required maximum swing of 2* VDD. In terms of power consumption, the Q-enhancement circuitry will consume more power than the circuit with the same transistor size but off-chip inductor loading. This is practically acceptable, as for the first stage, the power consumption is only a small potion of the total. The first stage consumes one-ninth of the total and Q-enhancement circuitry consumes (1/30) of total power when effective Q reaches 60. In addition, from the above calculations, since (8)-(10) are frequency dependent, this topology is suitable for narrowband applications. B. Second stage using injection-mode-locking

topology A differential topology with two inner cross-coupled transistors as positive feedback is proposed for the second stage as shown in Fig 2. The operating mechanism is: when M5 is turned on, M6 is turned off. Vm+ is low while Vm- is high. Therefore, M5 and M7 are turned on and M6 and M8 are turned off simultaneously. The turn-on resistor for M5 and M7 is ron5//ron7. To maximize efficiency, ron5//ron7 should be minimized. It is more efficient to design larger inner transistors M7 and M8 rather than M5 and M6, for two reasons: First when M7 is turned on, the peak voltage Vm- could go high as around 2.5Vdd [8] which is larger than that of M5 (2Vdd). Based on Eq. (5), the turn-on resistor could be further decreased. Second, regarding the previous analysis, to relax driving problem of first stage, M5 and M6 should be small. Through this topology, the capacitance at each input can now be significantly reduced without increasing the overall composite switch on-resistance. When the input signal is not applied, the second stage will oscillate itself at some specific frequency, in which the value is dependent on the loading inductor, the charging capacitor and the matching network. If the frequency of the input signal is in the locking range of the self-oscillation frequency, the output frequency will be locked to input frequency, otherwise, it will be the oscillation frequency itself. This topology requires a large locking range which is mainly dominant by input swing. The large input swing of the second stage helps increase its locking range. C. Inductor Realization For the transformer layout, two centre-tapped inductors are designed and transformed together shown in Fig 3. There are totally 3 turns for each inductor. The whole dimension is 400µm×400µm. The metal width for each

inductance is 15um, while the spacing is 1.5um for each metal spacing. The fitting results are tabulated in Table I.

Fig 3: Proposed transformer layout

L1

and L3

Q1 and Q3

L2 and L4

Q2

and Q4

k

Measurement 2.03nH 5.434 2.19nH 6.065 0.86 Simulation 2.11nH 6.5 2.44nH 6.8 0.6

Table 1: Simulated and Measured transformer parameters

For the second-stage injection mode-locking topology, the inductors for loading and output matching network are all realized by bondwire for its high Q solution. The measured coefficient of the bondwire value over length is approximately 1.2nH/mm.

IV. Measurement Results

Fig 4: Die photograph of the proposed PA

Fig 4 shows the die photo of the proposed power amplifier. The bare die is directly attached to PCB for testing purpose by using silver paint. It was fabricated in TSMC 0.18-µm CMOS technology. The total chip area is 1.08mm2. The matching network is achieved by off-chip capacitors and bondwires. Fig 5 shows the output power and PAE under different supply voltage. The output power is approximately proportional to VDD

2 as expected, while the efficiency remains relatively constant within a certain range of supply voltage. Fig 6 shows ACPR performance at 2.45GHz with a 10-KHz resolution.

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The measured output power and PAE under 1V supply voltage with frequency range from 2.4GHz-2.48GHz are shown in Fig 7. Power distribution between the first stage and the second stage is 1/9 and 8/9, respectively. At a 1-V supply voltage, the achieved output power and PAE at 2.45GHz are 15.6dBm and 39.5%, respectively. At a 1.8-V supply, the achieved output power and PAE at 2.45GHz are 20.3dBm and 43% respectively.

Fig 5: Measured output power and PAE versus supply

voltage

Fig 6: Measured ACPR performance

Fig 7: Measured output power and PAE versus frequency

at 1V

As shown in Fig 8, the gain of M1 versus DC current through Q-enhancement circuitry is plotted. There is totally around 6.7dB voltage gain improvement when the output swing of first stage reaches maximum. Table II shows the performance comparison within different PA design.

V. Conclusion

A two-stage Class E Power amplifier is successfully designed and fabricated in a standard 0.18um CMOS Process. An on-chip transformer feedback circuit is applied into the first stage to provide a high output swing. An injection mode locking topology is utilized into the second stage to realize high output power as well as relax

the driving requirement of first stage. At 2.45GHz under a 1-V supply, the achieved output power is 15.6dBm with 39.5% PAE.

Fig 8: Measured gain improvement with Q-enhancement

circuitry

Reference This

Work [9] [10] [6]

Technology 0.18um-CMOS

0.18um-CMOS

0.25um-CMOS

0.35um-CMOS

Minimum Pout (dBm) 15.6 @1V

12 @ 1V

22 @ 2V

18 @ 1V

PAE under minimum Pout (%)

39.5 @ 1V

16 @ 1V

46 @ 2V

33 @ 1V

Maximum Pout (dBm)

20.3 @ 1.8 V

23.5 @ 2.4V

23 @ 2.25V

20 @ 1.2V

PAE under maximum Pout (%)

43 @ 1.8V

45 @ 2.4V

46 @ 2.25V

35 @ 1.8V

Table II: Performance comparison among different Class I Bluetooth CMOS Power Amplifiers

Reference

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