Poster Presentation 6: Logic Circuits Operating in Both Sub-and Above-Threshold Voltages

Jabulani Nyathi and Brent BeroWashington State University

School of Electrical Engineering & Computer Science102 Spokane Ave

Pullman, WA 99164

Abstract-Interest in VLSI subthreshold design has recently increased due to the emergence ofsystems that require ultra-low power operation. Furthermore the ever increasing leakage currents,now used to drive logic make subthreshold design an interesting prospect. Subthreshold sacrificesspeed for power creating a clear divide between designing for high speed and ultra-low power. Itmight be beneficial to allow circuits designed for subthreshold operation to become operable atabove threshold voltages (super-threshold), depending on processing needs. In this study amongother things; the feasibility of optimizing device sizes for both subthreshold and above thresholdoperations is considered. Three widely publicized body biasing techniques are examined andcompared to a newly proposed tunable body biasing scheme. The comparison is in terms of powerand energy dissipation as well as speed. A number of logic styles are simulated to drawconclusions on what logic style in conjunction with what body biasing scheme offer improvedperformance.

The proposed tunable body biasing scheme offers the ability to operate circuits in either thesubthreshold region for ultra-low power, at above threshold voltages for high speed or at voltagesthat offer optimal speed-power operation (2*Vto) for example). Device sizing for circuits to spanall the regions of operation is examined. The tunable body biasing approach leads to increasedoperating frequencies particularly in subthreshold operation and shows no performancedegradation at voltages above threshold, hence bridging of the speed-power gap. Post layoutsimulations of circuits ranging from simple to more complex ones enable for effective evaluationof optimal device sizing and identifying the optimal power-speed operational region. Simulationshave been performed at a modest 180 nm technology node and ring oscillator circuits showoptimal operating regions ranging from 0.5 to 0.7 V. An 8-bit linear feedback shift register usingthe tunable body biasing scheme serves as a design example and expends 4.24 joules per secondat super-threshold while dissipating 2.34 nJ per second at subthreshold voltages. The linearfeedback shift register also shows optimal operating regions ranging from 0.5 to 1.1 V.

Traditionally Tunable BodyBiased Biased

Vdd = 376.2 mV Vdd = 376.2 mV \

Vih= 225 mVNVih =200mV Vil = 200 m

Vil 175 mV

Vss= mV Vss = 0 mV

TBB and static CMOS inverters have comparable noise margins, TBB VIH is 12.5% worse, andTBB VIL is 14.3% better.

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