Abstract- In this paper, an input inductor current injection
technique, together with the one-comparator counter-based pulse-width-modulation (PWM) control strategy, is presented herein and applied to the boost converter to upgrade its stability and transient upload response. This is easy to realize based on the field programmable gate arrays (FPGA). The detailed illustration of the proposed control strategy is provided, along with some experimental results.
I. INTRODUCTION
At present, the digital control is considered as a new trend in power electronics. This is because digital control possesses some advantages such as high feasibility, fast time-to-market, insensitiveness to environmental variations and component aging, monitor and communications etc., as compared to the analog control. During these years, there are many literatures on digital control in power electronics. However, one of key points in replacing analog control with digital control is cost. Consequently, the one-comparator counter-based pulse-width-modulation (PWM) control strategy without the analog-to-digital converter (ADC) have been presented [1-3], which is easy to realize and can be applied to any type of output voltage ripple for any type of DC-DC converter under any type of operating mode.
As generally recognized, the boost converter has bilinear characteristics, thus possessing one right-half plane zero in the s domain [4-6], thereby making this system tend to be unstable and hence possess the relatively low bandwidth in the control loop and hence the relatively slow transient load response, as compared to the buck converter. Therefore, in order to overcome these problems, there are many literatures on how to accelerate the transient load response of the boost converter. The methods proposed by literatures [7, 8] need information on the input inductor current to control the inner loop, and hence if digitalized, high-speed high-accuracy ADCs are needed, thereby making cost-down not easy to achieve. As for the method described in [9], it is very complicated along with information on the output load current required, thus causing digitalization to be difficult. In [10], since this controller is realized fully according to analog implementation, it is not easy to replace by digital implementation. Concerning [11], the currents flowing through the input inductor and the output
capacitor are to be sensed and hence two ADCs are required, and besides, the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output capacitor are increased due to the output capacitor in series with one sensor, thereby causing the output voltage sag and the corresponding recovery time to be increased during the transient upload period.
Based on the mention above, an input inductor current injection technique, incorporated with the one-comparator counter-based PWM control strategy which has been presented in [1-4] without any ADC utilized, is presented herein and applied to the boost converter using the field programmable gate arrays (FPGA). By doing so, the stability and bandwidth of the control loop is upgraded, thus making the resulting transient upload response faster than that without the proposed input inductor current injection. And, this upgrades the capability of the boost converter in industrial applications. The following are operating principles to be illustrated and some experimental results to be provided, so as to demonstrate the effectiveness of the proposed control strategy.
II. OVERALL SYSTEM CONFIGURATION
Fig. 1 shows the boost converter with the proposed input inductor current injection, based on one-comparator counter-based PWM control with swatoothed wave injection. The generated sawtoothed wave sv is added to the sensed voltage signal '
ov after the voltage divider to get the modified output voltage signal ov~ . Then, the signal ov is obtained by adding
ov~ to the modified input inductor current signal Li , which is obtained from the input inductor current Li via the current sensor through the high-pass filter (HPF) and the attenuator. After this, ov is sent to the comparator COMP to compare with the voltage reference refV so as to obtain the signal VFB. This signal is sent to FPGA to create the suitable PWM control signals M1 and M2 to drive the switches S1 and S2 respectively, based on two counters and one proportional-integral-derivative (PID) controller inside FPGA. It is noted that the switch S1 is the main switch and the switch S2 is the synchronous rectification (SR) switch. And hence, this converter always operates in the continuous current mode (CCM).
III. OVERVIEW OF ONE-COMPARATOR COUNTER-BASED PWM CONTROL AND ITS CONTROL LOOP
The basic operation principles of the one-comparator counter-based control strategy [10, 11] are based on the fact that the sensed output voltage ripple is mainly determined by the equivalent series resistance (ESR) of the output capacitor with the triangular-like current flowing through the output capacitor. Under such a condition without inductor current injection, the sensed output voltage ripple possesses the triangular-like wave and hence the sawtoothed wave injected is not necessary herein, that is to say, 0ˆ =Li , 0=sv and 'ˆ
oo vv = , as shown in Fig. 1. In Fig. 2, there are two counters created in FPGA whose system clock is set to 100MHz, i.e. the corresponding period is 10ns. One is PWM_COUNT employed to count the period Ts of the 9-bit digital PWM control signal M1 and the other is COUNT utilized to obtain information on the output voltage. And, Ts corresponds to 512CLK or 512, i.e.
s5.12μ . The moment PWM_COUNT becomes zero, COUNT is set to zero and the main switch S1 gets turned on. Besides, the comparator COMP shown in Fig. 1 is utilized to determine the relationship between the sensed output voltage ov sent to the negative terminal of COMP and the output voltage reference refV sent to the positive terminal of COMP.
As shown in Fig. 2, the output voltage ripple is approximately triangular. As S1 is turned on during the duty
cycle, ov is to increase. As soon as ov reaches refV , the comparator output signal VFB changes its status from the high level to the low level, i.e. VFB = 0, thereby creating a negative-edged signal, which is sent to FPGA. At this moment, COUNT starts counting from zero. As soon as VFB changes its status from the low level to the high level, i.e. VFB = 1, COUNT stops counting and the resulting value of COUNT is saved as REG, which is utilized to represent information on the feedback output voltage. In this case, the center point of the ripple of ov locates at refV , implying that the average or DC value of ov is equal to Vref. At this instant, REG is 256CLK or 256, that is to say, the corresponding elapsed time of COUNT is μs56.2 , which is half of the switching period Ts. On the other hand, if the center point of the ripple of ov is below the level of refV , implying that the average or DC value of ov is smaller than refV , then the resulting value of REG is smaller than 256, i.e. the corresponding sensed output voltage error, obtained by subtracting the value of REG from 256, is positive. And, if the center point of the ripple of ov is beyond the level of refV , implying that the average or DC value of ov is larger than refV , then the resulting value of REG is larger than 256, i.e. the corresponding sensed output voltage signal error is negative. Therefore, the larger the error in the sensed output voltage signal is, the larger the control effort that determines the next duty cycle.
refV
VFB
ov
CLKREG 256=
CLKTs 512= CLKTs 512=
CLKREG 256=COUNT
COUNTPWM _
Fig. 2. Center point of the ripple of ov equal to refV .
However, in actuality, the ripple of the sensed output
voltage signal is sometimes relatively small or distorted, i.e. non-triangular, due to too low equivalent series resistance (ESR) of the output capacitor, or too small triangular-like currents or non-triangular currents flowing through the output capacitor. Then, as shown in Fig. 1, a sawtoothed wave is injected into the sensed output voltage signal to get the modified output voltage signal [12], that is to say, 0ˆ =Li and
soo vvv += 'ˆ . Most of importance, the amplitude of the sawtoothed wave is about ten times of that of the ripple of the sensed output voltage signal so as to reduce the effect of the sensed output voltage signal on the sawthoothed wave after injection, as shown in Fig. 3. And then, the ripple of the modified output voltage signal possesses the sawtoothed-like wave, and accordingly the analysis of this sampling method to obtain information on the output voltage is almost the same as mentioned in the beginning of this section. In this paper, such a
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method, together with input inductor current injection to be discussed later, is utilized herein.
As for the corresponding control loop shown in Fig. 4, how to design the control loop for this converter is described below, along with definition of the maximum duty cycle of the PWM control signal M1. The value of REG is obtained from the sensed output voltage signal through one comparator and two counters, and such a value is subtracted from 256 to obtain the sensed output voltage signal error errorov −ˆ which is sent to the proportional-integral-derivative (PID) controller to get the control effort vf. And then, the result of the PID controller is sent to a limiter, added to 256 and restricted to 360, corresponding to the maximum duty cycle of 70%. Afterwards, the duty cycle of the 9-bit digital PWM control signal M1 used to drive S1 is created. And hence, the PWM control signal M2 to drive the switch S2 is obtained according to M1, with some modifications.
'ov
refV
refV
GND
sv
ov
(a)
(b)
CLKTs 512= CLKTs 512=
(c) Fig. 3. (a) Sensed output voltage signal with low voltage ripple; (b) generated
sawtoothed wave; (c) modified output voltage signal with sawtoothed-like ripple.
+−
PIDerrorov −ˆ 360~0 ovΣ
REG
256 Σ Plantfv
256
++
Fig. 4. Proposed control loop.
IV. PROPOSED INPUT INDUCTOR CURRENT INJECTION
A. Basic operating principles As generally recognized, the boost converter has bilinear
characteristics, that is to say, it possesses one right-half plane zero in the s domain, thereby causing the corresponding system bandwidth to be relatively low and hence the transient upload
responses to be relatively slow, as compared with the buck converter. Consequently, if the bandwidth of the boost converter must be enhanced greatly under some conditions, then oscillation is indispensable during the transient period. From the physical point of view, during the upload transient, the boost converter can be considered as a current source created from the input inductor and charging the output capacitor. Therefore, variations in the output voltage lag behind variations in the current flowing through the input inductor. On the other hand, from the point of view of control, if the system bandwidth must be extended, then as the transient upload occurs, the control effort from the PID controller is increasingly outputted to enlarge the input inductor current and hence to make the output voltage recovered to the prescribed voltage reference as soon as possible. Unfortunately, according to the mention above, it is obvious that variations in the output voltage are much slower than variations in the control effort generated by the PID controller. That is to say, during the transient upload period, the PID controller can not stop the output input inductor current immediately as it finds that the output voltage is equal to the prescribed voltage reference, thus causing the output voltage to go too high and even oscillate, as shown in Fig. 5.
ENLOAN_
Li
ov
Fig. 5. Illustration of associated waveforms without input inductor current injection.
Based on the mention above, the PID controller is
preferably designed such that the increased control effort influences the output voltage as soon as possible. That is to say, it is desired that the PID controller monitors variations in the output voltage as well as variations in the input inductor current simultaneously, so as to reduce the delay time between the two variations as minimum as possible. In order to attain this goal, a current injection technique is presented herein by sum of the appropriate sensed input inductor current signal and the modified output voltage signal, as shown in Fig. 1. By doing so, the PID controller considers the output voltage response to be fast during the transient upload period, so as to suppress output voltage oscillation to some extent. However, there is one problem existing, the sensed input inductor current signal has a DC component which deteriorates the output voltage accuracy in the steady state. That is to say, the more the DC portion of the sensed input inductor current signal, the less the accuracy of the output voltage in the steady state.
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Therefore, as shown in Fig. 1, one high-pass filter (HPF) composed of one resistor and one capacitor, is used to remove the DC component of the sensed input inductor current signal, so as to obtain the AC component of the sensed input inductor current which is added to the modified output voltage signal after the attenuator to enhance the system stability and bandwidth. But there are still another two problems about the amplitude and the duration of the sensed inductor current signal to be injected.
i
o
VV
D
A B
IRegion IIRegion
10 Fig. 6. Effect of parasitic parameters on the voltage ratio as a function of duty
cycle.
Before entering into discussing the question mentioned above, as generally recognized, the voltage ratio as a function of duty cycle is shown in Fig. 6, and hence there are two possible operating duty cycles corresponding to the same voltage ratio due to parasitic parameters. In Fig. 6, the black line with parasitic parameters considered is different from the bold dotted line without parasitic parameters considered. If the operating duty cycle falls in region II, such as at point B, then the larger the duty cycle, the more the output voltage sag, whereas if the operating duty cycle falls in region I, such as at point A, then the larger the duty cycle is, the less the output voltage sag.
According to the mention above, as shown in Fig. 7, the desired waveforms during the transient upload period without considering high-frequency portion, i.e. '~
oo vv = shown in Fig. 1, are the input inductor current, Li , the sensed input inductor current signal after HPF and the attenuator, Li , and the sensed output voltage, ov~ . For the boost converter operating during the interval between points a and b, ov~ keeps falling with a slight effect of Li on ov~ , due to this converter operating in region II shown in Fig. 6. Regarding the boost converter operating at point b, the output voltage sag corresponding to point D is deeper than that without Li injected, and also
Li corresponding to point C is equal to the required DC upload current. Concerning the boost converter operating after point b, it works in region I, as shown in Fig. 6. For the boost converter operating during the interval between points b and c, ov~ is rising from point D slower than that without Li injected, due to a negative effect of Li on ov~ . As to the boost converter operating at point c, ov~ corresponding to point F is equal to the voltage reference Vref. At this instant, if the value of Li corresponding to point E is sufficiently large, then ov~ has a
little overshoot and eventually falls to Vref corresponding to point G after point c, due to a positive effect of Li on ov~ .
Based on the mention above, as shown in Fig. 7, it is desired that the maximum value of Li locating at the point E corresponds to the DC value of ov~ locating at the point F. That is to say, for the effect of duration of Li on ov~ during the transient upload period, the duration of Li is the inverse of the oscillation radian frequency of the output voltage without the proposed control scheme added, which implies that the corner frequency of HPF is set to the oscillation frequency. On the other hand, for the effect of amplitude of Li on ov~ during the transient upload period, if this amplitude is too large, then the corresponding sag is large but oscillation is suppressed, as shown in Fig. 8. But if this amplitude is too small, then the corresponding sag is small but oscillation happens, as shown in Fig. 9. Therefore, the optimal ov~ during the upload transient shown in Fig. 10 under an appropriate amplitude of Li has a desired sag with oscillation as minimum as possible, thereby causing the amplitude and the duration to be determined mainly by experiments, to be discussed later.
Li
ov~
C
D
E
F
a b c
Li
G
Fig. 7. Illustration of the relationship between Li and ov~ .
ENLOND _
Li
ov~
controllerPIDfromseenvi oL~ˆ +
Li
Fig. 8. Illustration of associated waveforms with large input inductor current
injection.
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Li
Li
ov~
ENLOND _
controllerPIDfromseenvi oL~ˆ +
Fig. 9. Illustration of associated waveforms with small input inductor current
injection.
Li
Li
ov~
ENLOND _
controllerPIDfromseenvi oL~ˆ +
Fig. 10. Illustration of associated waveforms with appropriate input inductor
current injection.
B. Parameter tuning philosophy Initially, under the load change from no load to rated load,
the parameters of the PID controller without input inductor current injection is tuned to the extent that a little oscillation occurs but not too long, so as to pull up the bandwidth of the transient upload response as high as possible and to reduce the steady state error in the output voltage as minimum as possible. Afterwards, the sensed input inductor current signal is processed via HPF and the attenuator. According to information on the load change from rated load to no load mentioned above, regardless of the output voltage sag, the corner frequency of HPF is first tuned by its time constant close to the inverse of the measured oscillation radian frequency, so as to remove the oscillation as well as to obtain the recovery time as minimum as possible. By doing so, the duration of the sensed input inductor current signal is
determined. Sequentially, the amplitude of the sensed input inductor current signal is tuned by adjusting the attenuator gain. The larger the attenuator gain is, the larger the output voltage sag but the less the response oscillation; otherwise, the smaller the attenuator gain is, the smaller the output voltage sag but the more the response oscillation. Consequently, this amplitude is carefully chosen so as to meet the design requirements.
V. EXPERIMENTAL RESULTS
Before going into this section, there are some specifications to be described as follows: (i) DC input voltage Vi is set to 12V; (ii) rated DC output voltage is set to 24V; (iii) rated output current is 2A; (iv) input inductance L is chosen to be H6μ ; (v) output capacitance C is set to F722μ composed by one F680μ electrolytic capacitor in parallel with two F22μ MLCC capacitors; (vi) current sensor gain is 50mV/A; (vii) voltage divider gain is 0.5; (viii) slew rate of the output current change is s10A/μ ; (ix) sag due to load change from no load to rated load is within 750mV ; (x) parameters of the PID controller are kp, ki and kd set to 2, 0.125 and 4 respectively; (xi) product name of FPGA is EP1C3T100; and (xii) product name of comparator is LT1719.
From Figs. 11 to 13, under a given set of parameters of the PID controller mentioned above, these measured output voltages are related to various transient upload responses without input inductor current injection activated. From these results, it is obvious that measured variations in load affect the output voltage sag somewhat but the oscillation frequency slightly. Accordingly, the duration of the sensed input inductor current signal to be injected can be obtained via HPF, and hence the time constant of HPF is set to 0.1ms, i.e. the corresponding corner frequency is 1.6kHz that is close to the measured oscillation frequency during the transient upload period. Sequentially, an appropriate attenuator gain is set to 0.087 according to the desired output voltage sag due to load change from no load to rated load.
By the way, the experimental results show that in the steady state the output voltages at heavy loads are slightly larger than those at light loads because the integral gain ki of the PID controller is chosen not to be large enough. This is because the system without input inductor current injection under large values of ki tends to actuate the over-current protection function. Consequently, the value of ki is set to 0.125 for comparison of the results without and with input inductor current injection.
As compared with Figs. 11 to 13, it is obvious that from Figs. 14 to 16 the measured transient upload responses due to various load changes have remarkably small oscillations, thereby causing the corresponding recovery times to be shorten and hence the system bandwidth to be upgraded. But the output voltage has a rising tail in the beginning of the steady state, due to the non-ideal waveform of Li having a tail.
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sμ500
V5
mV500
ENLOAD _
ov
Fig. 11. Transient load response due to load change from 0% to 50% of rated
load without input inductor current injection.
sμ500
V5
mV500
ENLOAD _
ov
Fig. 12. Transient load response due to load change from 25% to 75% of rated
load without input inductor current injection.
sμ500
V5
mV500
ENLOAD _
ov
Fig. 13. Transient load response due to load change from 0% to 100% of rated
load without input inductor current injection.
sμ500
V5
mV500
ENLOAD _
ov
Fig. 14. Transient load response due to load change from 0% to 50% of rated
load with input inductor current injection.
sμ500
V5
mV500
ENLOAD _
ov
Fig. 15. Transient load response due to load change from 25% to 75% of rated
load with input inductor current injection.
sμ500
V5
mV500
ENLOAD _
ov
Fig. 16. Transient load response due to load change from 0% to 100% of rated
load with input inductor current injection.
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VI. CONCLUSION
In this paper, the input inductor current injection is presented to improve the natural disadvantage of the boost converter, thereby causing the transient upload response to be enhanced significantly. This method, incorporated with one-comparator counter-based PWM control using FPGA, makes the implementation of digitalization control of the boost converter easier than before.
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scheme to an FPGA-based SR forward converter,” IEEE APEC’06, vol. 3, pp. 1396-1400, 2006.
[2] K. I. Hwu and Y. T. Yau, “Accelerating the transient load response of an FPGA-counter-based SR Forward Converter,” IEEE PESC’06, pp. 366-370, 2006.
[3] K. I. Hwu and Y. T. Yau, “Improvement of one-comparator counter-based PWM control by applying a sawtoothed wave injection method,” IEEE APEC’07, vol. 1, pp. 478-481, 2007.
[4] H. Rodriguez, R. Ortega and G. Escobar, “A new family of energy-based non-linear controllers for switched power converters,” IEEE ISIE’01, vol. 2, pp 723-727, 2001.
[5] K. Viswanathan, D. Srinivasan and R. Oruganti, “A universal fuzzy controller for a non-linear power electronic converter,” IEEE FUZZ-IEEE'02, vol. 1, pp 46-51, 2002.
[6] Huh Sung-hoe and Park Gwi-Tae, “An adaptive fuzzy controller for power converters,” IEEE FUZZ-IEEE '99, vol. 1, pp 434-439, 1999.
[7] Tan Siew-Chong, Y. M. Lai, C. K. Tse and Chi Kin Wu, “A pulsewidth modulation based integral sliding mode current controller for boost converters,” IEEE PESC '06, pp. 1-7, 2006.
[8] E. Vidal-Idiarte, L. Martinez-Salamero, J. Calvente and A. Romero, “An H∞ control strategy for switching converters in sliding-mode current control,” IEEE Trans. on Power Electron., vol. 21, no. 2, pp. 553-556, 2006.
[9] D. Cortes, J. Alvarez and Ja Alvarez, “Robust control of the boost converter,” IIEEE ICIECA’05, pp. 121-126, 22005.
[10] Y. U. Hong, S. H. Jung, Y. J. Woo, B. K. Choi and G. H. Cho, “Single-chip quasi-PWM DC-DC converter with fast transient response comprising, loop-bandwidth control,” IEE Electron. Letters, vol. 41, no. 8, pp. 501-503, 2005.
[11] K. K. S. Leung and H. S. H. Chung, “State trajectory prediction control for boost converters,” IEEE ISCAS '04, vol. 5, pp. 556-559, 2004.
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