High-Efficiency Transmission-Line GaN HEMT Inverse Class F Power Amplifier for Active Antenna Arrays

Andrei Grebennikov

Bell Laboratories, Alcatel-Lucent, Blanchardstown Industrial Park, Dublin 15, Ireland andrei.grebennikov@alcatel-lucent.com

Abstract — In this paper, a novel load-network solution to implement the transmission-line inverse Class F power ampli-fier for WCDMA active antenna array applications is pre-sented. The theoretical analysis is based on an analytical deri-vation of the optimum load-network parameters to control the second and third harmonic at the device output including the device output parasitic shunt capacitance and series inductance. For an inverse Class F power amplifier based on a Nitronex GaN HEMT NPTB00004 with hybrid microstrip implementa-tion, the simulated output power of 37 dBm and power-added efficiency of more than 70% are achieved at a supply voltage of 25 V in a frequency bandwidth of 2.11 to 2.17 GHz. The test board with implemented inverse Class F GaN HEMT power amplifier has been measured and high-performance results with drain efficiencies of about 80% and higher were achieved across the wide ranges of bias supply voltages and operating frequencies.

Index Terms — RF power amplifier, inverse Class F, trans-mission line, efficiency, circuit design, resonant circuit, transis-tor.

I. INTRODUCTION

In modern wireless communication systems it is required that the power amplifier could operate with high efficiency, high linearity, and low harmonic output level simultane-ously. To increase efficiency of the power amplifier, it is possible to apply a switching-mode inverse Class F mode technique. This kind of a power amplifier requires an opera-tion in saturation mode resulting in a poor linearity, and therefore is not suitable to directly replace linear power am-plifiers in conventional WCDMA transmitters with non-constant envelope signal. However, to obtain both high effi-ciency and good linearity, such kind of nonlinear high-efficiency power amplifier operating in an inverse Class F mode can be used in advanced transmitter architectures such as Doherty, LINC (linear amplification using nonlinear components), or EER (envelope elimination and restoration) with digital predistortion [1, 2].

Highly efficient operation of the power amplifier can gen-erally be obtained by applying biharmonic or polyharmonic modes when an additional single-resonant or multi-resonant circuit tuned to the odd or even harmonics of the fundamen-tal frequency is added into the load network. An infinite number of even-harmonic resonators results in an idealized inverse Class F mode with a half-sinusoidal voltage wave-form and a square current waveform at the device output terminal. In inverse Class F power amplifiers analyzed in frequency domain, the fundamental and harmonic load-network impedances, optimized by short-circuit termination and open-circuit peaking to control the voltage and current

waveforms at the device output to obtain maximum effi-ciency, are equal to

0

dd2

0net 8 )(

IVRZ πω == (1)

harmonics oddfor 0 ])12[( 0net =+ ωnZ (2)

harmonicseven for )2( 0net ∞=ωnZ (3)

where R is the fundamental-frequency load-network imped-ance (or optimum load-line resistance), Vdd is the supply voltage, and I0 is the dc current component [3].

The ideal inverse class F power amplifier cannot provide all voltage third and higher-order odd harmonic short-circuit termination by the use of a single parallel transmission line, as it can be easily realized by a quarterwave transmission line for even-harmonic shorting in the conventional class F power amplifier. In this case, with a sufficiently simple cir-cuit schematic convenient for practical realization, applying the current second harmonic peaking and voltage third har-monic short termination can result in a maximum drain effi-ciency of more than 80% [4, 5]. For example, by providing a proper high-impedance second-harmonic peaking and load matching at the fundamental, the collector efficiency of 83% was achieved for a 435 MHz microstrip bipolar power am-plifier [6].

Generally, the control of the third and even harmonics at lower frequencies can be done using an inverse Class F load network based on both lumped elements and transmission lines [7, 8]. At higher frequencies, to control the second and third harmonics, it is preferable to use the short-circuit and open-circuit stubs instead of lumped capacitors in the load network for better performance predictability and tuning accuracy.

Figure 1 shows the typical transmission-line inverse Class F load-network schematic where a shunt 60-degree transmis-sion line TL1 provides low impedance for the third harmonic and certain impedances for the fundamental and second harmonics at the device drain terminal. The second-harmonic peaking is achieved by using of a 45-degree open-circuit stub TL3 which creates a low impedance at the end of a series transmission line TL2 at the second harmonic. As a result, the series transmission line with electrical length of less than 45° at the fundamental, combined in parallel with the shunt 60-degree transmission line and device output ca-pacitances Cout, operates as a second-harmonic tank [3, 9].

However, such an inverse Class F load network does not take into account the transistor output parasitic series bond-wire and lead inductance Lout that makes difficult to provide

978-1-4244-2802-1/09/$25.00 ©2009 IEEE 317

an acceptable second-harmonic peaking and third-harmonic short termination in real circuit. Even if Lout can be placed between the output capacitance Cout and shunt transmission line TL1 and a short-circuit termination is provided at its right-hand side, the open-circuit condition will be fully de-pended on a physical length of this inductance which is dif-ficult to set very accurately in real hybrid or monolithic inte-grated circuits.

Vdd

TL1

TL2, θ

TL3

60°

45° RL

a).

Cout

R

Device oputput

60° 45° RL

b).

Z0, θ

Fig. 1. Transmission-line inverse Class F power amplifier.

II. ANALYSIS AND DESIGN

The proposed schematic of the highly efficient transmis-sion-line power amplifier with low harmonic level using an inverse Class F mode is shown in Fig. 2, where complex-conjugate load matching is provided at the fundamental and both high impedance at the second harmonic and low im-pedance at the third harmonic are created at the device out-put by using two series transmission lines the electrical lengths of which depend on the values of the device output shunt capacitance Cout and series inductance Lout, a quarter-wave short-circuit stub, and an open-circuit stub with elec-trical length of 30°.

TL3

TL2, θ 2

TL4Cout

R

Device oputput

90°30°

RL

TL1, θ 1Lout

Fig. 2. Modified transmission-line inverse Class F power amplifier.

Figure 3(a) shows the load network seen by the device multiharmonic current source at the fundamental when the combined series transmission line TL1 + TL2, together with an open-circuit capacitive stub TL4 with electrical length of 30°, provides an impedance matching between optimum output device impedance R and load resistance RL, where Cout and Lout are the elements of the matching circuit, by proper choice of the transmission-line characteristic imped-ances Z1 and Z2.

Rat undamental

TL1 + TL2

Z1, θ1 + θ2

TL4Z2

30°

a).

b).

Cout

Lout

RL

Infinite impedance at second harmonic

Z1, 2θ1

Cout

Lout

c).

Zero impedance at third harmonic

Cout

Lout Z1, 3(θ1 + θ2)

Fig. 3. Load networks seen by the device output at harmonics.

The load network seen by the device current source at the second harmonic is shown in Fig. 3(b) (taking into account the shorting effect of the quarterwave short-circuit stub TL3), where the transmission line TL1 provides an open-circuit condition for the second harmonic at the device output by forming a second-harmonic tank. Similarly for the load net-work at the third harmonic shown in Fig. 3(c), due to the open-circuit effect of the short-circuited quarterwave line TL3 and short-circuit effect of the open-circuit harmonic stub TL4 at the third harmonic. In this case, the combined trans-mission line TL1 + TL2, together with the series inductance Lout, provides a short-circuit condition for the third harmonic at the device output being shorted at its right-hand side. De-pending on the actual physical length of the device output electrode, the on-board adjusting of the transmission lines TL1 and TL2 can easily provide the required open-circuit and short-circuit conditions, as well as an impedance matching at the fundamental frequency, due to their series connection to the device output.

By using Eqs. (2) and (3), the electrical lengths of the transmission lines TL1 and TL2 as analytical functions of the device output series inductance Lout and shunt capacitance Cout are obtained from

( )out 0 1

outout2

011 2

2 1tan

21

CZCL

ωωθ −

= − (4)

11

out012 3tan

31

3 θωπθ −−= −

ZL (5)

where the transmission-line characteristic impedance Z1 can be set in advance and where the total electrical length θ1 + θ2 = π or 180° at the third harmonic when Lout = 0.

318

R Cout

L

RLC

Fig. 4. Equivalent representations of load network at fundamental.

CoutR

90°

30°

RL

Lout θ1

Fig. 5. Special case of inverse Class F load network.

However, in order to omit an additional matching section at the fundamental, the inverse Class F load network can also be used to match the output device fundamental-frequency impedance R with the standard load impedance RL

(usually equal to 50 Ω). In this case, it is necessary to prop-erly optimize both characteristic impedances Z1 and Z2. Fig-ure 4 shows the equivalent fundamental-frequency represen-tation of the inverse Class F load network shown in Fig. 3(a), including the device output parameters Lout and Cout. Here, the corresponding elements of the lumped T-type matching circuit can be written as C = tan30°/(ω0Z2) and L ≅(Z1/ω0)sin(θ1 + θ2) + Lout due to the sufficiently short length of the combined transmission line TL1 + TL2, typically much less than 60° at the fundamental depending on the device parameters. As a result,

( )( )21

out01 sin

θθ

ω+

−= LLZ (6)

31

02 C

Zω

= (7)

When RL > R and Q = ω0CoutR, it follows for a lumped low-pass T-type matching circuit that

( ) 1 1 2LL −+= Q

RRQ (8)

L0

L R

QCω

= (9)

L2L

L

1 RQQQL

++= (10)

where the parameters Lout, Cout, R, and RL are fixed [10]. By subsequent calculation of the load quality factor QL from Eq. (8), then the capacitance C and inductance L from Eqs. (9) and (10), respectively, the characteristic impedance Z2 can be directly obtained from Eq. (7). The remaining parameters including the electrical lengths θ1 and θ2 and characteristic impedance Z1 can be found from a system of three equations represented by Eqs. (4) to (6).

For most practical cases when ω0Lout/Z1 < 0.1, from Eqs. (5) and (6) it follows that the characteristic impedance Z1

can be easily calculated from

( )3

2 out 01

LLZ −= ω . (11)

For particular values of the parameters Cout and Lout when Cout is sufficiently small and Lout is enough large, the electri-cal length θ2 can be set to zero, thus resulting in a special simplified case of the inverse Class F load network shown in Fig. 5. Hence, the transcendental equation to define explic-itly the required characteristic impedance Z1 can be written as

( ) 1

out01

out 0 1

outout2

01 3tan31

3

22 1tan

21

ZL

CZCL ωπ

ωω −− −=− . (12)

III. SIMULATION AND IMPLEMENTATION

Figure 6 shows the simulated circuit schematic of the in-verse Class F GaN HEMT power amplifier based on a 28 V 5 W Nitronex RF power transistor NPTB00004. The input matching circuit provides a complex-conjugate matching with a 50-Ω source. The load network represents the simpli-fied transmission-line circuit shown in Fig. 5.

Figure 7 shows the simulated results of an inverse Class F power amplifier using a RO4350 30-mil substrate. The maximum output power of 37 dBm, drain efficiency of 73% and PAE of 70% at the center bandwidth frequency of 2.14 GHz are achieved with a power gain of 15 dB (linear gain > 20 dB) and a supply voltage of 25 V.

V_input V_gateV_load

V_drain

V_dc

MLINTL4

L=130 milW=67 mi lSubst="RO4350"

RR1R=75 Ohm

MLINTL5

L=650 milW=45 mi lSubst="RO4350"

CC2C=20 pF

V_DCSRC1Vdc=-1.35 V

MLINT L19

L=400 mi lW=280 mi lSubst="RO4350"

MCROSOCros3

W4=280 mi lW3=67 milW2=67 milW1=67 milSubst="RO4350"

P_1T onePORT 1

Freq=RF_freqP=dbmtow(P_in)Z=50 OhmNum=1

I_ProbeI_input

I_ProbeI_load

TermTerm2

Z=50 OhmNum=2

CC3C=50 pF

MLINTL6

L=470 mi lW=67 milSubst="RO4350"

MCROSOCros2

W4=200 mi lW3=67 milW2=67 milW1=67 milSubst="RO4350"

V_DCSRC2Vdc=V_dc

I_ProbeI_dc

MLINT L7

L=50 milW=67 milSubst="RO4350"

MLINTL15

L=350 mi lW=200 mi lSubst="RO4350"

MLINTL8

L=650 mi lW=67 milSubst="RO4350"

NPT B00004_NPTB00004X1Temperature=25

Fig. 6. Circuit schematic of inverse Class F GaN HEMT amplifier.

5 10 15 200 25

14

16

18

20

12

22

25

30

35

20

40

P_in

Gai

n

Pout_dB

m

5 10 15 200 25

20

40

60

0

80

20

40

60

0

80

P_in

Eff

PAE

a).

b).

Gain Pout_dBm

PAE Eff

Fig. 7. Simulated results of inverse Class F GaN HEMT amplifier.

319

Fig. 8. PCB board layout of inverse Class F GaN HEMT amplifier.

Gain, dB

0 5

10

15

20

Pin, dBm5 10 15 20

Pout, dBm

40

30

20

Drain efficiency, %

0 0

20

40

60

80

Pin, dBm5 10 15 20

PAE, %

80

60

40

20

a).

b).

Fig. 9. Measured results of inverse Class F power amplifier.

Figure 8 shows the test board of this GaN HEMT power amplifier. The input matching circuit, output load network, and gate and drain bias circuits (having bypass capacitors on their ends) are fully based on microstrip lines of different electrical lengths and characteristic impedances according to the simulation setup shown in Fig. 6. Figure 9 shows the measured results with a saturated output power of 35 dBm and a PAE of 70.5% with a power gain of 12.5 dB at the operating frequency of 2.14 GHz (gate bias voltage Vg = −1.4 V, quiescent current Iq = 20 mA, and drain supply volt-age Vdd = 25 V), achieved without any tuning of the input matching circuit and load network. In this case, the deeper the saturation mode, the lower dc supply current is meas-ured, resulting in an increasing drain efficiency (78.5% and higher) with almost constant fundamental output power. The fundamental output power is varied almost linearly from 33 dBm at Vdd = 20 V up to 37.5 dBm at Vdd = 35 V, and maximum drain efficiency of about 82% is achieved at a dc supply voltage of 32.5 V. For Vdd = 25 V and Pin = 25 dBm, the output power increases up to 37.2 dBm at lower band-width frequencies, however the drain efficiency achieves the maximum value of 87% at 1.95 GHz. Due to the short-circuit and open-circuit effects of the corresponding quar-terwave transmission-line stubs, the second and third har-monic components are suppressed by more than 25 dB over the most part of the measured frequency range from 1.800 to 2.175 GHz.

IV. CONCLUSION

A novel load-network solution to implement the transmis-sion-line inverse Class F power amplifier for WCDMA ac-tive antenna array applications is presented. The theoretical analysis is based on an analytical derivation of the optimum load-network parameters to control the second and third harmonic at the device output including the device output parasitic shunt capacitance and series inductance. For an inverse Class F power amplifier based on a Nitronex GaN HEMT NPTB00004, the simulated output power of 37 dBm and power-added efficiency of more than 70% are achieved at a supply voltage of 25 V in a frequency bandwidth of 2.11 to 2.17 GHz. The test board with implemented inverse Class F GaN HEMT power amplifier has been measured and high-performance results with drain efficiencies of about 80% and higher were achieved across the wide ranges of bias supply voltages and operating frequencies.

REFERENCES

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[5] F. H. Raab, “Class-E, Class-C, and Class-F power amplifiers based upon a finite number of harmonics,” IEEE Trans. Microwave Theory Tech., vol. MTT-49, pp. 1462-11468, Aug. 2001.

[6] W. McCalpin, “High efficiency power amplification with optimally loaded harmonic waveshaping,” Proc. RF Tech. Expo’86 (Anaheim, CA), pp. 119-124, 1986.

[7] F. Lepine, A. Adahl, and H. Zirath, “L-band LDMOS power amplifi-ers based on an inverse Class-F architecture,” IEEE Trans. Micro-wave Theory Tech., vol. MTT-53, pp. 2007-2012, June 2005.

[8] A. Ouyahia, C. Duperrier, C. Tolant, F. Temcamani, and P. Eudeline, “A 71.9% power-added-efficiency inverse Class-F LDMOS,” 2006 IEEE MTT-S Int. Microwave Symp. Dig., pp. 1542-1545.

[9] W. Gerhard and R. Knochel, “A 2.14 GHz inverse Class F Si-LDMOS power amplifier with voltage second harmonic peaking,” 2006 German Microwave Conf. Guide, p. 21.

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