CMOS-MEMS Variable Capacitors with Low Parasitic Capacitance for Frequency-Reconfigurable RF Circuits

John Reinke1, Abhishek Jajoo1, Leon Wang1, Gary Fedder1, 2, 3, and Tamal Mukherjee1

1Department of ECE, 2The Robotics Institute, 3Institute for Complex Engineered Systems Carnegie Mellon University, Pittsburgh, PA, 15213, USA

Abstract — The design and characterization of a CMOS-

MEMS variable capacitor is presented. Measured results demonstrate a tuning ratio of 6.9:1, a quality factor of 28 at 3 GHz, and a self-resonant frequency of 11 GHz, with sub-50 fF parasitic capacitance. Simulations of two frequency-reconfigurable circuits, a low-noise amplifier and a power amplifier, show the importance of low parasitic capacitance for practical reconfigurable front-end designs.

Index Terms — Capacitors, electrothermal effects, microelectromechanical devices, Q factor, tunable amplifiers.

I. INTRODUCTION

Monolithic, frequency-reconfigurable transceivers could enable communication over an increasing number of wireless communication standards in a cost-effective manner. Frequency-reconfiguration can be accomplished using variable capacitors to tune the resonance frequencies of LC circuits. MEMS variable capacitors have shown promise as tunable RF components, but the majority of MEMS devices are not monolithically integrated with CMOS. Thus, they need bond pads which add ~100 fF of parasitic capacitance. Additional capacitance reduces the quality factor (Q) of an LC tank which decreases the gain and efficiency of RF circuits. This drawback can be overcome by using CMOS-MEMS variable capacitors which are integrated with CMOS [1].

Frequency-reconfigurable circuits using such CMOS-MEMS variable capacitors have been reported in the past [2]. However, the 1st generation variable capacitor in those circuits contained large parasitic capacitances, greater than those of a typical bond pad. This paper presents an improved 2nd generation variable capacitor which achieves parasitic capacitances below 50 fF. Furthermore, the new device exhibits a capacitance tuning ratio of 6.9:1, greater than the earlier 2.5:1 tuning ratio.

To demonstrate how the 2nd generation variable capacitor can improve circuit performance, two frequency-reconfigurable circuits, a low-noise amplifier (LNA) and a power amplifier (PA), are simulated with the enhanced device. These simulation results are compared with both simulated and measured results [3] from the same circuits using the 1st generation variable capacitor.

II. CMOS-MEMS VARIABLE CAPACITOR

The CMOS-MEMS variable capacitor is fabricated in 0.35 µm BiCMOS and micro-machined using the CMOS-MEMS post-process [4]. The resulting mechanical structure is composed of the back-end-of-line metal-dielectric stack. This multi-layer stack is used to create both the capacitance electrodes and the actuator beams, which curl in response to changes in temperature [5]. When combined with embedded polysilicon resistors used for heating, these actuator beams form electrothermal actuators which control the lateral (in-plane) gap, and hence capacitance, of the device.

The 1st generation CMOS-MEMS variable capacitor had two key problems. First, the RF signal was routed through an electrothermal actuator such that the metal traces for the RF signal were in close proximity to those of the DC actuation signals (see Fig. 3(b)). This routing resulted in large parasitic capacitances to ground at both terminals of the capacitor (see Table I). Second, due to residual stresses in the CMOS materials, the MEMS beams curled vertically (out-of-plane) causing the interdigitated capacitance beams to be vertically misaligned (see Fig. 1(a)). This vertical misalignment reduced the maximum capacitance and limited the tuning range to less than 3:1.

(b)(a) Fig. 1. Diagram of (a) vertically misaligned beams (b) vertically aligned beams shown with virtual anchor

The 2nd generation CMOS-MEMS variable capacitor is similar in concept to the original design but improved to decrease the parasitic capacitance and increase the tuning range. The device consists of two sets of interdigitated capacitance beams; one set is fixed and the other set is movable (see Fig. 2). To change the gap and resulting capacitance, the position of the movable capacitance beams is controlled by an electrothermal actuator. A mechanical latch, also controlled by electrothermal

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actuators, is used to hold the movable capacitance beams at any of six positions without consuming power.

Electrothermal_actuatorfor_gap_control

Electrothermal_actuatorsfor_latch_control

Interdigitated capacitance_beams

Latch

Port 1

Port 2 RF_interconnect

200 µm

Fig. 2. SEM of 2nd generation CMOS-MEMS variable capacitor

The topology of the 2nd generation CMOS-MEMS variable capacitor was designed to minimize parasitic capacitance to ground. Routing which is not suspended (see Fig. 3(a)) introduces parasitic capacitance to the substrate which degrades the quality factor (Q). Routing through the electrothermal actuator beams (see Fig. 3(b)) is convenient but creates a parasitic capacitance to the DC actuation voltage, which acts as an RF ground. To avoid both the aforementioned routing methods, a suspended RF interconnect was included to pass the RF signal to the movable capacitance beams (see Fig. 2). The RF interconnect consists of several narrow (0.5 µm) beams in parallel to minimize the spring constant, which reduces the mechanical load on the actuator. This topology electrically isolates the actuators from the RF signal to minimize parasitic capacitance.

(a) (b) (c)

Air gap Air gap

RF

RF

RF

GND

RF

RF

DC

RF

RF

RF

Oxide

Metal

Silicon

Note: diagram is not to scale

Fig. 3. Diagram of RF routing through (a) unsuspended

interconnect (b) actuator beams (c) suspended interconnect

Two techniques were used to maximize the tuning range. First, both sets of capacitance beams were anchored at equivalent locations to ensure vertical alignment between the capacitance beams, which increases maximum capacitance. This topology uses

folded mechanical structures to create a virtual anchor for the movable capacitance beams [6]. This virtual anchor is elevated and angled to match the curl of the fixed capacitance beams (see Fig. 1(b)). An optical profilometer was used to verify that the resulting misalignment was no more than 1.6 µm and usually less than 1.0 µm, which is acceptable given a total beam height of 9.4 µm (see Fig. 4).

-5-4-3-2-1012

180

Vert

ical

Hei

ght (

µm)

X Direction

Vertical height along line AB-1.9 µm -0.3 µm

A B

A B

Note: adjacent beamsappear connected butare actually separate

Fig. 4. Optical profilometer scan illustrating vertical misalignment between capacitance beams

Second, the electrothermal actuators were optimized to traverse a 10 µm gap, twice that of the 1st generation device, which decreases minimum capacitance. When the two actuator materials, aluminum and oxide in this work, have similar elastic moduli, the following proportionality is accurate:

WLd /2∝ , (1)

where d is the mechanical displacement and L and W are the length and width of the actuator beam, respectively. The beam width was reduced to 1 µm and the number of actuator beams was scaled to provide enough force to displace the RF interconnect by 10 µm.

2-port S-parameters of the CMOS-MEMS variable capacitor were measured from 100 MHz to 20 GHz using a vector network analyzer (VNA) and an RF probe station. The effects of the probe pads have been removed using open-short de-embedding.

The measured 2-port characteristics were lumped into a �-model and fitted to an appropriate circuit (see Fig. 5). The resulting model consists of a series RLC circuit with a capacitance to ground at each port. The model provides a good match to the measured series impedance, which is calculated from Y21 (see Fig. 6). The extracted circuit model of the 2nd generation CMOS-MEMS variable capacitor is compared with that of the 1st generation device (see Table 1). The Q presented is the worst-case Q corresponding to the maximum capacitance position when port 2 is grounded. Measurements indicate that the tuning range has been increased from 2.5:1 to 6.9:1 and that Q has been increased by ~50%. Furthermore, the parasitic capacitances to ground, C1g and C2g, have been reduced by an order of magnitude.

510

C1g C2g

CsRs Ls Port 2Port 1

Port 2Port 1

Y22+Y21

-Y21

Y11+Y12

(b)

(a)

Fig. 5. Electrical model of CMOS-MEMS variable capacitor in (a) Y-parameters (b) circuit components

1

10

100

1,000

10,000

100,000

0.1 1 10

|1/-Y

21| (

�)

Frequency (GHz)

MeasurementExtracted Model

Cmax Position

Cmin Position

Fig. 6. Plot of measured and extracted series impedance for both minimum and maximum capacitance positions

TABLE I CMOS-MEMS variable capacitor parameters

Design 1st gen. 2nd gen. Csmin (fF) 150 54

Csmax (fF) 380 372

Csmax:Csmin 2.5:1 6.9:1

C1g (fF) 71 13

C2g (fF) 425 30

Rs (�) 7.2 4.5

Ls (pH) 522 531

Q @ 3 GHz 18 28

III. FREQUENCY-RECONFIGURABLE CIRCUITS

Using the 1st generation CMOS-MEMS variable capacitor, two frequency-reconfigurable circuits, an LNA and a PA, have been fabricated and characterized [3]. In both circuits, the variable capacitors control resonance frequencies of LC networks; using the device in maximum capacitance position enables low frequency operation while the converse is true for high frequency operation. These circuits were re-designed and simulated using the 2nd generation device to demonstrate improved circuit performance as a result of the enhanced variable capacitor.

The frequency-reconfigurable LNA is a single-stage LNA [7] modified for frequency reconfiguration (see Fig. 7). CMOS-MEMS variable capacitors, Cin and

Vin

Rs

Vbias

LB

Cin

Q1

Q2

CloadLload

Cout

Vout

VDD

LE

On-chip

Bias-T

Fig. 7. Schematic of frequency-reconfigurable LNA

-25

-15

-5

5

15

25

1 2 3 4 5S 2

1(d

B)

Frequency (GHz)

Measured w/ 1st Gen. Cap.Simulated w/ 1st Gen. Cap.Simulated w/ 2nd Gen. Cap.

S21 @ Cmax

S21 @ Cmin

Fig. 8. Comparison of S21 for LNA’s designed with 1st and 2nd generation CMOS-MEMS variable capacitors

TABLE II LNA performance summary

Design w/ 1st gen. variable capacitor

(Measured)

Design w/ 2nd gen. variable capacitor

(Simulated) Freq (GHz) 2.7 3.1 2.3 3.1

S21 (dB) 7.7 10.2 17 21 NF (dB) 4.2 4.7 2.3 2.6 S11 (dB) -30 -16 -14.7 -25 S22 (dB) - 6.9 -13.7 - 8 -18

P1dB (dBm) -10 -11 -8 -11 IIP3 (dBm) -0.5 -3 0.5 -4

Power (mW) 2.5 2.5 2.5 2.5

FoM [8] (S21/NF*PDC)

0.37 0.44 1.65 2.46

Cload, were included in the input and output LC networks to control the operating frequency of the LNA. An L-match circuit was added at the output for impedance matching, which is required only for testing purposes.

The LNA was re-designed with the 2nd generation device using the same topology and total power consumption. Simulations, which use measured S-parameters of the 2nd generation variable capacitor, show that the gain, S21, improved by approximately 10 dB for both frequencies of operation (see Fig. 8). The reduction in parasitic capacitance within the variable capacitor contributes to increased gain. Increasing the capacitance ratio doubled

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the tuning range of the LNA (see Table II). At both frequencies, the LNA figure of merit improved by ~5x.

The frequency-reconfigurable PA consists of a class E output stage driven by a class A/B pre-amplifier (see Fig. 9) [9]. CMOS-MEMS variable capacitors are included to tune the output network of the class E stage. The input of this stage is tuned using a variable capacitor in parallel with a switched capacitor to minimize area. The pre-amplifier uses a 50 � resistor for wide-band input-matching.

The PA was re-designed using the same topology but with the 2nd generation CMOS-MEMS variable capacitor. Component values were scaled to preserve the center frequency of the PA. Circuit simulations were performed using the variable capacitor model extracted from

On-chip

L2 L1 C2

C1 RLM1

VDD

Vout

L3

Vb2

C5

L4

Q1

VDD

C6

Rm

Rs

Vin

Vb1

Pre-amplifier Class E PA

C4

C3

Bias-T

Fig. 9. Schematic of frequency-reconfigurable PA

-5

0

5

10

15

20

2 2.5 3 3.5 4

Out

put P

ower

(dB

m)

Frequency (GHz)

Measured w/ 1st Gen. Cap.Simulated w/ 1st Gen. Cap.Simulated w/ 2nd Gen. Cap.

Pout @ CmaxPout @ Cmin

Fig. 10. Comparison of output power (given 4 dBm input power) for PA’s designed with 1st and 2nd generation CMOS-MEMS variable capacitors

TABLE III PA performance summary

Design w/ 1st gen. variable capacitor

(Measured)

Design w/ 2nd gen. variable capacitor

(Simulated)

Freq (GHz) 2.7 3.2 2.6 3.5

Pout (dBm) 13.7 10.1 16.8 16.9

Pin (dBm) 7.0 4.8 8.4 9.2

DE (%) 21.7 10.6 29.4 28.7

PAE (%) 17.0 7.5 25.1 23.8

HD2 (dBc) -24.2 -20.0 -19.2 -28.6

HD3 (dBc) -51.6 -46.2 -39.1 -43.8

measured results. Using the 2nd generation device, the PA exhibits a wider tuning range and higher output power due to the increased capacitance ratio and quality factor, respectively (see Fig. 10). Reduced parasitic capacitance within the variable capacitor contributes to higher efficiency but also increases harmonic distortion slightly. Nonetheless, the authors consider the PA substantially improved by the 2nd generation variable capacitor.

IV. CONCLUSION

The improved CMOS-MEMS variable capacitor has a measured capacitance ratio of 6.9:1 and a Q of 28 at 3 GHz. The parasitic capacitances at both terminals are reduced by an order of magnitude when compared with those of the previous topology. This enhanced variable capacitor was used in circuit simulations of two frequency-reconfigurable circuits, an LNA and a PA. Results for both circuits show an improvement in total tuning range as well as increased gain for the LNA and higher output power and efficiency for the PA.

ACKNOWLEDGEMENT

This research was sponsored by C2S2, ITRI Labs at CMU, the NDSEG Fellowship Program, and the AFOSR.

REFERENCES

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[3] A. Jajoo, L. Wang, and T. Mukherjee, “MEMS Varactor Enabled Frequency-Reconfigurable LNA and PA in the Upper UHF Band,” IEEE IMS Dig., June 2009.

[4] G. K. Fedder, S. Santhanam, M. L. Reed, S. C. Eagle, D. F. Guillou, M. S.-C Lu and L. R. Carley, “Laminated High-Aspect Ratio Microstructures In A Conventional CMOS Process,” Sensors & Actuators, vol. A57, no. 2, pp 103-110, March 1997.

[5] P. J. Gilgunn, J. Liu, N. Sarkar, and G. K. Fedder, "CMOS-MEMS Lateral Electrothermal Actuators," J. Microelectromech. Syst., vol. 17, no. 1, Feb. 2008.

[6] G. Zhang, H. Xie, L. E. deRosset and G. Fedder, “A Lateral Capacitive CMOS Accelerometer with Structural Curl Compensation,” IEEE MEMS, pp. 606-611, Jan. 1999.

[7] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE JSSC, vol. 32, no. 5, pp. 745-759, May 1997.

[8] K. W. Kobayashi et. al., “Ultra-low dc power GaAs HBT S- and C-band low noise amplifiers for portable wireless applications,” IEEE MTT, vol. 43, no. 12, pp. 3055-3061, Dec. 1995.

[9] N. Sokal, “Class-E RF Power Amplifiers,” QEX, no. 204, pp 9-20, Jan/Feb 2001.

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