Abstract— This paper presents a novel design of lowpower charge redistribution successive approximation ana-log to digital converter(CR-SAR ADC). During its conver-sion, the voltage swing of the capacitor array is reduced tohalf of the voltage reference without decreasing the ADCdynamic range. The reduced voltage swing results in a sig-nificant reduction of ADC power consumption. Also, theproposed design requires only half of the total capacitancethat is used in a traditional CR-SAR ADC with the sameresolution. MATLAB simulations are performed to com-pare the power consumption due to charging the capacitorarray in the proposed and previous low power CR-SARADC’S. The proposed circuit is implemented using a 0.13µCMOS technology. Post-layout simulation shows that theproposed converter consumes 63% less energy compared toa traditional CR-SAR ADC.
I. Introduction
The charge redistribution successive approximation reg-ister (CR-SAR) analog to digital converter(ADC) circuitsare widely used in many applications that require lowpower consumptions, such as wireless sensor networks,biomedical instrumentation circuits and battery powereddevices. This is due to its ability to achieve medium speedand medium resolution with low power consumption. Asshown in Figure 1, A CR-SAR ADC includes a compara-tor, a binary weighted capacitor array and SAR digitallogic. An N-bit CR-SAR ADC consists of N+1 capacitorshaving a total capacitance of 2NC0, where C0 is the unitcapacitance. Due to this large capacitance, most of theenergy consumed by a CR-SAR ADC is used to charge itscapacitance array. Several methods [1-5] were previouslyproposed to reduce the energy consumed by the capacitorarray. More details of these techniques will be discussed inSection 2.
This paper presents a novel CR-SAR ADC design to re-duce the energy consumed by the capacitor array. The ref-erence voltage used in the proposed design is half of the ref-erence voltage used in traditional CR-SAR ADC’s withoutsacrificing the ADC dynamic range. The reduced voltagereference level drastically decreases the energy consumedby the capacitor array. Also the total capacitance used inthe proposed method is half of that used in a traditionalCR-SAR ADC that has the same resolution. Post-layoutsimulations show that the proposed technique reduces over60% of energy compared to traditional design.
The rest of the paper is organized as follows. Section
Vref
SARand
Control Logic
Sn S3 S2 S1
Dn
Dn-1
Dn
Vin
Digital OutputBn,........,B2,B1
SS
Cn Cn-1 C3 C2 C1 C0
VX
Fig. 1. Traditional SAR-ADC
2 reviews previous design techniques for low power CR-SAR ADC. The proposed technique is discussed in Section3. Simulation results are presented in Section 4 and thepaper is concluded in Section 5
II. Related Work
Several techniques were proposed previously to reducethe power consumption of the capacitor array in CR-SARADC. The technique proposed by Ginsburg et.al. [1] avoidsthe charge wastage during the down transition by splittingthe Most Significant Bit (MSB) capacitor of the array intoa binary-scaled sub-array. During the first clock cycle theMSB sub-array is charged to Vref . If the output of the
comparator indicates Vin <Vref
2 , instead of throwing awaythe charge on the MSB capacitor, the charge will be reuti-lized during the conversion of the remaining bits. However,the limitation of this technique is that it only save powerif Vin <
Vref
2 .In [2], Ricky et.al. proposed a novel successive approx-
imation (SA) technique, which has two step search algo-rithm and utilizes two unequal sized binary-weighted ca-pacitor arrays to save the switching energy. It works in twophases. First phase will perform a coarse-level search todetermine MSB’s. The second phase conducts a fine-levelsearch to determine the Least Significant Bits(LSB’S). Thistechnique consumes less power mainly due to two reasons.First, small capacitors are used for MSB conversion, thusit consumes less power during charging and discharging ofcapacitor array. Second, although a large capacitor arrayis used during fine level conversion, only a small portion ofthem is to be charged and discharged. However, this circuit
requires large area and potentially introduces nonlinearitydue to parasitic capacitance associated with its samplingcapacitor.
The method proposed by Lampinen [3] consists of a dou-ble SA algorithm. The circuit operates in two steps. Thefirst step logarithmically determines the coarse-level of thesignal. The second step uses the binary search algorithmsimilar to the conventional SA algorithm. In this methodif the input voltage is low there is no need to go throughall the upper bits as in conventional method. Therefore,it saves the switching energy. Nevertheless the power sav-ing efficiency of this technique strongly depends upon theinput voltage level. In [4] Dragan et.al proposed two en-ergy efficient SAR-ADC control algorithms that reduce thenumber of steps required for a given conversion. The basicassumption used in this approach is the difference betweentwo successive analog input samples is less than a specificvalue called as bandsize. These algorithms utilize band sizeto determine the MSB’s according to the previously con-verted digital value. Then the algorithms perform conver-sion to find LSB’s. But the effectiveness of these algorithmsdepends on the input signal. Chang et.al., proposed an en-ergy saving switching sequence to determine the MSB in afully differential SAR ADC circuit [5]. After determiningthe MSB, the energy saving switching sequence is combinedwith the capacitor splitting technique to further reduce theswitching energy. In [6] Hong et.al proposed a low voltageCR-SAR ADC with bootstrapped sampling switch. En-ergy consumed per conversion step was calculated by usingfigure of merit. A small unit capacitance (24fF) is used inthis circuit in order to achieve low power consumption.
III. Proposed CR-SAR ADC circuit
Vref /2
Sn-2 S2 S1
Cn-1 C2C1 C0
VinSsample
CS
To SAR
Vref /2
Cn-2
VX
SA
Sn-1
Fig. 2. Proposed CR-SAR ADC
The proposed CR-SAR ADC architecture is shown inFigure 2. Compared to previous low power CR-SAR ADCdesigns, the significant difference of the proposed techniqueis the capacitor array is charged only to half of the volt-age reference. This will significantly minimize the energyconsumed by the capacitor array. The circuit operates intwo phases sampling and redistribution. During the sam-pling phase, the switch Ssample is closed. At the same time
switch SA is connected toVref
2 for sampling the input volt-age Vin. At the starting of redistribution phase the Ssample
is open and the sampling capacitor CS holds the value forrest of the conversion process. Also all the capacitor bot-tom plates in the capacitor array are connected to
Vref
2 .Since the initial charge on the capacitors array is zero, thevoltage at node VX will be
Vref
2 (ignoring the parasitic ca-pacitance). During the first clock cycle of the redistributionphase the sampled input voltage Vin is compared with VX
which isVref
2 . The comparator output produces the MSBof the ADC output. If the comparator output is 1 then SA
switches to ground. Therefore the voltage at the positiveinput of the comparator becomes Vin− Vref
2 . Otherwise, SA
remains connected toVref
2 . Starting from the second clockcycle, ADC operates very similar to traditional CR-SARADC. At the beginning of ith cycle, capacitor Cn−i+1 firstconnected to ground. Then the node voltage VX becomes:
VX =Ceq ∗ Vref
2nC0(1)
where Ceq is the total capacitance connected toVref
2 andC0 is the unit capacitance. If the comparator output is 1then capacitor Cn−i+1 switches back to
Vref
2 otherwise thecapacitor remains connected to ground. Even though thereference voltage used in the proposed design is half whencompared to traditional one, the proposed CR-SAR ADCcircuit digitalizes any analog input between 0 and Vref .
Vref/2
SA
Cs CP
SsampleVin Va
Fig. 3. Impact of parasitic capacitance in the sample and hold circuit
Since the voltage at the positive input of the comparatormay also experience voltage change during the conversion.The parasitic capacitance at that node will affect the ac-curacy of the ADC. With considering the lumped parasiticcapacitance CP the sample and hold circuit used in the pro-posed design is sketched in Figure 3. Ideally if SA switchesto ground after the first clock cycle, the voltage Va at thecomparator positive input should be Vin − Vref
2 . Consider-ing parasitic capacitance it is easy to show the actual valueis:
Va = Vin − Vref
2+
CP
CP + CS
Vref
2(2)
Clearly the error introduced by the parasitic capacitance(the third term on the right hand side of Equation 2) isconstant. Therefore, it is easy to be corrected.The proposed architecture consumes significantly less en-
ergy due to the following factors. First, the voltage swing
of capacitor array is reduced to half of the reference volt-age. Second, the total capacitor array has been reducedby half, because of availability of
Vref
2 . The reduced ca-pacitor array significantly reduces the area required by theproposed CR-SAR ADC. It is easy to show that the powerconsumption associated with charging the capacitor arraysin the traditional and proposed CR-SAR ADC circuits canbe estimated using following two equations:
Eproposedn−bit = 2(n−5)C0V
2ref +
1
2CS(Vin − Vref
2)2
+n∑
i=2
2(i−6)5C0V2ref
(3)
Etraditionaln−bit =
1
22nC0V
2in +
n∑i=1
2(i−3)5CV 2ref (4)
The detailed derivation of Equation 4 can be found in [2]and Equation 3 can be derived similarly [7]. For 10-bitADC circuits, the above equations indicate that over 89%of energy consumed by charging the capacitor array can besaved by the proposed design.Although a reduced voltage reference (
Vref
2 ) is used ,the input range of the proposed ADC circuit remains thesame as that of conventional CR-SAR ADC which requiresvoltage reference of Vref . Also the use of reduced voltagereference does not increase the circuit complexity in manyapplications. For example, instead of using bandgap volt-age reference to generate voltage level Vref , we can use
the same bandgap reference to generateVref
2 with minormodification.
IV. Experimental Results
To compare the energy saving in the capacitor array ofthe proposed design with previously reported low powerCR-SAR ADC circuits, MATLAB simulations are per-formed to calculate the energy associated with chargingthe capacitor array. The method to estimate energy con-sumption in MATLAB simulations similar to Equations 3and 4. In MATLAB simulation we assume the ADC res-olution is 10 bit, Vref is 1.2V and the unit capacitance is100fF. The obtained energy consumption for different in-put levels are plotted in Figure 4. Note that the X- axisrepresents the digital output corresponding to the analoginput. Clearly the proposed CR-SAR ADC consumes sig-nificantly less energy than traditional and charge splittingADC circuits technique. Although the circuit presentedin [2] has slightly smaller energy consumption than ourproposed design, it requires much larger area and also itsperformance is potentially affected by nonlinear offsets in-troduced by parasitic capacitance at the positive input ofthe comparator. Detailed discussion about this affect isgiven in Appendix I.In addition to MATLAB simulations we also imple-
mented two 10-bit CR-SAR ADC circuits using the tra-ditional and proposed architectures with a 0.13µ CMOStechnology. The layouts of traditional and proposed CR-SAR ADC’s are shown in Figures 5 and 6 respectively. The
ouput code
Sw
itch
ing
Ene
rgy
in p
J
OUTPUT CODE VS SWITCHING ENERGY
200 400 600 800 1000
20
40
60
80
100
120
TraditionalCap Split [1]Proposed Two Step SA [2]
Fig. 4. Average energy consumption at each output code
area of the two designs are 0.48 µm2 and 0.29 µm2 respec-tively the smaller area of the proposed design is mainly dueto the reduced capacitor array. The power supply as wellas Vref for the design are 1.2V and also the unit capaci-tance value is 100fF. The value of the sampling capacitoris 600fF.
A rail-to-rail comparator is used in this design. Post-layout simulations are performed to compare the energyconsumption of the traditional and proposed designs. Inthe simulation setup of ADC, the input clock frequency is10 MHz. The signal fed to ADC is a sinusoidal waveformwith a frequency of 81.817KHz. Its magnitude is 0.6V withan offset of 0.6V. The average power consumption obtainedfrom the post-layout simulations are shown in Table 1. It
shows that over 60% of power reduction is achieved by theproposed design. Although the CR-SAR ADC circuit in [6]consumes less energy per conversion step, they use figureof merit to calculate energy consumed per conversion stepand also their sampling rate is very less when compared toproposed design
We also investigated the power consumption of eachADC block using schematic simulations and the results arelisted in Table 2. Also simulation results show that thepower consumption associated with charging of the capac-itor array in the proposed design is roughly 86% less thanthat of traditional design. This number is smaller than thepower saving calculated using post layout simulation. Thisis mainly caused by the parasitic capacitance associatedwith capacitors and switches used in the capacitor array.Figures 4 and 8 show the current drawn by the capacitorarray and its integration for both traditional and proposedCR-SAR ADC’s.
TABLE II
Percentage of energy consumption of each ADC block
Block Name Traditional(PJ) Proposed(PJ)Capacitor array 67% 26%
Logic 6% 18%Comparator 26% 55%
Finally, Figure 9 shows the voltage swing at the com-parator input and output of the proposed design during theconversion. In Figure 9, the first row represents the clock ofthe ADC circuit, second row shows the complimented com-parator output , third row represents the resultant voltageof the capacitor array and the wave form in the fourth row
Fig. 7. Current drawn by capacitor array and current integrationwaveforms of traditional CR-SAR ADC
Fig. 8. Current drawn by capacitor array and current integrationwaveforms of proposed CR-SAR ADC
represents the voltage on the sampling capacitor. It can beseen that after the MSB conversion, the comparator out-put is 1(its complimented output is 0). According to theprevious discussion in Section 3, the switch SA connects toground. This results in the decrease of the voltage at thepositive input terminal of the comparator.
V. Conclusions
A novel low-power CR-SAR ADC is presented in thispaper. In the proposed design, the voltage swing acrossthe capacitor array is reduced to half of the reference volt-age. This significantly decreases the power consumption ofthe proposed CR-SAR ADC circuit without sacrificing thedynamic range of the converter. The total capacitance ofthe capacitor array used in the proposed technique is halfof the total capacitance of the conventional design. There-fore the proposed circuit occupies smaller area. MATLABsimulations are performed to compare the power consump-tion due to charging the capacitor array in the proposedand previous low-power CR-SAR ADC’S. Post-layout sim-ulations were performed for both traditional and proposedCR-SAR ADC architectures and the energy consumption
of the proposed ADC is 63% less than that of traditionaldesign. Thus the proposed CR-SAR ADC has significantlyless power consumption.
Appendix
I Parasitic Analysis
Vin
Vref
CS
CP
Ssample
Va
C1 C2
Fig. 10. The effect of parasitic capacitance in the ADC [2]
The sampling circuit used in [2] is shown in Figure 10. CS is the sampling capacitor, CP is the parasitic capac-itance, C1 AND C2 are the sum of the capacitances con-nected to Vref and ground respectively. Ideally the voltageat Va is given by
Va = Vin +C1Vref
C1 + C2(5)
However, due to parasitic capacitance, voltage at node Va
will be
Va =(CS + CP )(CS + C1 + C2) ∗ Vin
(CS + CP )(CS + C1 + C2)− (C2S)
+C1CSVref
(CS + CP )(CS + C1 + C2)− (C2S)
(6)
The Equation 6 is simplified into
Va = Vin + VinCS
C1 + C2+
C1Vref
C1 + C2(7)
Comparing Equations 5 and 7 it is easy to see that thesecond term at right hand side of the Equation 7 is a errorterm, whose value depends on Vin and hence cause nonlin-ear errors on the ADC output.
References
[1] B.P. Ginsburg and A.P. Chandrakasan, “An energy-efficientcharge recycling approach for a sar converter with capacitive dac,”in Circuits and Systems, 2005. ISCAS 2005. IEEE InternationalSymposium on, May 2005, pp. 184–187 Vol. 1.
[2] Ricky Yiu kee Choi and Chi ying Tsui, “A low energy two-stepsuccessive approximation algorithm for adc design,” Quality Elec-tronic Design, International Symposium on, vol. 0, pp. 317–320,2008.
[3] H. Lampinen, P. Perala, and O. Vainio, “Novel successive-approximation algorithms,” in Circuits and Systems, 2005. IS-CAS 2005. IEEE International Symposium on, May 2005, pp.188–191 Vol. 1.
[4] D.B. Stankovic, M.K. Stojcev, and G.L. Djordjevic, “Power re-duction technique for successive-approximation analog-to-digitalconverters,” in Telecommunications in Modern Satellite, Cableand Broadcasting Services, 2007. TELSIKS 2007. 8th Interna-tional Conference on, Sept. 2007, pp. 355–358.
[5] You-Kuang Chang, Chao-Shiun Wang, and Chorng-Kuang Wang,“A 8-bit 500-ks/s low power sar adc for bio-medical applica-tions,” in Solid-State Circuits Conference, 2007. ASSCC ’07.IEEE Asian, Nov. 2007, pp. 228–231.
[6] Hao-Chiao Hong and Guo-Ming Lee, “A 65-fj/conversion-step0.9-v 200-ks/s rail-to-rail 8-bit successive approximation adc,”Solid-State Circuits, IEEE Journal of, vol. 42, no. 10, pp. 2161–2168, Oct. 2007.
[7] Ramgopal Sekar, “Low power techniques in successive approx-imation register (sar) analog-to-digital converter,” M.S. thesis,Southren Illinois University Carbondale, AUG. 2009.
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