Improved Linearity CMOS Active Resistor Based

on Complementary Computational Circuits

Cosmin Popa

Faculty of Electronics, Telecommunications and Information Technology University Politehnica of Bucharest

Bucharest, Romania

Abstract-A new active resistor circuit will be presented in

this paper. The main advantages of the original proposed

implementation are the improved linearity, the small area

consumption and the improved frequency response. An original

technique for linearizing the I(V) characteristic of the active

resistor will be proposed, based on the "mirroring" of the Ohm

law from the input pins to another reference pins. The area

consumption of the active resistor will be minimized by

replacing the classical MOS transistor by a FGMOS (floating

.Qate MOS) device. The circuit frequency response is very good

as a result of biasing all MOS transistors in the saturation region

and of a current-mode operation of the square-root circuit. The

circuit is implemented in 0.35Jlm CMOS technology on a die

area of 25Jlm X 35Jlm, being supplied at ± 6V . The circuit

presents a very good linearity (THD < 0.6% ) for an extended

range of the input voltage (- 5V < V x - Vy < 5V). The

tuning range is extremely large comparing with the previous

reported active resistors: ± (600kQ - 6MQ) , the circuit being

able to simulate both positive and negative active resistances.

Keywords-linearity, active resistor, computational circuits

I. INTRODUCTION

CMOS active resistors are very important blocks in VLSI analog designs, mainly used for replacing the large value passive resistors, with the great advantage of a much smaller area occupied on silicon and of the possibility of obtaining very large values of the equivalent resistance (very useful in CMOS VLSI designs). Their utilisation domains includes amplitude control in low distortion oscillators, voltage controlled amplifiers and active RC filters. These important applications for programmable floating resistors have motivated a significant research effort for linearising their current-voltage characteristic.

The first generation of MOS active resistors [I] , [2] used MOS transistors working in the linear region. The main disadvantage is that the realised active resistor is inherently nonlinear and the distortion components were complex functions on MOS technological parameters.

A better design of CMOS active resistors is based on MOS transistors working in saturation [3]-[IS]. Because of the quadratic characteristic of the MOS transistor, some linearisation techniques were developed in order to minimize the nonlinear terms from the current-voltage characteristic of the active resistor. Usually, the resulting linearisation of the I - V characteristic is obtained by a first-order analysis. However, the second-order effects which affect the MOS transistor operation (mobility degradation, bulk effect and short-channel effect) limits the circuit linearity introducing odd and even-order distortions, as shown in [4]. For this reason, an improved

linearization technique has to be design to compensate the nonlinearities introduced by the second-order effects.

II. THEORETICAL ANALYSIS

The original idea for implementing a linear current-voltage characteristic of the active resistor, similar to the characteristic of a classical passive resistor is to "mirror" the Ohm law from the input pins of the circuit to another pins used for applying an external reference voltage and an external reference current. The equivalent resistance of the active structure will be very easily controllable by the ratio between the reference voltage and the reference current. Because of the requirements for a good frequency response, only MOS transistors working in saturation could be used and a current­mode operation of an important part of the circuit will be implemented, the original choose being to use the quadratic and the square-root functions as complementary functions. In order to reduce the silicon occupied area, classical MOS devices have been replaced by FGMOS transistors, having the most important advantage of reducing the circuit complexity, reflected in the silicon area.

A. The block diagram of the FGMOS active resistor

The structure of the proposed active resistor is based on four important blocks: two voltage-current squarers, a current square-root circuit, a current divider circuit and a current-pass circuit, named SQ, SQR, DIV and I, respectively on the block diagram from Figure I.

Vo

10 O------7---� 10

Vx Ixy Vy

, , �-- - ----- ------- --- ---- ------ ------- ------- ------ - - - ---

Figure I. The block diagram of the active resistor

978-1-4244-8157-6/10/$26.00 ©201O IEEE 450 ICECS 2010

The 1 Xy current is proportional to the square-root of the

product between 1 and 10 currents, while 1 is proportional with

the ratio of 12 and 1 j currents. Each of these two last currents is

proportional with the square of V X - Vy and Vo voltages,

respectively. The result of this original proposed implementation of the circuit will be a linear relation between the differential voltage

across the two pins of the active resistor, V X - Vy and the current

passing through it, 1 xy .

B. The FGMOS transistor

The FGMOS transistor is a MOS transistor whose gate is floating. The drain current of a FGMOS transistor with n-input gates in the saturation region is given by the following relation:

(1)

where K = f.1 n Cox (W / L) is the transconductance parameter of

the transistor, f.1n is the electron mobility, Cox is the gate oxide

capacitance, W / L is the transistor aspect ratio, ki, i = 1, ... , n are

the capacitive coupling ratios, Vi is the i -th input voltage, Vs is

the source voltage and V T is the threshold voltage of the transistor.

The capacitive coupling ratio is defined as:

(2)

Ci are the input capacitances between the floating-gate and each

of the i -th input and Cox is the gate-source capacitance which is

equal to (2/ 3)Cox for operation in the saturation region. All the

overlap capacitances are assumed to be considerably smaller than n

capacitances summation L Ci +CGS' Equation (I) shows that i=j

the FGMOS transistor drain current in saturation is proportional to the square of the weighted sum of the input signals, where the weight of each input signal is determined by the capacitive coupling ratio of the input.

C. The voltage-current squarer

The new proposed squarer is based on the perfect symmetrical structure presented in Figure 2. The utilization of a FGMOS device will strongly decrease the silicon occupied area of the square circuit.

The output current expression has a linear dependence on the

drain currents of T x, Ty and TZ transistors:

12 =IX +ly - IZ' (3)

It results a quadratic dependence of the output current 12 on the

differential input voltage V X - Vy :

(4)

r-------�------�--------------�------�-o VDD

L-------�-------+----------------------�_o -VDD Figure 2. The voltage-current squarer

In a similar way, the other squarer from the block diagram will

compute the following expression of 1 j current:

D. The square-root circuit

K 2 Ij=--VO'

4 (5)

The square-root circuit is presented in Figure 3, designed using exclusively MOS active devices biased in the saturation region for improving the circuit frequency response.

r-----�--------�----�--� VDD

10

10

Figure 3. The CMOS square-root circuit

For a strong inversion of all the MOS transistors from Figure 3, it is possible to write that:

equivalent with:

1=I+I0+2�101 . (7)

Implementing the proper linear relation between the previous current of the square-root circuit:

(8)

451

the output current of the circuit from Figure 4 will be proportional to the square-root of the input current:

Ixy=2�/OI . (9)

The current lOis named reference current.

E. The divider circuit

The divider circuit could be obtained using two square-root circuits from Figure 3 connected as it is shown in Figure 4. The computed

functions are 101 = 2.JI;i and 102 = 2 � I 2 1 O . Because

101 = 102 , the function implemented by the circuit from Figure 4

will be:

(10)

F. The current-pass circuit

The necessity of designing this circuit is derived from the requirement that the same current to pass between the two output pins, X and Y. The implementation in CMOS technology of this circuit is very simple, consisting in a simple and a multiple current mirrors (Figure 5).

r--_- --.._---�-_--_1_--�o__�_---.._--o__-�---_1_---o__-_-__O vDI)

I,

Figure 4. The divider circuit

r------.------.----<J VI)I)

Ixy Vy

Vx

'-----_---0 -VI)I) Figure 5. The current-pass circuit

G. The linear characteristic a/the FGMOS active resistor

U sing relations (7), (8), (12) and (13), it results that the equi valent resistance of the active resistor having the block diagram presented in Figure 1 is:

Vx - Vy RECH. =

I xy

Vo =--

210 (II)

The great advantage of the previous presented circuit is that the value of the equivalent active resistance could be very easily

controlled by modifying the ratio of a reference voltage V 0 and a

reference current 10, The proposed principle of operation of the

active resistor is equivalent with a "mirroring" of the Ohm law from

the input pins V X and Vy to another pins (inputs for V 0 voltage

and 10 current). The mismatches between the corresponding

devices slightly affect the circuit linearity. It exists specific techniques for reducing the impact of mismatches, based on an anti-

452

parallel connections of two quasi-identical active resistor structures, having different biasing and proper controlled asymmetries.

Ill. SIMULATED RESULTS

The circuit was implemented in 0.35J..Lm CMOS technology on a

die area of 25J..Lm X 35J..Lm , being supplied at ± 6V . The SPICE

simulation of the active resistor (for multiple values of the equivalent resistance) is presented in Figure 6. The circuit presents a

very good linearity (THD < 0.6%) for an extended range of the

input voltage ( - 5V < V x - Vy < 5V). The tuning range is

extremely large comparing with the previous reported active

resistors: ± (600kQ - 6MQ) , the circuit being able to simulate

both positive and negative active resistances. An other important advantage of the proposed structure is referring to the possibility of operating also as floating resistor and as ground-connected resistor.

'x,

'-----'--'_--1-_---1-_--1-_-'-_-1---_-'-'-_'-----'--'_--1 Vx -v, -sv .oW ·3V ·2V -IV IV 2V 3V 4V 5V

Figure 6. The simulation I xy (V X - Vy ) for the active resistor structure

A comparison between the proposed circuit and the previous reported active resistors is presented in Table l.

Table 1 Techn. Supply Operating Tuning range (lim) voltage range

(V) (V) This 0.35 ±6 ±5 ±(600ill-work 6MQ)

[6] 2 10 2.4 56-112 kQ [7] 3 10 8 -

[8] 2 5 3 ±5%

THD Floating Negative (%) resistance

0.6 yes yes

1 yes no

±1 no no 0.01 no no

[9] BiCMOS - 10 - 0.0032 no no [10] 0.5 3.3 2 -[11] 0.5 3.6 2.5 -[12] 0.8 3.3 3 < 93.3 ill [13] 1.5 ±5V - 2.6-5.1 MQ

IV. CONCLUSIONS

A new active resistor circuit has been presented in this paper. The main advantages of the original proposed implementation are the improved linearity, the small area consumption and the improved frequency response. An original technique for linearizing the J(V) characteristic of the active resistor will be proposed, based on the "mirroring" of the Ohm law from the input pins to another reference pins. The area consumption of the active resistor will be minimized by replacing the classical MOS transistor by a FGMOS (Eloating Qate MOS) device. The circuit frequency response is very good as a result of biasing all MOS transistors in the saturation region and of a current-mode operation of the square-root circuit. The circuit is

implemented in 0.35�m CMOS technology on a die area of

25�m X 35�m, being supplied at ± 6V. The active resistor

presents a very good linearity (THD < 0.6%) for an extended

range of the input voltage ( - 5V < V x - Vy < 5V). The tuning

range is extremely large comparing with the previous reported

active resistors: ± (6001cQ - 6MQ), the circuit being able to

simulate both positive and negative active resistances.

AKNOWLEDGEMENTS The work has been co-funded by the Sectoral Operational Programme Human Resources Development 2007-2013 of the Romanian Ministry of Labour, Family and Social Protection through the Financial Agreement POSDRU/89/1.5/S/62557.

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