A Novel TCAD-Based Methodology to Minimize the Impact of Parasitic Structures on ESD Performance

Nicholas Olson, Gianluca Boselli*, Akram Salman* and Elyse Rosenbaum Department of Electrical & Computer Engineering

University of Illinois at Urbana-Champaign Urbana, IL USA

naolson@illinois.edu

*Texas Instruments Inc.

Dallas, Texas USA

Abstract—During an ESD event, breakdown of a parasitic bipolar transistor can lead to chip failure. For a variety of ESD protection networks, it is demonstrated that TCAD simulations correctly predict the stress level at which failure occurs due to bipolar breakdown. A procedure to characterize the interaction between any two N-type diffusions and the ESD cells to which they are connected is presented.

Keywords- Electrostatic Discharge; ESD; Parasitic Bipolar; TCAD

I. INTRODUCTION It is well established that the breakdown of a parasitic NPN

during an ESD event can lead to chip failures [1]. Parasitic NPNs may be formed between any pair of two N-type diffusions. One such scenario is illustrated in Figure 1; in this figure, the ground net is tied to the substrate, which forms the base of the parasitic NPN. During an ESD event from pin POS to pin NEG, the substrate is at a positive potential with respect to pin NEG, thus forward biasing the base-emitter junction of any parasitic NPNs connected between the two pins. This forward bias condition lowers the breakdown voltage, Vt1, of the parasitic bipolar transistor [2]. Parasitic NPNs are often formed between circuit blocks and it may not be possible to engineer all the parasitic devices to safely operate in breakdown; therefore, the ESD engineer’s objective is to avoid parasitic bipolar breakdown. Achieving this objective is non-trivial because the breakdown voltage varies with the layout.

Multiple strategies for preventing parasitic NPN breakdown [2, 3, 4] have been disclosed in the literature, with the most common being to space the N-regions farther apart. The challenge is to optimize the spacing so as to ensure a robust design without unnecessarily sacrificing silicon area. The breakdown voltage depends on the location of the substrate taps, the doping profiles of the N-regions and the base, the ESD clamp characteristics and the orientation of the N-regions with respect to each other; thus, there is not a single value for the optimum spacing. Process complexity increases the number of variables. For example, in a modern BiCMOS process, there may be over 10 types of N-regions (acting as collectors/emitters) and more than 3 types of P-regions (acting as bases), leading to hundreds of different types of parasitic devices. It is necessary to develop a methodology to efficiently and accurately determine the interaction between any two N-type regions and the ESD cells connected to them, without the

Figure 1. Example ESD network. Solid arrow depicts intended path for ESD

current and dashed arrow represents a parasitic path, for the case of positive stress on pad POS with respect to pad NEG.

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ESD2

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ESD1

2 Figure 2. Test structure. Shaded regions are N-regions.

need to run hundreds of test structures. This paper presents such a methodology; it requires only a limited number of 2D TCAD simulations to be performed.

II. MEASUREMENTS

A. Test Structures Test structures consisting of two ESD clamps and a built-in

NPN were fabricated in a state-of-the-art BiCMOS process. Figure 2 depicts a conceptual view of the test structure layout. Each ESD clamp consists of a snapback device and a diode for reverse conduction. Pad 2 is connected to the P+ guardrings that surround the ESD clamps. A variety of N-type and P-type diffusions are available in this process technology and are listed in Table I. This paper presents results only for a subset of these diffusions. Multiple N-type diffusions may be combined to form a single N-region (for example, see Figure 3B). The

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test structures vary in terms of the N-regions used to form the emitter and collector of the parasitic NPN and also the spacing between the two N-regions. Figures 3A and 3B show two of the different NPNs that were investigated. High voltage N-Well (HV-NW) is a N-well diffusion that is deeper than the normal N-well and can reach the N-buried layer, NBL. N-SINKER is similar to the HV-NW, except it has a higher doping concentration.

B. Testing Method Pulsed I-V characteristics were obtained using a TLP

system with a 100 ns pulse-width and 10 ns rise-time. First, pulses are applied between pads 1 and 2, and then between pads 2 and 3 to generate the I-V curves (taken to failure) of the stand-alone ESD clamps. Next, the pulsed I-V characteristic is measured between pad 1 and pad 3 on a fresh structure. This exercises the whole ESD network with the parasitic NPN in parallel. Finally, the first two I-V curves are summed; that is, current is plotted as a function of V12 + V23. The resulting curve is what is expected if there were no parasitic device and is hereafter referred to as the “summed I-V.”

The summed I-V is compared with the I-V curve measured between pad 1 and pad 3. If the pad 1 to pad 3 measurement produced failure at a lower current, it is concluded that the parasitic bipolar was driven into breakdown and the test is classified as a fail. This is a conservative definition of failure since in a normal design process, an ITARGET would be specified as the maximum expected current through the ESD network. Therefore, the pass threshold would be lowered from the ESD protection device failure level.

C. Results For a given pair of N-regions, the pass/fail results are

tabulated as a function of the spacing and the type of ESD clamp. Examples are given in Tables IIA and IIB, which contain the measurement results for the specific test structures shown in Figures 3A and 3B. Tables IIA and IIB are only a small portion of the full results grid, which contains data for test structures that contain all allowed combinations of ESD clamps and diffusions from Table I. In Table II, ESD1 through ESD4 denote four different bipolar-based snapback ESD clamps that have increasingly larger trigger voltages; the higher trigger voltages are achieved by cascoding the protection devices. The pulsed I-V characteristics of these ESD clamps are shown in Figure 4. The data in Table II indicate that, as expected, the likelihood of failure increases when the ESD clamp trigger voltage is increased and/or the N-region spacing is decreased. The data in Table II also show that the addition of higher doped diffusions is detrimental. This is unsurprising since higher doped junctions are known to breakdown at lower voltages.

Table II shows that the minimum spacing needed to avoid parasitic NPN triggering is variable, depending on the type of clamp and N-diffusion. To avoid applying overly conservative spacing rules to all configurations, a comprehensive matrix of ESD cells and parasitics needs to be created and the corresponding failure levels determined. Given the size of the matrix, it is NOT feasible to do this at the silicon level. Thus, in the next section, a TCAD-assisted procedure for characterizing

critical elements in the matrix of ESD cells and parasitics is presented.

TABLE I. LIST OF AVAILABLE DIFFUSIONS THAT MAY FORM PARASITIC NPN DEVICES. THE TWO N-DIFFUSIONS FORMING THE NPN MAY BE OF THE SAME OR DIFFERENT TYPES .

N Diffusions P Diffusions N+ P+

N-Well P-Well High Voltage Well P-sub

N-SINKER Moat NBL PBL

Figure 3. Cross section of parasitic structures. A: HV-NW. B: HV-NW+NBL+N-SINKER.

TABLE II. PASS/FAIL GRID. HORIZONTAL LINES (GREEN)=PASS. VERTICAL LINES (RED)=FAIL. NO LINES (GRAY)=NO DATA AVAILABLE. TABLES A AND B EACH CONTAIN DATA FOR A FIXED PAIR OF N-REGIONS WITH VARIABLE SPACING (I.E. BASE WIDTH OF THE NPN). IN BOTH EXPERIMENTS, THE MAXIMUM SPACING IS IDENTICAL AND ALL OTHER SPACINGS ARE NORMALIZED WITH RESPECT TO THIS VALUE. CIRCLED CASE WILL BE REFERENCED LATER.

Primary Protection

Device

Device in Diode

OperationESD1 ESD2ESD2 ESD1ESD3 ESD4ESD4 ESD3

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Device

Device in Diode

OperationESD1 ESD2ESD2 ESD1ESD3 ESD4ESD4 ESD3

0.23 0.36 0.44 0.55 0.72 1Normalized Spacing

HV-NW+NBL+N-Sinker to HV-NW+NBL+N-Sinker

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Figure 4. TLP I-Vs of clamps ESD1 through ESD4 used in Table II. The added R in the legend indicates a clamp was tested in reverse operation mode.

III. TCAD-ASSISTED BREAKDOWN PREDICTION TCAD simulations have been shown to be useful in

analyzing ESD networks with parasitic bipolar transistors [5]. This suggests it may be possible to develop structure-specific spacing rules without needing to fabricate an unreasonable amount of test structures. In the rest of this section, a method for using TCAD simulations to predict NPN breakdown and to develop spacing rules is presented.

A. Methodology First, 2D quasi-static TCAD simulations are used to obtain

the stand-alone I-V characteristics of the NPN devices of interest. The substrate bias is varied and the collector voltage is ramped up. As indicated in Figure 5, the potential at the base of the parasitic bipolar transistor will be less than the applied substrate bias voltage, and this potential difference is a function of the substrate tap placement. Figure 6 shows an example set of simulated I-V curves. Using the data of Figure 6, a plot of Vt1 vs. substrate bias can be generated. The next step is to combine this data with the summed I-V. An example summed I-V is shown in Figure 7. Figure 7 also shows the I-V data for the second ESD clamp alone, this is equivalent to a plot of Vsub. Figure 8 shows the NPN Vt1, obtained from TCAD simulation, and the voltage drop across the ESD network, obtained from the summed I-V, both plotted as a function of the substrate bias. The voltage drop across the ESD network is, of course, VCE of any parasitic NPN that is connected in parallel. As long as VCE is less than the NPN Vt1, the NPN will not enter breakdown. The breakdown point is reached when the curves cross each other. The current at this point is denoted as the failure current, Ifail. Ifail is obtained by locating the point VCE = Vt1 in Figure 8 and then finding the current at this VCE in the dataplot of Figure 7. Figure 9 summarizes the complete flow of this method for predicting the failure point of any ESD network which contains a parasitic BJT.

VSub

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Figure 5. ESD network showing bias condition of parasitic NPN. Vsub (potential at the substrate taps, i.e., P+ guard rings) and Vbase are at different potentials. In the TCAD simulations, Vsub is set externally; thus, it is important to include substrate taps into the TCAD simulions since Rsub will affect the results.

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Figure 6. TCAD simulated I-V characteristics of a parasitic NPN. Substrate bias values in legend.

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Figure 7. Pulsed I-V data of ESD clamps summed together and the second

ESD clamp by itself. The voltage across ESD2 is equal to the substrate bias when the full test structure is measured from pad 1 to pad 3.

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Figure 8. Simulated NPN Vt1 from Figure 6 is plotted along with the

expected collector voltage from Figure 7, all with respect to the substrate bias. Estimated failure point circled.

Identify Parasitic Structure

Begin

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Identify ESD Path

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Identify ESD Path

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Figure 9. Methodology to calculate failure from TCAD simulation along

with the pulsed I-V data for the ESD network.

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Figure 10. Failure voltage measured using TLP with that obtained from

TCAD simulations using the described methodology. Values normalized to failure level of TLP measurements. Test 1 is the same structure as the circled case in Table II.

B. Results and Discussion The above described procedure was applied to several

different test structures and the results are shown in Figure 10. The test structures included two different ESD clamps, two different types of N-regions, and several different spacings. The estimated failure points derived from the TCAD simulations agree well with the failure currents and voltages measured using TLP. This confirms that TCAD simulation data may be combined with ESD clamp data to estimate failure levels when any arbitrary NPN is located between the anode and cathode of the ESD network.

Without loss of generality, the methodology can be applied using ESD clamp I-V curves obtained directly from simulation, making this approach applicable for pre-silicon evaluation. A few stand-alone NPN test structures would be needed to calibrate the process deck. When doing any of the TCAD simulations proposed here, it is important to use an accurate cross-section in a well calibrated process.

Accurate simulation of the breakdown voltage is not only dependent on how well the process has been simulated but also on the grid used for TCAD electrical simulations. It was found that truncating the cross-section to a too shallow depth below the silicon surface can alter the results. In practice, one can run multiple TCAD simulations, increasing the vertical extent of the simulation grid each time, until the parasitic NPN behavior no longer changes; at this point, a sufficiently large device cross-section is being simulated. In this study, it was found that extending the simulation grid to a depth over 2x that of the deepest diffusion was required.

To construct Figure 8, only a few Vt1 values were simulated, but intermediate values can be interpolated with a good degree of accuracy using the solid curve shown. The solid curve has the form y=AxB. However, note that the solid curve is not extended down to zero substrate bias. At zero bias, the NPN breakdown mechanism changes to reverse PN junction breakdown. It is important to do several TCAD simulations for low substrate bias values, since extrapolated data from simulations obtained at only higher substrate voltages can introduce too much error.

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IV. ANALYSIS TCAD simulations may be used to provide additional

insight into the relation between N-region type and breakdown voltage. Figures 11 and 12 depict TCAD results for the parasitic structures defined in Figure 3A and 3B, respectively; they show impact ionization rates near the collector of each parasitic NPN. Figure 11 shows that for the NPN of Figure 3A, the most impact ionization occurs inside the HV-NW. The addition of the N-SINKER and NBL layers (Figure 12) shifts the location of maximum impact ionization to the PN junction. Figure 12 shows increased impact ionization along the entire junction although the highest concentration is at the NBL to substrate interface. This is seen more clearly on a structure with just HV-NW and NBL, Figure 13. Information about impact ionization and current density, obtained from TCAD simulations, provides guidance as to how to inhibit breakdown of the parasitic NPN. For example, if breakdown occurs near the surface, adding an implant or some type of shallow isolation, if available, may help to increase the breakdown voltage of the parasitic NPN. If the breakdown occurs deeper in the substrate, as seen in the cases presented here, the solution may be to change the P-region profile below the surface. For this process, a PBL diffusion was available that was at the desired depth.

Indeed, additional TCAD simulations confirm that breakdown of the parasitic NPN may be inhibited by adding a P+ buried layer (PBL) in between the two N-regions, but not extending all the way to the N-regions. The PBL is helpful because it is located in the substrate at the depth where the parasitic bipolar has its highest current density. The PBL degrades the bipolar’s current gain and increases the breakdown voltage. Figure 14 shows the simulated current density in devices with and without PBL at similar collector voltage levels (but different collector current levels). Figure 15 compares the simulated I-V curves for these two devices, and Table III provides TLP measurement results which confirm the simulation results. For comparison, the second row in Table III is the same structure as the circled case in Table II. In all cases, the addition of the PBL increases the Ifailvalue.

Figure 11. Simulated impact ionization rate near the collector of the structure

in Figure 3A. Plot on the left is for a bias point where IC<It1 and the plot on the right is is for IC>It1. The highest level of impact ionization is inside the HV-NW near the actual contact where there is a shallow region of higher doping.

Figure 12. Simulated impact ionization rate near the collector of the structure

in Figure 3B. Plot on the left is at a point where IC<It1 and the plot on the right is at a point where IC>It1. The highest level of impact ionization is at the NBL/substrate interface near the bottom left of the N-region.

Figure 13. Simulated impact ionization rate near the collector of a structure with HV-NW and NBL. Plot on the left is at a point where IC<It1 and the plot on the right is at a point where IC>It1. The highest level of impact ionization is at the NBL/substrate interface near the bottom left of the N-region.

Figure 14. Total current density of a HV-NW based parasitic NPN. Cross section on the left is with PBL and cross section on the right is without PBL.

The PBL interrupts the normal current path and changes the bipolar’s behavior.

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Figure 15. TCAD simulation showing benefit of adding PBL in between collector and emitter of the parasitic NPN. Solid curves are without PBL. Dotted curves are with PBL. Collector and emitter are HV-NW diffusions.

TABLE III. TLP DATA FOR TWO DIFFERENT ESD NETWORKS AND TWO DIFFERENT VALUES OF THE PARASITIC NPN BASE WIDTH (I.E., N-REGION SPACING). Δ IFAIL IS THE DIFFERENCE BETWEEN THE NO PBL CASE AND THE PBL CASE. THE ADDITION OF A PBL BETWEEN THE N-REGIONS INCREASES IMPEDES BIPOLAR BREAKDOWN AND IMPROVES THE FAILURE CURRENT.

No PBL PBL

ESD Network

Spacing (Normalized) Ifail (A) Ifail (A) ΔIfail (A)

A 0.63 (No PBL)0.66 (PBL) 0.177 0.957 + 0.78

A 1 0.198 2.608 + 2.41

B 0.63 (No PBL)0.66 (PBL) 1.959 3.243 + 1.28

B 1 3.074 5.701 + 2.63

V. CONCLUSIONS Parasitic NPN transistors can cause ESD failures. A time-

efficient 2D TCAD-based methodology for accurately determining the interaction between any two N-type diffusions and the ESD cells connected to them has been demonstrated. The methodology is shown to drastically reduce the number of test structures needed to create N-diffusions spacing rules, even prior to silicon fabrication.

TCAD simulations have also been utilized to analyze the behavior of the parasitic bipolar. By identifying the breakdown location and the region of highest base current density, design changes can be made to inhibit the NPN breakdown. A successful demonstration of this process was shown; the TCAD-informed addition of a PBL layer raised the failure current of a particular test structure.

REFERENCES [1] D. Trémouilles et al., “Latch-Up Ring Design Guidelines to Improve

Electrostatic Discharge (ESD) Protection Scheme Efficiency,” IEEE Journal of Solid-State Circuits, vol. 39, no. 10, pp. 1778-1782, 2004.

[2] A. Amerasekera, C. Duvvury, "ESD in Silicon Integrated Circuits", John Wiley and Sons, 1995.

[3] U. Glaser et al., “Base pushout driven snapback in parasitic bipolar devices between different power domains,” IEEE International Reliability Physics Symposium, pp. 387-392, 2004.

[4] L. Cerati et al., "Novel Technique to Reduce Latch-up Risk due to ESD protection devices in smart power technologies," EOS/ESD Symposium, pp. 32-38, 2006.

[5] K. Esmark (private communication), 2007.

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