Understanding Transient Latchup Hazards and the Impact of Guard Rings

Farzan Farbiz and Elyse Rosenbaum Department of Electrical and Computer Engineering,

University of Illinois at Urbana-Champaign Urbana, Illinois, USA ffarbiz2@illinois.edu

Abstract—An experimental study of transient latchup is conducted. Measurements are performed on test structures fabricated in 90-nm and 130-nm CMOS technologies. The worst case testing conditions differ for static and transient latchup. Device simulation is used to understand the measurement results. P-well and N-well guard rings are evaluated under transient test conditions.

Keywords—Latchup; Guard rings

I. INTRODUCTION Latchup refers to the undesired triggering of a parasitic

PNPN, located between the power supply and the ground rail of an integrated circuit. Figure 1 illustrates how a parasitic PNPN is formed in a bulk-Si CMOS inverter. Under normal circuit operating conditions, this PNPN should be in its high impedance state. If it is triggered into the low impedance mode, the resulting localized current conduction may result in circuit malfunction or even permanent damage to the part. Latchup may be triggered by a voltage perturbation at one of the terminals of the parasitic PNPN (referred to as internal latchup), or it may be triggered by a perturbation applied elsewhere in the circuit, i.e., outside the PNPN (referred to as external latchup). After the perturbation, or trigger source, is removed, the PNPN will remain in the low impedance state if its holding voltage is lower than the supply voltage [1]. Therefore, latchup is a serious reliability concern as long any of circuit blocks within an IC have a supply voltage that is greater than the holding voltage of a parasitic PNPN, roughly 1.2V [2].

The JEDEC latchup test standard, JESD78B, describes several (static) tests that may trigger latchup [3]. Among them, the I-tests are relevant to external latchup, which is the focus of this work. In the negative [positive] I-test, negative [positive] current is injected at a signal pin; the injected current is the trigger source. The chip is powered up during testing, and the current drawn from each of its power supplies is recorded both before and after the application of the trigger source. If the current drawn from any of the power supplies has increased appreciably after the trigger source is removed, latchup has occurred. The smallest valued injection current that causes latchup is called the latchup trigger current and is denoted Itrig.

The current source used for standardized I-tests [3] has a slow rise-time (5µs-5ms) and a long pulse-width (10µs-1s), which is why this is classified as static testing. Under

Substrate

NW2

VDD

N+ P+P+ N+ N+ P+

VSS

PW2

In

Out

Qp Qn

RPW,2

RNW,2

real-world use conditions, latchup may be caused by powered-on ESD events such as cable discharge events (CDE) [4] —such events are characterized by their short duration (hundreds of nanoseconds) and fast rise-time (a few nanoseconds). A variety of non-standardized procedures have been proposed for TLU testing. One such test is described in a recommended practice document published by the ESD Association [5]; in this test, the stimulus—a negative voltage pulse—is applied directly to the supply terminal of the PNPN device, placing it in the category of internal latchup testing. More relevant to this work is the transient I-test [6][7], in which the trigger source is a current pulse with short pulse duration and fast rise-time. The details of the experimental setup for the transient I-test are given in Section II.

In the following sections of the paper, Itrig values obtained from positive and negative transient I-tests are compared. The efficacy of guard rings under transient testing conditions is evaluated. Henceforth, Itrig measured during a negative I-test will be referred to as negative Itrig, and Itrig measured during a positive I-test will be referred to as positive Itrig. Furthermore, only the magnitude of Itrig is reported, i.e., both negative Itrig and positive Itrig are reported as positive numbers.

Figure 1. Device cross section of a CMOS inverter. The parasitic bipolar transistors form a PNPN that could be triggered on and cause latchup.

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II. EXPERIMENTAL SETUP AND THE TEST STRUCTURES Figure 2 illustrates the experimental set-up used to study

TLU in this work. A high power pulse generator, with output impedance of 50Ω, is connected to the signal pad of the test structure, labeled I/O, via a rise-time filter (RTF) and a 50Ω resistive matching network. RTF sets the rise-time of the pulse, tr, to the desired value, which is 7 ns, unless otherwise noted. The pulse-width, TPW, is variable. The use of the matching network results in cleaner pulse waveforms by eliminating reflections [8]. The current injected into the signal pin, Iinj, is calculated by measuring the voltage drop across RS of the matching network (refer to Fig. 2). IDD denotes the current provided by the power supply connected to the PNPN, or victim. Latchup is said to have been triggered if IDD exceeds 2mA after the trigger source has been removed. Before the trigger source is applied, IDD < 0.1 mA.

In a well designed IC, the latchup trigger current is high, 100s of mA. Such high levels of current injection can be provided by forward-biased PN junctions, and the test structures for the positive and negative I-tests reflect this. (Note that in a typical CMOS IC, many PN junctions will be found at the signal pads.) Figure 3 contains cross-sectional representations of the test structures used in this work. The test structures were fabricated in 90 and 130-nm CMOS technologies. In Fig. 3, victim orientation refers to the relative placement of PW2 and NW2, with respect to the substrate current injector.

In advanced CMOS technologies, different power supply voltages are used with I/O and core transistors. The supply voltage is 2.5V for the I/O and 1V for the core in the 90-nm technology used in this work; these numbers are 3.3V and 1.2V for the 130-nm technology. Parasitic PNPN are found in both I/O and core logic circuits, meaning that the victims of Fig. 3 could have VDD of 1V, 1.2V, 2.5V or 3.3V. Itrig is only a weakly decreasing function of VDD for VDD ≥ 1.5V [9]; note

Substrate

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+ -

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that latchup cannot be sustained after the removal of the trigger source if VDD ≤ 1.2V. Therefore, VDD was set to 1.5V in all the experiments. VDDIO was also set to 1.5V, arbitrarily, because Itrig is insensitive to VDDIO.

It is important to note that during a negative [positive] I-test, the PN junction injects minority [majority] carriers into

Figure 3. Test structure cross-sections. Each consists of a substrate current injector and a PNPN (victim). The injectors have 4 fingers (only one is shown). Key layout spacings are highlighted in the figures; dTAP=40 µm and dvictim=5 µm, unless otherwise noted. dvictim is measured from the victim to the right-most finger of the injector. Structures (a) and (b) are used for negative I-tests; (c) and (d) are used for positive I-tests. The victims in (a) and (c) are 0o oriented, which means that the P-well of the victim (PW2) is closer to the injector than is its N-well (NW2). (b) and (d) show 180o oriented victims, in which the relative positions of PW2 and NW2 are swapped. N-well guard rings (NGR) and P-well guard rings (PGR) are 1 µm wide.

(d)

(c)

(b)

(a)

Figure 2. Experimental set-up. The rise-time filter adjusts the rise-time of the pulse injected into the device under test. Iinj is calculated from the measured voltage drop across the matching network. IDD is the current through the dc power supply.

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the substrate. It is normal practice to surround a minority carrier injector with an N-well guard ring (NGR), to prevent the electrons from reaching the victims. Similarly, majority carrier injectors are surrounded by P-type guard rings (PGR)—comprised of a P+ diffusion inside a P-well. The guard ring efficacy may be assessed by measuring Itrig both with and without the guard ring activated. An inactive GR is left floating; in this work, an active NGR is connected to VDD, and an active PGR is connected to VSS.

III. RESULTS AND DISCUSSIONS

A. Pulse-width dependence The pulse-width dependence of Itrig is investigated by

changing TPW of the trigger source. The measurement results are shown in Figs. 4 and 5. The results shown in Fig. 4 confirm previous observations [6][7]: negative Itrig is a decreasing function of TPW. These data also show that for a fixed substrate current injector to victim spacing (dvictim), negative Itrig is virtually identical for 90 and 130-nm CMOS technologies. The data of Fig. 5 reveal that positive Itrig is also a function of pulse-width; a comparison of Figs. 4 and 5 indicates that Itrig becomes independent of TPW on a significantly shorter timescale under positive test conditions than under negative test conditions. The different time dependencies observed under positive and negative test conditions suggest that these time dependencies are not intrinsic to the victim. This hypothesis is confirmed by applying a pulsed overvoltage to the VDD terminal of the victim so as to trigger internal latchup. The measurement results of Fig. 6 show that the latchup trigger voltage is independent of TPW on a time scale ranging from less than 100ns up to 100µs.

The pulse-width dependence of negative Itrig is attributed to the non-quasi-static behavior of the parasitic NPN transistor Q1, formed by the N+ region of the injector, the P-substrate, and NW2 (refer to Fig. 3). This is confirmed by an experiment. The potential at the emitter of Q1 is pulled below zero, resulting in emitter current. The steady-state value of IE is just a little bit less than the value of Itrig obtained from the static I-test. The

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measured rise time for IE is 7ns. The collector current IC,Q1(t) is monitored. As shown in Fig. 7, IC,Q1 approaches steady-state far more slowly than does IE. Latchup is triggered when IC,Q1 is large enough to forward bias the base-emitter junction of the victim, i.e., when

, 1crit

C Q NWI I= . (1)

In (1), critNWI is the minimum amount of current that has to be

collected by NW2 to trigger latchup. Based on Figure 7, if the current injected at the IO pad is just slightly higher than the static Itrig, it will take about 10µs for IC,Q1 to reach crit

NWI . Therefore, Itrig should be a decreasing function of TPW for TPW ≤ 10µs, consistent with the data of Fig. 4.

IC,Q1 increases slowly as a result of the large transit time for minority carriers in the substrate. The transit time is affected by recombination in the base region of Q1. One may show this

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Figure 6. Vtrig for internal latchup vs. TPW. The victim is shown in Fig. 2. The terminals of the substrate injector are left floating. A trigger source with pulse-width of TPW and rise-time of 7ns is placed in series with the dc supply, VDD. 130-nm CMOS technology.

Figure 5. Itrig from positive I-test. Guard rings are inactive. 0° oriented victim. 130-nm CMOS technology.

Figure 4. Negative I-test. 0° oriented victims. Itrig is a decreasing function of TPW. 90-nm and 130-nm CMOS technologies. NGR are inactive.

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mathematically by solving the diffusion equation in the base region of Q1 to obtain an analytical expression for IC,Q1(t). A closed form solution cannot be obtained if one attempts to model the non-uniform, three-dimensional geometry of Q1. Here, we formulate and solve the diffusion equation for a simplified NPN transistor that has uniform geometry in two dimensions. This transistor is shown in Fig. 8. The base length in the x-direction is dbase. Under low-level injection conditions, the diffusion equation in the base is written as

2

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nn

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= −∂ ∂

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In (2), Dn is the diffusion constant for electrons in the substrate and Jn and τn are the current density and the carrier lifetime, respectively, of electrons in the substrate (base of Q1). Partial differential equation (2) is solved by the Laplace transform method. Taking the Laplace transform of (2) and solving for Np(s,x), one gets

1 1

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∂

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. (4)

One may set C2 to zero, as long as the solution will not be used to find the current in devices with base n nd D τ<< , the diffusion length for electrons in the substrate. C1 is found by considering the boundary condition at the base edge x=0,

( ,0) ( )n EJ t J u t= ⋅ , (5)

where u(t) is the unit step function and JE is the emitter current density. A unit step function is used in (5) because the source driving the emitter has a very fast rise-time, justifying the step function approximation which greatly simplifies the algebra. Eq. (5) can be rewritten in the Laplace domain,

( ,0) En

JJ ss

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(6) is substituted in (4), yielding

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The final expression for Jn(s) thus becomes

1

( , )n

n

sx

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JJ s x e

s

τ+

−

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The collector current density, JC(t), is calculated by setting x=dbase in (8) and then taking the inverse Laplace transform;

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n n

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n baseC E

n

D d e eJ t J dttD

τ

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Finally, one may write an expression for the common base current gain, α.

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n n

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From (1), latchup is triggered when the current collected by NW2 of the victim is equal to crit

NWI . This N-well region is analogous to the collector region of the transistor in Fig. 8. Itrig is related to crit

NWI by the NW collection efficiency, αNW. Reasonably assuming that αNW has the same functional form as does α derived above, one obtains the following expression for the pulsewidth-dependent Itrig.

Figure 8. A 1-d NPN is used to simplify the derivation of the diffusion equation.

Figure 7. Collector and emitter current of Q1 during a negative I-test for a 0° oriented victim. 130-nm CMOS technology.

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2

4

1.50

base

PW n n

critNW

trig dtT D t

II

e eC dtt

τ− −

=

⋅∫

. (11)

In (11), the constant C is a function of the emitter and collector areas, and other material and geometric constants. Eq. (11) is plotted in Fig. 9; the model predicts that Itrig should be a decreasing function of TPW for TPW ≤ 10µs, consistent with the measurement data. Generally, in a technology with a moderate or high resistivity substrate, τn will be large and negative Itrig will be a strong function of TPW.

The pulse-width dependence of positive Itrig (see Fig. 5) may be understood by considering current conduction through Q2 (refer to Fig. 3(c)). Figure 10 shows that IC,Q2 saturates after 200ns, which is consistent with the behavior of Itrig in Fig. 5. IC,Q2 reaches steady-state much faster than does IC,Q1 because Q2 has a shorter base width than Q1 Therefore, the pulse-width dependence of negative Itrig is more pronounced than that of positive Itrig.

B. Effect of trigger source rise-time During transient test conditions, displacement current will

augment the carrier injection into the substrate. Recall that the PN junction current injectors have an associated capacitance. Displacement current is a majority carrier current. Referring to Fig. 3(c) or (d), let Idisp denote the amount of displacement current injected into the I/O when the pad voltage is raised from VDDIO to Vinj with a rise-time of tedge; for the test structure of Fig. 3(a) or (b), let Idisp denote the amount of displacement current injected into the I/O when the pad voltage is lowered from 0 to –Vinj with a fall-time of tedge. Because Idisp is a decreasing function of tedge, fewer carriers are injected into the device as tedge increases. Therefore, one might expect Itrig to be an increasing function of tedge. However, both positive and negative Itrig are insensitive to dV/dt, as indicated by the data in Figs. 11 and 12. These results are explained below.

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During a negative I-test, latchup is triggered by electrons,

whereas the displacement current in the substrate is a hole current. In fact, during a negative I-test, substrate hole current has the wrong polarity to trigger latchup [10]. Thus, negative Itrig is insensitive to tedge, as was shown in Fig. 11.

Figure 13 shows parasitic PNP Q2, which controls substrate current injection during a positive I-test. The substrate current is equal to the collector current of Q2, IC,Q2. The displacement current component of IC,Q2 is denoted as IC,Q2,disp. RNW is small (< 3Ω) because the substrate current injector was, in fact, an ESD protection diode, which has a small on-resistance. It

follows that ( )BC BENW edgeR C C t+ << , and therefore

( ), 2, 1edge

NW BC BE

tC Q disp R C CBC

disp BC BE

I Ce

I C C

−+ <<

+. (12)

The inequality in (12) indicates that only a small fraction of the displacement current at the I/O pin is injected into the

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Figure 11. Negative I-test. Itrig is insensitive to tedge. TPW=500ns. 0° oriented victims. 130-nm CMOS.

Figure 10. Collector current of Q2 during a positive I-test for a 0° oriented victim. 130-nm CMOS technology.

Figure 9. Itrig vs. TPW as predicted by eq. (11). Dn = 30 cm2s-1 and τn = 3µs, reasonable values for 90 and 130-nm technologies [10]. Itrig becomes constant for TPW ≥ 10µs, similar to the data of Fig. 4.

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substrate. This is why positive Itrig is insensitive to tedge.

C. Orientation of the victim In previous works, it was claimed that 0° victim orientation

(Fig. 3(a)) provides the lowest value of negative Itrig [6][7]. Figures 14 and 15 indicate that this is generally not a correct assertion. It’s true only under static test conditions in the absence of guard rings. In most cases, the 180° oriented victim (Fig. 3(b)) has the lower trigger current; this can be attributed to the smaller base width of Q1, dbase.

The device simulation results of Fig. 16 may be used to further understand the effects of orientation. The value of Itrig depends both on the fraction of current injected at the I/O pad that gets collected by NW2 of the victim (i.e., αNW) and on the direction of current flow within NW2. The current must be directed such that it lowers the N-well potential in the vicinity of the P+ diffusion, thus forward biasing the PN junction, a necessary step to trigger latchup. When NGR are used (Fig. 16(a)), current flows vertically through NW2, regardless of orientation, and the 180o oriented victim always has lower Itrig due to the smaller dbase and consequently larger αNW. Figures

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16(b) and 16(c) illustrate current flow in structures without GR. For the 180° oriented victim (Fig. 16(b)), the portion of the current that flows laterally between the injector and NW2 does not assist in lowering the N-well potential in the vicinity of the P+ diffusion (see Fig. 16(d)). For the 0° oriented victim (Fig. 16(c)), all of the current in NW2 helps to lower the potential near the P+ diffusion (see Fig. 16(e)). Thus, for the case of no NGR and long TPW, Itrig of the 0° oriented victim is lower than that of the 180° oriented victim. However, as the stress pulse-width is made small, eq. (11) indicates that the number of carriers collected by NW2 of the 0o oriented victim (long dbase) becomes a decreasing fraction of the number collected by NW2 of the 180o oriented victim (shorter dbase). Therefore, for short stress durations, the 180o oriented victim has the lowest Itrig, as shown in Fig. 14.

Figure 17 examines the effect of orientation on positive Itrig. For the positive I-test, the 180o victim orientation (Fig. 3(d)) provides the lower Itrig, regardless of TPW; only the GR active

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Figure 15. Same experiment as for Fig. 14, except that the NGR are active. The 180° oriented victim has the smallest Itrig, regardless of TPW.

Figure 14. Negative I-test with inactive NGR. Only for large TPW does the 0° oriented victim have smaller Itrig than the 180o oriented victim. 130-nm CMOS technology.

Figure 13. Parasitic PNP Q2 is the substrate current injector during a positive I-test (see Figs. 3(c)(d)). RNW is the N-well resistance. CBE and CBC are the base-emitter and the base-collector junction capacitances, respectively. Only the P+ diffusion of the victim is shown.

Figure 12. Positive I-test. Itrig is insensitive to tedge. TPW=1µs. 0° oriented victims. 130-nm CMOS.

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case is examined. In [9], it is shown that in a positive I-test

,

2 ,2

1 BE ontrig

Q PW

VI

Rα= ⋅ , (13)

where αQ2 is the common-base current gain of Q2, RPW,2 is the P-well resistance shown in Fig. 1, and VBE,on represents the on-state base-emitter voltage drop of Q2. (13) seems to suggest that positive Itrig will be independent of both spacing (dvictim) and orientation; the first of these predictions is consistent with measurement data [10]. The orientation effect seen here (cf. Fig. 17) is an artifact of the test structure design. Since the test structures contain guard rings, (13) is modified to account for their presence,

,

2 ,2

1 1 BE ontrig

Q PGR PW

VI

f Rα= ⋅ ⋅ , (14)

where fPGR is the fraction of injected carriers that is collected by the PGR. Note that Itrig is a decreasing function of RPW,2. In the test structures with a 0o oriented victim, the PGR are placed in the same well as is the victim (PW2). In these test structures, the PGR not only increase Itrig by collecting some of the excess holes from the substrate, they also increase Itrig by decreasing RPW,2.

D. Guard ring efficiency under TLU testing N-well [P-well] guard rings increase negative [positive] Itrig, thus improving latchup resilience; however, Fig. 18 shows that the relative benefit of NGR decreases for short stress durations. In the earlier dataplots, e.g. Fig. 4, it was shown that Itrig is higher for short TPW; we have previously shown that NGR efficiency drops under high-level injection conditions [11]. Taken together, these two observations explain why NGR raise Itrig by a smaller percent as TPW decreases.

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E. Triple well technology

Triple well can be used to reduce the latchup hazard due to substrate hole injection, which occurs during a positive I-test. In the 130-nm technology, placing the victim inside a deep N-well was found to increase Itrig by almost a factor of 2. However, a comparison of the data in Figs. 4 and 19 shows that placing the victim inside a deep N-well enhances its susceptibility to negative TLU; that is, for a given dvictim, Itrig is lower when the victim P-well lies within a deep N-well. A similar observation was made about static latchup [12]. Triple well raises the latchup threat because the deep N-well provides an additional collection area for electrons.

F. Negative I-test vs. Positive I-test Previously, it had been reported that the negative I-test

provides the lowest Itrig, that is, it’s the worst case test condition [12]. However, the data of Figs. 20 and 21 show that this is too

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Figure 18. ΔItrig/Itrig(GR inactive) where ΔItrig≡ Itrig(GR active) - Itrig(GR inactive). 0° oriented victims. Circular data markers are for a negative I-test; square ones are for a positive I-test. 130-nm CMOS technology.

Figure 17. Positive I-test with active PGR. The 180° oriented victim has the lower Itrig. 130-nm CMOS technology.

Figure 16. Simulated current flow during a negative I-test for (a) 180° oriented victim with active NGR, (b) 180° oriented victim without NGR, and (c) 0° oriented victim without NGR. Figs. (d) and (e) show potential contours for cases (b) and (c), respectively. Iinj= 3 mA/µm in all of the simulations.

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general a claim. These figures compare the values of Itrig obtained from positive and negative I-tests, both when the GR are inactive (Fig. 20) and when they are active (Fig. 21). If TPW is large, as is the case for static latchup testing, the negative I-test does yield the smallest Itrig. However, for stress durations less than about 500ns, the positive I-test yields a lower value of Itrig.

IV. CONCLUSIONS Negative current injection is worst case during static

latchup testing [7], which is generally used for product qualification. However, real world stresses, such as cable discharges, are transient, in which case positive current injection is worst case.

A 0o oriented victim is most susceptible to latchup only during static testing and if guard rings are not used. Otherwise, a 180o oriented victim will have a lower latchup trigger current. For the case of a negative I-test, this is because of the proximity of victim N-well to the substrate current injector (larger αNW); for the case of a positive I-test, it is due to the

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direction of current flow within the victim P-well.

N-type guard rings become less efficient in preventing TLU as the pulse-width of the injected current decreases. Thus, they must be evaluated under short transient pulses relevant to TLU.

ACKNOWLEDGMENT The authors gratefully acknowledge UMC for fabricating

the test structures through the UMC University Program. This work was supported by Semiconductor Research Corporation.

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Kluwer Academic Publishers, NY, 1986. [2] W. Moms, “Latchup in CMOS,” Proceedings of International Reliability

Physics Symposium, pp. 76-84, 2003. [3] “IC Latch-Up Test, JESD78B Standard”, http://www.jedec.org, pp. 1-19,

2008. [4] Telecommunications Industry Association (TIA), Category 6 Cabling:

Static Discharge Between LAN Cabling and Data Terminal Equipment, Category 6 Consortium, Dec. 2002.

[5] “Transient Latch-up testing- Component Level Supply Transient Stimulation”, ANSI/ESD SP5.4-2004, ESD Association, 2004.

[6] K. Domanski et al., “Development strategy for TLU-robust products,” Proceedings of ESD/EOS Symposium, pp. 299-307, 2004.

[7] D. Kontos et al., “External latchup characterization under static and transient conditions in advanced bulk CMOS technologies,” Proceedings of International Reliability Physics Symposium, pp. 358-363, 2007.

[8] S. Joshi and E. Rosenbaum, "Transmission line pulsed waveform shaping with microwave filters," Proc. EOS/ESD Symp., pp. 364-371, 2003.

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Figure 19. Negative I-test on 0° oriented victims built using triple well. NGR are inactive. 130-nm CMOS technology.

Figure 21. Same experiment as for Fig. 20, except the guard rings are active.

Figure 20. Itrig from positive and negative I-tests. Guard rings are inactive. 0° oriented victims. 130-nm CMOS technology.

IRPS10-473 4D.2.8