A Generalized, IB-independent, Physical HCI Lifetime Projection Methodology based on Universality of

Hot-Carrier Degradation Dhanoop Varghese, Muhammad Ashraful Alam

School of Electrical and Computer Engineering Purdue University

West Lafayette, IN, 47907, USA 1-765-494-5988, alam@purdue.edu

Bonnie Weir LSI

Allentown, PA, 18109, USA

Abstract—We develop a novel approach for hot carrier lifetime prediction based on the ‘universality of HCI degradation’ that not only generalizes the classical theory by obviating the measurement of IB, but also allows prediction of HCI lifetime over a broad range of technology nodes, bias conditions, and device geometries. We explain the shape of the degradation vs. time characteristic based on the energy distribution of the Si-O bonds, and we show, based on the bond-dispersion model, that the degradation shows similar features for both ON- and OFF-state bias conditions.

Keywords- on-state hot-carrier; off-state hot-carrier; universal degradation; bond-dispersion model; voltage acceleration model;

I. INTRODUCTION Despite significant scaling in voltage even at the 40nm

technology node, hot carrier injection (HCI) remains an important reliability issue for CMOS transistors [1, 2]. The degradation is believed to be due to energetic carriers that get injected into the gate dielectric and create damage by breaking bonds (Si-H, Si-O etc.) within the dielectric. Classical hot carrier theories (a) assume a constant power law exponent n for degradation (∆=Atn) and (b) use the change in impact ionization current measured at the bulk terminal (IB) as a measure of voltage acceleration from stress to operating conditions (see Fig. 1). Both of these observations do not apply to modern MOSFETs: HCI degradation shows a saturating behavior with the time exponents gradually reducing at longer stress time and at higher degradation levels. Also the traditional voltage acceleration model [1] (and an even more recent variant of it [3,4]) based on the bulk current (IB) is no longer a viable predictor of HCI lifetime of ultra-scaled devices because IB for transistors with thin oxides is irretrievably contaminated by gate leakage (IG). The alternate empirical model uses linear temporal extrapolation of degradation data and an eB/VD voltage acceleration model, which are not physically justified. In addition, as worst-case HCI lifetimes become shorter with

transistor scaling, and designers increasingly rely on reliability modeling for lifetime projection, one must correctly estimate the HCI lifetimes at all VG and VD combinations (not only at VG=VD or VG=VD/2). For example, HCI lifetime at VG>VD bias conditions deviates from the empirical eB/VD model (see Fig. 7b) and is several orders of magnitude lower compared to that predicted by classical/empirical hot carrier models [4].

In this paper we demonstrate that the HCI in logic transistors exhibits a universal time-dependent (temporal)

TSMC, AMAT, NCN

Figure 1. Lifetime extrapolation based on classical ON-state hot carrier theories assumes constant power law time exponent (dashed line) while we show that the degradation has saturating characteristics at longer stress time (dotted line). The bulk current for ultra-scaled 40nm technology node transistor is dominated by gate leakage and therefore cannot be used to compute HCI voltage acceleration factors. The alternate empirical model lacks explicit physical justification and HCI lifetime at VG>VD bias conditions is shown to deviate from eB/VD model (see Fig. 7b) [4]. In this paper we demonstrate that hot carrier degradation (both at ON- and OFF-state) exhibit universal behavior, which can be used to perform fast and accurate lifetime extrapolation for a range of technology nodes, device geometries and bias conditions.

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degradation. The saturating nature of the universal curve is explained based on a bond-dispersion model [5]. Even though, temporal universality of ON state HCI, i.e. NIT ~ f(t/t0(VG, VD, T)), has been previously suggested in literature [6-8], its application to a wide range of devices and bias conditions and implications for lifetime projection have not been explored. A judicious use of this universality enables fast and efficient (IB-independent) methodology of lifetime extrapolation that provides more accurate results than simple linear extrapolations of short-term data.

II. UNIVERSALITY OF DEGRADATION Fig. 2 shows the HCI-induced parameter degradation for

transistors from 40nm technology node. The high gate leakage current in these transistors prevents direct monitoring of interface damage through charge pumping (CP) or DCIV [9] techniques. The lack of recovery on removal of the stress (data not shown) [10], however, indicates dominant contribution to interface degradation arises primarily from permanent interface traps. The theory of NIT-generation [5] suggests (see Fig. 5) that the individual curves can be scaled laterally by factors S (or shifted in log scale) to overlap in time. The resulting curve is universal over > 6 orders of magnitude in time. A single long

term measurement at a given stress bias (Fig. 2, rightmost panel) verifies the hypothesis that various stress biases trace different parts of a single time-dependent universal curve.

Fig. 3a shows the HCI-induced interface damage measured by CP during ON-state stress (VG=2V, VD ≥3V) of 130nm logic transistors. Fig. 3b shows that the universality of interface damage remains unaffected as the bias condition is changed from ON (VG=2V) to OFF (VG=0V) in spite of the reduction in drain current over four orders of magnitude.

Fig. 4a summarizes the universal curves from hot carrier measurements carried out on a wide range of device geometries (drain extended NMOS, long and short channel core logic NMOS) and bias conditions (VG=0V, 1V, and 2V). The universal curves are formed by scaling multiple short-term degradation data as shown in Fig. 3. Since the universal curves are for various device geometries and bias conditions, they differ in their relative magnitudes and degradation rates. However, all the universal curves shown in Fig. 4a have very similar shape as given by the equation:

ΔICP=Aξ(St), (1)

where ξ is the universal function, and the pre-factor A and scaling factor S are determined by the device geometry and

Figure 2. Degradation in (a) linear drain current, (b) saturation drain current and (c) threshold voltage at (LHS) VG=VD, T=125oC and (RHS) VG=1V, T=25oC ON-state hot carrier stress for ultra-scaled logic transistors. Solid black line (rightmost panel) represents data from single long term (300ks) measurement.

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LC=50nm LC=40nm

LC=50nm

VD VD

Time (s) Time (s)

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Figure 3. NIT time evolution measured through charge pumping at (a) ON-state and (b) OFF-state hot carrier stress conditions for 130nm technology logic transistors. The solid black line represents data from single long term (300ks) measurement.

Figure 4. (a) Universal degradation curves for various stress biases (ON/OFF) and device structures (solid: Drain extended NMOS for I/O applications [7], dashed: Logic 0.7µm, dotted: Logic 0.16 µm) formed through the scaling of degradation data (see Fig. 3). (b) Various degradation curves show very similar time evolution over several orders of magnitude in time.

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T=27OC T=27OC (a) (b)

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applied bias. To prove this, the universal curves are scaled along x-axis and y-axis directions (see Fig. 4b), and the resultant curve overlaps over six orders of magnitude in time. The similar shape for all universal curves indicates the robustness of the underlying hot carrier degradation mechanism.

III. THEORY OF UNIVERSAL DEGRADATION Let us now consider the shape of the universal curve via the

framework of Si-O bond-dispersion (B-D) model [5]. The Si-O bond precursors have a finite energy distribution in a disordered medium like SiO2 (see Fig. 5a) [5]. The precursors at various energies break at different rates, which are then added together to obtain the net interface damage (see Fig. 5b). Bond-dispersion simulation with an energy spread specified by σ=0.22eV is found to explain the measurement data over several orders of magnitude in time. The reaction rate constant being dependent on hot hole density (p), a change in VG and VD combination changes the hot hole injection, thereby changing the degradation rate and shifting the curves laterally. Indeed, this universality of damage is model-agnostic and could be also arrived at within the R-D formulation of Si-H bond-dissociation [11].

To understand why the extremes of ON- and OFF-state degradation showed identical universal features, we obtained electric field and hot carrier profiles from device- and Monte Carlo simulations (see Fig. 6). The magnitude of the electric field and hot carriers are different at various VG, but their spatial profile close to interface almost remained the same. The B-D model therefore predicts similar universal degradation at both ON- and OFF-state bias conditions. The difference in absolute hot hole densities at these bias conditions, however, results in different degradation rates for the universal curves (rate constant k0 ~ hot hole density p) as shown in Fig. 4a.

IV. VOLTAGE ACCELERATION MODEL The scaling factors used to construct the universal curves

are proportional to the degradation rate at each bias, and hence can be used to obtain the voltage acceleration of device lifetime (TF ~ 1/S) (see Fig. 7). Unlike the actual lifetime, the scaling factors can be obtained using short term measurements. Moreover, the method no longer relies on the problematic measure of IB for HCI lifetime projection. As shown in Fig. 7a, the linear extrapolations lead to inaccurate values at low stress voltages which in turn lead to inaccurate projections at operating conditions (Fig. 7b). The universality of hot carrier degradation, therefore, proves to be a more accurate alternative for lifetime extrapolation based on short term stress data, especially in the regimes of interest for reliability modeling. Moreover, by adopting this model-agnostic methodology, we no longer rely on the model of IG-IB relationship and obviate the debate as to whether hot hole or hot electron injection is responsible for HCI degradation, to make accurate HCI-lifetime projection possible.

Figure 5. (a) Energy distribution of Si-O bond precursors. EAV denotes the average and σ denotes the standard deviation of Si-O bond energies. The bonds with lower energies break first and are followed by bonds with progressively higher energies. (b) Total damage is obtained by summing up (red solid line) contributions from precursors at each energy grid point (dashed lines). The B-D model explains the CP universal curve over several orders of magnitude in time (symbols: measurement, Lines: simulation).

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Gate Edge L/4

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VG=2V VD=4.6V Y

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L/4 Gate Edge

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VG=0V VD=4.6V

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Figure 6. (a) Electric field profile close to the Si/SiO2 interface for long channel transistors at ON- and OFF-state bias conditions obtained from device simulations. The electric field profiles are found to be similar at all bias conditions and peak close to the gate edge. The resultant 2D hot hole profile (E>4.7eV) obtained from Monte Carlo simulations at (b) ON-state and (c) OFF-state biases are also similar, resulting in similar universal degradation. Though the spatial profiles are similar, the absolute hot hole densities are different at both bias conditions, resulting in different degradation rates for the universal curves.

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V. CONCLUSIONS Theory, modeling and measurements over a wide range of technology nodes and operating conditions are used to demonstrate universality of HCI degradation and to develop a new lifetime prediction methodology that is independent of substrate and gate current measurements or any specific physical models of HCI degradation. We also find that this generalized model anticipates other popular classical models as special cases.

ACKNOWLEDGEMENT We gratefully acknowledge Texas Instruments for

supporting the research, Network of Computational Nanotechnology at Purdue for the computational facilities and Birck Nanotechnology Center at Purdue for the experimental facilities.

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[3] S. E. Rauch, F. J. Guarin, and G. LaRosa, “Impact of E-E scattering on the hot-carrier degradation of deepsubmicron NMOSFETs”, IEEE Electron Device Letters, vol. 19, pp. 463−465, December, 1998.

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[5] K. Hess, A. Haggag, W. McMahon, B. Fischer, K. Cheng, J. Lee and J. Lyding, “Simulation of Si-SiO2 defect generation in CMOS chips: from atomistic structure to chip failure rates”, in Proc. Int. Electron Devices Meeting, pp. 93−96, December, 2000.

[6] J.-S. Goo, Y.-G. Kim, H. L’Yee, H.-Y. Kwon, and H. Shin, “An analytical model for hot-carrier-induced degradation of deep-submicron n-channel LDD MOSFETs”, Solid-State Electronics, vol. 38, pp. 1191−1196, June, 1995.

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Figure 7. (a) Lifetime estimation using long-term extrapolation (dashed line) and that using scaling factors and universal degradation curve (solid line) for 40nm devices. By knowing the shape of the universal curve (obtained by scaling multiple short-term degradation data) and the respective scaling factors, long-term degradation at each bias point and the corresponding device lifetime can be obtained accurately. (b) Voltage acceleration of normalized hot carrier lifetime thus obtained are plotted using eB/VD model, and clearly shows deviations at VG>VD bias condition. Both techniques agree well at lower lifetimes where errors due to extrapolation are smaller, but show differences as lifetime gets longer, resulting in significant differences when curves are extended to low VD values. The universality of hot carrier degradation allows quick estimation of scaling factors based on short term measurements and facilitates fast and accurate lifetime prediction for the entire range of operating bias conditions.

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