Abstract We review the recent progress on the development of two-terminal resistive devices (memristors). Devices based on solid-state electrolytes (e.g. a-Si) have been shown to possess a number of promising performance metrics such as yield, on/off ratio, switching speed, endurance and retention suitable for memory or reconfigurable circuit applications. In addition, devices with incremental resistance changes have been demonstrated and can be used to emulate synaptic functions in hardware based neuromorphic circuits. Device and SPICE modeling based on a properly chosen internal state variable have been carried out and will be useful for large-scale circuit simulations.

Index Terms RRAM, memristor, crossbar, neuromorphic circuit

I. INTRODUCTION

s the basic building block of electronics, field effect transistor (FET), approaches the 10-nanometer regime, a

number of fundamental and practical issues start to emerge due to difficulties in nanometer-resolution fabrication, electrostatic control and power management [1-3]. New devices and architectures are expected to continue the scaling trend the semiconductor industry has enjoyed in the past decades. Two-terminal resistive switches (also called memristive devices or memristors) have attracted increasing interest as a suitable alternative to complement transistors [4-10]. In such a device, an otherwise insulating film is sandwiched between a top and a bottom nanowire electrode (Fig. 1a, inset). This simple structure allowed the devices to be scaled down to < 10 nm in size without suffering from the same problems facing transistor scaling. In addition, the devices can be close-packed into the so-called crossbar form, in which two nanowire electrode arrays overlay each other at 90° angle so that a two-terminal resistive device is created at each cross-point (Fig. 1b). This configuration provides the highest possible integration density and random-access capability for nonvolatile memory and other applications [11-15].

Specifically, the conductance of a memristor or memristive device is not determined by the present control signals (e.g.

This work was supported in part by DARPA under contract HRL0011-09-C-001 and by NSF under contract ECCS-0954621.

W. L, K.-H. K., T. C., and S. G. are with the Electrical Engineering and Computer Science Department, the University of Michigan, Ann Arbor, MI 48103 USA (phone: 734-615-2306; fax: 734-763-9324; e-mail: wluee@umich.edu).

voltage or current), but rather determined by the history of those signals (e.g. time integral of voltage or current, or charge or flux) [4-6]. This type of device thus exhibits an inherent

- -V characteristics. Unlike other passive two-terminal devices such as resistors or capacitors, the hysteresis of a memristive device can be used for information storage (e.g. resistive memory RRAM, with low resistance on- -and reconfigurable signal routing (opening and closing the connections between the nanowire electrodes. Overall, the memristor-based crossbar network structure can offer the following advantages: 1) it allows ultra-high density memory storage with relatively small number of control electrodes n2

crosspoints can be accessed by n-rows and n-columns in the crossbar; 2) it offers large connectivity between devices each column or row is connected to n-rows or columns through n different devices; and 3) it facilitates reconfigurable circuits the circuit configuration can be readily changed by changing the conductance of the memristive devices at selected crosspoints.

The concept of memristive devices in fact covers a wide range of devices with inherent memory. The mechanism can be attributed to a) phase change due to Joule heating in chalcogenide-based phase-change memories [16]; b) conductive filament formation due to Joule heating observed in certain oxides [17,18]; c) conductive filament formation due to electrochemical redox processes observed in binary oxides (e.g. NiO, CuO2, TiO2) [19,20], chalcogenides, and polymers [7,21]; d) field-assisted drift/diffusion of ions in amorphous films [22,23]; and e) possible conformational changes in molecules [24,25]. However, understanding the switching mechanism for specific devices has always been a challenging topic, partly due to difficulties in direct material characterizations in these nanoscale devices [7,26]. The

Two-Terminal Resistive Switches (Memristors) for Memory and Logic Applications

Wei Lu, Member, IEEE, Kuk-Hwan Kim, Ting Chang, and Siddharth Gaba, Student Member, IEEE

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Fig. 1. (a) Memristive devices showing hysteretic resistive switching characteristics. The device can be in the on or off state depending on the programming sequence. (b) Schematic of a crossbar array.

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devices can show unipolar switching, in which the 0->1 and 1->0 transition depends only on the amplitude of the applied signals but not the polarity; or bipolar switching, in which one voltage polarity always switches the device from 0->1 and the opposite polarity always switches the device from 1->0 [7,8]. It is generally believed the operation of unipolar type devices is based on a thermal effect, while the operation of the bipolar type devices is based on a field-assisted process.

II. DEVICE FABRICATION AND OPERATION

A. Digital Memristor Devices Here we focus our discussions on bipolar-type devices,

which normally require lower switching current since thermal effects do not have to be in play. The generally accepted explanation for this type of devices is the injection and redistribution of ions inside an otherwise insulting host matrix (electrolyte) under the influence of an electric field [7,9,22,23]. Since the local resistivity depends on the ion concentration, the redistribution and storage of ions can result in nonlinear hysteretic I-V characteristics (Fig. 2) [7,9,22,23]. These devices can be further divided into two categories:

switches from low to high (or high to low) when the applied voltage crosses a threshold (Fig. 2a); and analog (or

agradual function of the applied bias (e.g. Fig. 2b) [27].

For digital type devices conducting filament formation is normally the dominating mechanism. For example, by forming Ag filaments in amorphous silicon (a-Si, which serves as the electrolyte material) we have observed robust resistance switching effects [10,23,27-29]. Fig. 2a shows the I-V characteristics of the digital memristive devices using a structure consisting of an Ag top electrode, a heavily doped polysilicon bottom electrode, and an intrinsic a-Si active layer. The device shows a number of desirable characteristics. For example, a well-defined threshold and abrupt resistance switching were observed (Fig. 2a) with on/off ratio ~ 106 at 1V read voltage. Reliable resistance switching was observed for devices with active area down to 50 nm × 50 nm, and limited only by fabrication resolution. Other performance metrics such as switching speed of < 10 ns (Fig. 3a-b), endurance of >108 (Fig. 3c) and data retention of ~ 7 years have also been demonstrated [10,23,27-29]. These performance metrics put the Ag/a-Si based digital memristive system very favorably against other emerging approaches.

A filament model based on field-assisted drift/diffusion of Ag ions has been developed to explain our devices [23]. In this model, the filament providing the conduction path is composed of a chain of Ag islands, and current is carried out by electron tunneling through the Ag islands and onto the bottom electrode, schematically illustrated in Fig. 4a. This hypothesis was supported by the following observations: 1) The on-state resistance is independent of the device area - we

Fig. 2. I-V characteristics of a digital (a) and analog (b) memristive device. Insets: schematics of the switching mechanisms. Fig.3. (a) Fast 10 ns write and erase pulses used to program the digital

memristive device. Inset: blow-up of the write pulse. (b) The corresponding output signal. (c) Repeated write/erase.

Fig. 4. (a) Semilog plot of the average switching time vs. the bias for a digital memristive device. Inset shows a schematic of the filament growth process. The activation energy barrier Ea for the Ag particle is lowered due to applied bias. (b-c) histogram of the switching time at two different bias conditions. The solid lines are fits for Poisson processes.

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observed that the on-resistance changes by only ~ 40% when the device area was reduced by six orders of magnitude from 1×103 m2 to 2.5×10-3 m2 (50 nm × 50 nm) [10]. This observation suggests that the on-state of the device is dominated by localized nanoscale filaments and is thus independent of the device area. Furthermore, since the off-state conductance is dominated by leakage and is proportional to the device area, this effect leads to an observed improvement of ON/OFF resistance ratio as the device area is reduced, i.e., scaling actually improves the device performance [10]; 2) The switching speed is exponentially dependent on the applied bias. Fig. 4a shows the average switching time vs. the applied bias voltage. An exponential dependence on the bias was observed and can be explained by the lowering of the activation potential for Ag ions during filament growth, as illustrated in the inset to Fig. 4a. Figs. 4b-c plot the histograms of the switching time at two different biases. The statistics of the switching time at each bias can be explained by a Poisson process (solid line fits), confirming the filament growth is a thermally activated process with the activation potential tuned by the applied bias (Inset to Fig. 4a). These observations confirm the hypothesis that the on-state conduction is dominated by a conductive filament and that the filament grows by one step length when a new Ag particle hops into a new trapping site (Fig. 4a); 3) The tunneling model consistently explains the device data. The step-by-step filament formation process schematically illustrated in Fig. 4a is consistent with the current steps observed in the device switching data plotted in semilog plots (e.g. Fig. 5c). Temperature dependent measurements also showed that the on-state conduction is dominated by a tunneling process [28]. Recent imaging studies such as TEM characterizations have

also been able to observe the formation of Ag filaments in the amorphous films [30].

A potential problem for the crossbar based memory and cells. As

illustrated in Fig. 5a, if cells a-c are in the on-state but cell d is in the off-state, current can flow in the highlighted path and

this problem, current rectifying devices are needed to break the shunting paths, and one-transistor-one-resistive-switch (1T1R) or one-diode-one-resistive-switch (1D1R) structures have been proposed [31,32]. The 1D1R structure (Fig. 5b) is more desirable since incorporating transistors at the crosspoints nullifies many of the advantages offered by the crossbar array. Unfortunately, the 1D1R structure may not be suitable for memristive devices due to their bipolar resistance switching nature: a negative bias is needed to erase the device but in this case most of the programming voltage will be dropped across the reverse-biased diode instead of on the memristive device (Fig. 5b). This dilemma has caused research emphasis in the RRAM community to shift to the unipolar type of devices which normally require higher programming current/power, instead of the bipolar memristive devices [32].

The problem however may be circumvented using a memristive device with intrinsic diode characteristics. This device offers current rectifying but does not suffer from the voltage divider effect with an external diode. Indeed, by tailoring the active a-Si material and programming parameters we were able to observe intrinsic diode characteristics in certain nanoscale memristive devices [29]. As shown in Fig. 5c, besides showing well-defined bipolar resistance switching, the device in the on-state shows distinct diode characteristics: the current at positive bias is much higher than that at negative bias. We note that at small negative biases the device still remains in the on-state, as evident in the semilog plot and the fact that reading the device status at small positive read voltage still results in a high on-conductance. The true off-state can only be achieved with a negative erase voltage of < -3 V. The rectifying ratio of the device at voltages of ±1 V is > 105, sufficient for suppressing the shunting paths in reasonably sized crossbar arrays.

Another key attribute of the solid-state electrolyte based approach is its compatibility with CMOS fabrication and its excellent reliability and reproducibility. Fig. 6 shows the results obtained from a prototype high-density crossbar array based on the Ag/a-Si system. This study demonstrated that pitch size down to 100 nm (corresponding to density of 10 Gbit/cm2) can be fabricated at present stage with densities > 100 Gbit/cm2 accessible with improved lithography resolution. More importantly, individual bits inside the array can be addressed with high uniformity (with yield > 92%, Fig. 6c) using an automated test setup [28].

B. Analog Memristor Devices The rich knowledge existed for thin-film deposition further

enabled one to design and explore different device characteristics. For the digital device discussed above, a single conductive filament may dominate the device characteristics. The discrete step-by-step growth of the filament leads to

Fig. 5. (a) Potential crosstalk problem. A faulty on-current can be measured through the current path highlighted by the arrows. (b) The 1D1R structure may solve the crosstalk problem but is not compatible with bipolar memristive devices. (c) Intrinsic diode behavior observed in a-Si memristive devices. Inset: semilog plot of the data.

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Fig. 6. Experimentally demonstrated crossbar memory arrays. (a) SEM image of a 1kb array. (b) A simple 8-and read from the array (c) Low and high resistance states of the first 400 bits within the 1kb array, illustrating the uniformity of the array.

abrupt and discrete changes in the device resistance. On the other hand, a distributed interface and gradual change of the interface can lead to incremental resistance changes (Fig. 2b) and the so called analog memristor behavior [9,33]. In our study on analog memristor devices, Ag and Si were co-deposited (for example, by sputtering) during the device fabrication and an Ag distribution profile was intentionally created during device fabrication [33]. For such devices, a continuous supply of positive (negative) voltage causes a continuous and incremental increase (decrease) of the conductance (Fig. 2b, Fig. 7a), distinct from the abrupt conductance change observed in Fig. 2a for the digital devices. Similar effects were obtained when DC bias sweeps were replaced with programming pulses, as shown in Fig. 7b. Here we show the memristor conductance can be increased incrementally by the application of a series of positive voltage pulses, and decreased incrementally by a series of negative voltage pulses. Tests with random combinations of write and erase pulses [33] further demonstrated the analog operation principle of the memristor device [4,5,33] - that the change in conductance can be controlled by the time integral of voltage, which is in turn determined by both the voltage pulse width and amplitude.

The two-terminal memristor devices allow the emulation of synaptic functions in hardware-based neuromorphic circuits. The large connectivity (1 neuron is typically connected to 104

synapses with a synaptic density of 1010/cm2) is the key that allows the tremendous computing power offered by biological systems (e.g. mammal brain), while in the meantime presenting significant challenges to emulate using CMOS circuits. On the other hand, a synapse is essentially a two-terminal device and bears striking resemblance to the memristor, and the large connectivity can be mapped out in the crossbar structure [32-35]. In this configuration, as schematically shown in Fig. 7d, every CMOS neuron in the

-connected to a large number (determined by the size of the

-memristors at the crosspoints representing synapses.

Fig. 7. (a) Analog (gradual) current-voltage hysteresis. (b) Gradual resistance change obtained from the analog memristive device. P: potentiation, D: depression. (c) Schematic of a memristor synapse approach for neuromorphic systems. (d) A schematic figure for hybrid CMOS neuron/memristor synapse circuits to emulate the biological neuron system.

We have shown that an integrated analog memristor/CMOS neuron circuit system (Fig. 7) can offer several critical synaptic functionalities such as Spike Timing Dependent Plasticity (STDP), one of the key learning mechanisms of brains to adapt to (learn from) environmental changes. In STDP, a synaptic connection between two neurons is altered as a function of the timing difference between the pre-synaptic ( - tro-chemical signals in bio-systems) (Fig. 8b). By demonstrating this crucial learning rule in a memristor/CMOS neuron circuit system (Fig. 8a), we show this approach indeed has the potential to provide a path for hardware implemented neuromorphic systems, which may one day offer comparable density but orders-of-magnitude faster speed compared with the cerebral cortex [34,36].

Figure 8. Demonstration of STDP in the artificial synapses based on memristive devices. (a) Experimentally obtained synaptic activity (STDP) from the memristor synapse. Inset: fabricated artificial synapses. (b) An example of STDP observed in actual bio-neuron systems. Inset: A phase contrast image of a hippocampal neuron. The neuron image and STDP data were adapted with permission from Nature Protocols 1, 2406-2415 (2006) & J. Neurosci. 18, 10464-10472 (1998).

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III. MODELING

A device model based on field-assisted drift/diffusion of Ag ions has been developed to explain and help predict the memristor device characteristics [35,37]. The behavior of a general memristive device can be described by a pair of coupled equations [4-6],

vvwGi ),( (1) and

),( vwfw (2) Here Eq. (1) is the normal I-V equation for a resistive device, where w is an (or a group of) internal state variable(s). However, unlike normal devices where the internal state variable w is determined by the present control signals, in a memristive device, only (dw/dt), i.e. the rate of the state variable change, is explicitly determined. Eq. (2) thus implies that the state of the device depends on the history of the device. The state of the memristor can only be determined by solving Eqs. 1-2 self-consistently. In addition, by choosing different internal state variables and modifying the rate equation (2), a broad range of devices can be shown to fall in the general category of memristive devices.

For example, by using a tunneling equation in Eq. (1) and using the length of the conducting filament as the state variable in Eq. (2), the sharp I-V switching curve (e.g. Fig. 2b) can be predicted without inserting any threshold effects. The transient effect such as time-to switch can also be well predicted [23,37]. On the other hand, for the analog memristors as shown in Fig. 7, we found the device behavior can be best described by treating the state variable w as an area index (e.g. the number of filaments in filamentary resistive devices or the area of the conductive region in ionic devices) [35]. In other words, the gradual increase in device conductance is caused by the increase in the number of parallel conduction channels (or effectively the channel area) due to the motion of metal ions or oxygen vacancies in metal-oxide based memristors [35]. The current through the device can be described by a Schottky contact in the ion poor region and an Ohmic-like contact (dominated by tunneling) in the ion-rich conducting region [22,35], i.e.

)sinh()]exp(1[)1( VwVwI (3) Here the 1st term describes the Schottky term and the 2nd term describes the tunneling term, with w representing the portion of the tunneling (ion rich) area, i.e. w = 0 indicates fully Schottky-dominated conduction while w = 1 indicates fully tunneling-dominated conduction.

In addition, the memristor rate equation (2) can be written as

)]exp()[exp( 21 VVdtdw

(4)

Here , , , , 1, and 2 are all positive-valued parameters determined by material properties such as the barrier height for Schottky barrier and for tunneling, the depletion width in the Schottky barrier region, the effective tunneling distance in the conducting region, and interface effects. In practice they can be treated as fitting parameters and are independent of w.The expression of Eq. 4 is based on the observed effect that the drift rate of the ions (or oxygen vacancies) is a field-

assisted thermal activation process and is exponentially dependent on the applied field at the conditions producing resistance switching [23,38]. Eq. 4 was also chosen such that (dw/dt) can be different at positive and negative biases ( 1 2)to account for potential differences in the activation energies for forward and backward ion hopping, e.g. in the presence of a build-in field. Having asymmetric activation energies ( 1 2)however is not essential in modeling. Normally we can keep

1= 2= , Eq. 4 thus reduces to the usual simpler form of sinh function [23,38].

Fig. 9. (a) Simulation results based on Eqs. 3-4. The device experiences 5 consecutive positive voltage sweeps followed by 5 consecutive negative voltage sweeps. (b) Simulation results based on Eqs. 3 and 5 including the diffusion term.

Simulation results based on the model of Eqs. 3-4 using matlab are shown in Fig. 9 with 5 consecutive positive voltage sweeps followed by 5 negative voltage sweeps. This model captures many of the observed experimental results including the incremental resistance change, as well as the switching dynamics and transient effects. Such a model will likely be useful in circuit analysis of the proposed memristor-based memory or logic circuits.

In addition, Eq. 4 can be modified to include a diffusion component. Specifically, the more resistive state is normally the thermodynamically ground state [38], diffusion of ions will leads to a natural decay to that state and result in dissolution of the conductive region, which in turn explains the finite retention of the memristor devices particularly the analog ones which rely on the high mobility of ions or oxygen vacancies. By adding a diffusion term, (-w/ , where is a diffusion time constant, the rate equation Eq. 4 can be rewritten as

wVdtdw )]sinh(

(5) I-V curves based on the new model using Eqs. 3 and 5 are shown in Fig. 9b. The model including the diffusion term produces an overlap of the hysteresis curves that have been observed in some analog memristor devices [35,39] due to relatively short retention. In addition, results of voltage-pulse based programming operations are also reliably captured by the model shown in Fig. 10, further proofing the validity of the model.

Finally, the device model based on Eqs. 3-5 can be readily implemented into the SPICE simulator library using LTspice [35] by using a floating capacitor to store the value of the internal state variable w [40]. Eqs. 3-5 can then be solved self-consistently in the memristor SPICE sub-circuit. Simulation results based on the SPICE model are identical to that of

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Fig. 10. Simulation of analog memristor devices based on Eqs. 3 and 5. The device experiences 50 positive voltage pulses followed by 50 negative voltage pulses.

IV. CONCLUSION

Two-terminal resistive switches (memristors) can potentially supplement or replace CMOS in certain memory and logic applications. Here we discussed the structure, operation, modeling and applications of memristors based on a solid-state electrolyte. By adjusting the material and device structure and through appropriate programming sequences, a number of switching characteristics can be observed. Memristor devices exhibit extremely non-linear I-V behaviors and unconventional transient effects. Careful device optimization, modeling and circuit simulation will likely one day lead to memristor-based memory and logic circuits with much higher function density and power efficiency than that can be achieved through transistor scaling alone.

ACKNOWLEDGMENT

W. L. thanks Drs. S. H. Jo, N. Srinivasa and M. Laiho for helpful discussions and suggestions.

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[31] A. Chen, S. Haddad, Y. C. Wu, T. N. Fang, Z. Lan, S. Avanzino, S. Pangrle, M. Buynoski, M. Rathor, W. D. Cai, N. Tripsas, C. Bill, M. VanBuskirk, and M. Taguchi, "Non-volatile resistive switching for advanced memory applications," IEDM Tech. Dig., pp. 765-768, 2005.

[32] M. J. Lee, Y. Park, B. S. Kang, S. E. Ahn, C. Lee, K. Kim, W. X. Xianyu, G. Stefanovich, J. H. Lee, S. J. Chung, Y. H. Kim, C. S. Lee, J. B. Park, I. G. Baek, and I. K. Yoo, "2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications," IEDM Tech. Dig., pp. 771-774, 2007.

0 100 200 300 400 5000.0

1.5

3.0

4.5

I (uA

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[33] S. H. Jo, T. Chang, I. Ebong, B. Bhavitavya, P. Mazumder and W. Lu,

Nano Lett., 10, 1297-1301 (2010). [34] G. S. Snider, "Cortical Computing with memristive Nanodevices,"

SciDac Review, pp. 58-65, 2008. [35] T. Chang, S.-H. Jo, K.-H. Kim. P. Sheridan. S. Gaba and W. Lu,

Appl. Phys. A. accepted.[36] K. K. Likharev, "Hybrid CMOS/Nanoelectronic Circuits: Opportunities

and Challenges," J. Nanoelectronics and Optoelectronics, vol. 3, pp. 203-230, 2008.

[37]

[38] D. M. Strukov, R. S. Wiland low volatility of thin- Appl. Phys. A 94, 515 (2009).

[39]97, 012902 (2010).

[40]Radioengineering, vol. 18, no. 2, pp.

210 214, 2009. [41] M. Laiho, E. Lehtonen, P. Kanerva, and W. Lu,

submitted.

Wei Lu ) received the B.S. degree in physics from Tsinghua University, Beijing, China, in 1996, and the M.A. and Ph.D. in physics from Rice University, Houston, TX in 1999 and 2003, respectively. From 2003 to 2005, he was a postdoctoral research fellow at Harvard University, Cambridge, MA. In 2005, he joined the faculty of the Electrical Engineering and Computer Science Department at the University of Michigan as an assistant professor.

Prof. Lu is a co-Editor-in-Chief for Nanoscale, a member of the IEEE, APS, MRS, an active member of two IEEE technical committees and several program committees. His research interest lies in the application and fundamental understanding of nanostructures and nanodevices, including high-density memory and logic devices based on two-terminal resistive switches (memristors), and semiconductor nanowire based electronics. He is a recipient of the NSF CAREER Award.

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