Systematic Design of Multi-Bit Continuous-Time Delta-Sigma Modulators Using Two-Step Quantizer

Sakkarapani BaZagopaZ, Rajaram Mohan Roy KoppuZa and VishaZ Saxena

Electrical and Computer Engineering Department, Boise State University Boise, ID 83725-2075.

Email: {sakkarapanibalagopal.rajaramkoppula.vishalsaxena}@u.boisestate.edu

Abstract-A 50 0 MS/s, wideband 4thorder continuous-time delta sigma modulator (CT-.6I:M) using a two-step 5-bit quan­tizer, consisting of only 10 comparators, is proposed and pre­sented using O.18t.tm CMOS technology. A proposed modulator takes advantage of the high resolution two step quantization technique and an excess loop compensation of more than one cycle to achieve a low-power, high dynamic range with a wide conversion bandwidth. A robust systematic design method is used to determine the loop filter coefficients by considering the non­ideal opamps effects including the finite gain and the presence of multiple internal poles and zeros . T he proposed CT-.6I:M achieves a dynamic range of 75.83 dB, peak SNR of 75.1 dB with 25 MHz bandwidth (OSR = 10) while consuming only 27.5 m W from the 1.8 V supply. T he relevant design trade offs have been investigated and presented with simulation results.

Index Terms-Analog-digital (AID) conversion, two-step flash ADC, continuous-time (CT), CIFF, sigma-delta(I:.6).

I. INTRODUCTION

C ONTINUOUS-TIME delta-Sigma (CT-L.E) analog to digital converters (ADCs) are becoming an attractive

choice in broadband wireless communication systems due to several attractive features like inherent anti-aliasing fil­tering (AAF) , relaxed bandwidth requirements of the active elements and lower power consumption when compared to their discrete-time counterparts. However, the rapid evolu­tion of wireless data communication standards, in recent years, demands higher signal bandwidth and signal-to-noise ratio (SNR) from CT-L.E ADCs. To achieve a wider signal bandwidth in CT-L.E ADCs, the designers are limited by the lower oversampling ratio (OSR) for a given clock rate. Furthermore, any limitation on overs amp ling ratio limits the maximum achievable SNR. In order to compensate for the SNR degradation due to lower OSR, higher resolution, i.e. multi-bit quantizers are often used [ 1], [2], [3]. Several CT-L.E modulator targeting 10-12 bits resolution with a signal band­width ranging from 5-20 MHz have been recently reported [2], [3].

Continuous-time Loop-Fllter

L(s)

Figure 1. General block diagram of a CT-6I: modulator.

Contlnuous-tlma Loop�ilt.r

L(s)

Figure 2. Block diagram of a CT- 6I: modulator with an SIH.

There are several advantages in using a multi-bit quantizer, which include a lower quantization noise floor and higher dynamic range, relaxed slew-rate requirements in the loop­filer opamps. A lower LSB size allows a higher out-of-band gain (OBG) which allows aggressive noise shaping with higher maximum stable amplitude (MSA) [2], [4]. Increasing the resolution above 4-bits results in an exponential increase in circuit complexity, as increase in I-bit in the quantizer requires a doubling of the number of comparators. Also, in a given technology, the maximum achievable sampling frequency, is,max is primarily constrained by the tolerable excess loop delay (ELD) in the CT-L.E loop. ELD is primarily contributed by the finite regeneration time of the comparator latches in the quantizer and the delay from the dynamic element match­ing (DEM) logic in the feedback DAC. Recently, discrete­time (DT) L.E modulators with multi-step quantization have been reported reported [5]. The modulators exploit the lower quantization noise available with multi-stage quantizers by developing techniques to accommodate the increased quantizer latency. In this paper, we propose a first CT-L.EM which employs a two-step quantizer with more than 4-bits resolution. The additional delay, greater than the clock period (Ts), due to the two-step conversion is compensated using a sample­and-hold (SIH) based technique illustrated in [6]. Typically, in a conventional CT-L.EM, ELD is selected to be smaller than 0.5 for reduced sensitivity of the loop-filter coefficients with process spread. However, with this ELD compensation method, an ELD of 1.5 can be allowed which can lead to up to three-fold increase in the sampling rate (/s). In this work, the latency of the two-step quantizer is accommodated, using the SIH based ELD compensation, without sacrificing the sampling rate.

The architecture and implementation details of the CT­L.E, employing a two-step quantizer, form the discussion of rest of the paper. Section II illustrates the technique for

978-1-61284-857-0/11/$26.00 @2011 IEEE

ELD compensation greater than one clock cycle. Section III demonstrates the system level design of CT-6� using the two-step quantizer. Section IV discusses the circuit level implementation of the proposed CT-6� modulator. Section V presents the simulation results of the proposed modulator. Finally, section VI draws conclusions about the work.

II. COMPENSATION FOR AN ELD > 1 CLOCK CYCLE

Fig. 1 shows the block diagram of the traditional single-loop CT-6� modulator. In this figure, L(8) is the continuous-time loop filter, implemented using cascaded integrators with dis­tributed feed-forward summation (CIFF) architecture, whose output is sampled and quantized at frequency, fs , or equivalent time period Ts. ko is the gain of the direct path introduced to compensate for an ELD of less than one clock cycle. Con­ventionally, the loop-filter coefficients K = [ko kl k2 ... k nL where n is the order of the loop filter, are obtained by least-square fitting the impulse response of discrete-time loop filter Ld(Z) = 1 - NTF-I(z) to the continuous time loop­filter,Lc (8) ,using the impulse invariance transformation (lIT) for a given delayed feedback DAC pulse shape [ 1], [4]. The ELD compensation method using the direct path around the quantizer (ko) performs adequately well as long as the excess delay is less than a clock cycle (i.e. ELD < 1).

Fig. 2 shows the modified CT-6�M block diagram, in­corporating an ELD compensation technique of more than one clock cycle. Here, the ELD compensation is achieved by using an additional feedback path around the sampler using a sample-and-hold (SIH) with a gain a. The purpose of this fast loop is to restore the second sample of the open-loop response, l[n]. Due to this additional loop formed by the SIH, an extra zero appears in the resulting noise-transfer function (NTF). Therefore, the resulting noise-transfer function NT Fnew (z) is of the form

NTFnew(z) = (1 +az-I).NTForig(Z) ( 1)

where NTForig(z) is the originally desired NTF without the SIH short loop [6].

The remaining samples of l[n] are restored by appropriately choosing loop-filter coefficients K = [ko kl k2 ... k n] by least squares fitting the following equation.

h[n] @ f[n] + rho hI h2 ... h n]K = J[n] (2)

where h[n] and f[n] are the impulse response of the NTForig(z) and (1 + az-I) respectively. Further, horn] = lorn] @ h[n], hdn] = h[n] @ h[n], . . . , where lorn] and ldn] represent the sampled DAC pulse response of direct path and at the output of ith integrator. By rearranging the above eq. 2, the value of K can found by least squares fitting eq. 3.

rho hI h2 ... h n]K =f[n]- h[n] @ f[n] (3)

The systematic method of obtaining the loop-filter coeffi­cients using eq.3 is more robust, as it considers the effect the integrator non-idealities including finite op-amp gain (AoL) and the presence of additional poles and zeros. Even though, the ability to tolerate and ELD in the range of 1 to 1.5 increases the achievable sampling rate (fs) by a factor of

2

7

C!)� 6f---t---r----:.;'" '" o 5

4

2.5 3.5 OBGorig

Figure 3. 0 BG orig V sO BGnew for 3rdand 4th order CT-6� modulators.

20 0 ,-------------- --�- _J___l___ or--r--l'i ' .......... iD "

I·, or-/'/ (f • ] -20

5, :l1.JO 1' /' 'rt

I

t

Order • 4 OSR =10 OBGorlg" 3 I-OBGnew'" 7

-ELO<1 f------ ELO = 1.5 I I -500 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 001,

Figure 4. INTF(ejW)I showing the effect of (1 + az-1 ) in the NTFnew(ejW).

2, there are few drawbacks. Fig. 3 shows the comparison between the resultant OBG (OBGnew) with 1 < ELD < 2 with the desired OBG (OBGorig). The larger OBGnew of the NTFnew results in increased 'wiggling' of the quantizer output sequence. As a consequence, the signal variation at the input of the quantizer (Yc( t)) is increased by a larger extent and thus overloading the quantizer more often, which significantly reduces the maximum stable amplitude (MSA). Therefore, in order to design a stable modulator with ELD > 1, either a lower OBG should be used (OBG ::; 2) or a higher resolution quantizer (resolution> 4) with lower LSB size must be used to achieve a desirable MSA in the range of O.S. In this design, a 5-bit quantizer is used which allows for an aggressive OBG of NTForig(z) to 3, and achieves a desirable MSA.

III. SY STEM LEVEL DESIGN OF PROPOSED CT-6� ADC

This section briefly demonstrate the various architectural choices made in our design.

A. Architectural Choices

For low OSR design, increasing the order above three doesn't give much improvement in SNR [2]. However, due to additional zero in NTFnew(z) have demote the SNR performance of CT-6� by an order [6]. Therefore, to com­pensate it, forth order loop filer is chosen. Further, for better stability and desirable MSA of the 4th order, 5-bit multibit single-loop modulator, OBGorig is chosen as 3 (corresponding OBGnew is 7). Fig. 4 illustrates the magnitude responses of NTForig(ejW) and NTFnew(ejW) before and after the ELD compensation respectively.

Figure 5. The last integrator of L(s) is used a summation amplifier[6j.

B. Loop Filter Design

A loop-filter architecture with cascaded integrators with dis­tributed feed-forward summation (CIFF) is used to implement the 4th order loop filter. Table I shows the coefficients of a fourth-order NTForig(z), with OBGorig = 3, and optimized zeros is given for ELD < 1, ELD = 1.5 (with ideal opamp) and ELD = 1.5 (including opamp non-idealities (NI)

AOL 1+_8_ (i.e) A( s) = ) "'.1 ) ). Also, in order to decrease 1+_8_ 1+_8_ ""pI ""'p2 the power dissipatIOn and avoid the delay introduced by summation, the last integrator is used for the summation as shown in the fig. 5 [6]. Due to the use of 5-bit quantizer, the slew rate requirements on the first integrator in the loop filter are greatly relaxed.

Table I COEFFICIENTS OF A FORTH ORDER NTF(z)FOR ELD < I, = 1.5 AND

=1.5(INCLUDING OPAMP NON-IDEALITIES(NI))

C. Quantizer Design

A 5-bit, 500MS/s two-step flash ADC with NRZ feedback DAC is employed as the quantizer. Fig. 6 shows the singly­ended representation of the two-step flash quantizer system level schematic [7]. The first stage of the quantizer comprises of 7 comparators and is followed by a 3-bit segmented capacitor DAC. The output of a DAC is directly coupled to the switch-capacitor residue amplifier. The residue amplifier drives the 3 comparators in the fine flash stage. The quantizer full-scale range is set to 2.4Vpp, which results in a step size of 300 m V in the coarse flash stage and 150 m V in the fine flash stage. The chosen full-scale range relaxes the offset requirement on comparator in the two-step flash ADC. During the phase <PI, the coarse flash stage estimates the three most significant bits (MSBs) of the sampled signal and provides an equivalent thermometer code output. The resultant code drives highly linear segmented capacitive DAC to decode the signal back to 3-bit resolution analog signal. Then, during the clock

Vre, VI.. V ... , ? ? ? " , : : 7·Comparators : " ,

r--;L ��o:Lc ________ C _____ ! - 'I

Course flash stage

amplifier

-:- Fine flash stage

Figure 6. Simplified single-ended function diagram of ADC.

Figure 7. Two stage operational amplifier used in a CT-ll.I; modulator.

3

phase <P2, residue Vsub is estimated by the residue amplifier by subtracting Vdae from Vin. Finally, the fine stage digitizes the residue Vsub to encode the two least significant bits of the ADC. Further, during <Prst clock phase, all the capacitors in the circuit are reset or discharged to ground. The time delay assigned to the first flash stage, DAC and the Subtractor combined together is 0.8Tsand, the time delay assigned to the second flash stage and current DAC combined is 0.7Ts.Thus, the net delay introduced by the 5-bit quantizer including the DEM logic is 1.5Ts.

IV. CIRCUIT DESIGN

In this section, the circuit level blocks, used in the CT-D� modulator, are described. The proposed CT-D� modulator was implemented in a 0.18 J-Lm CMOS technology.

A. Operational Amplifier

Fig. 7 shows the schematic of the a two-stage opamp compensated for high-speed. A PMOS diff-pair is used as the first stage and a class-AB buffer is used as the second stage. Ml to M6 are long length devices to mitigate the input referred flicker noise. A compensation capacitor, GIG, of 5001 F is employed in the design. To ensure that the op-amp common mode output voltage is held at Vern, separate common mode feedback (CMFB) loops are used in both of the op-amp stages. The total current drawn by the 1 st and 4th operational amplifier including the CMFB circuitry is 2.1mA and 2.3mA.

B. Comparator

The circuit diagram of the comparator used in the flash ADC is shown in the fig. 8. The operation of the comparator

Figure S. Comparator circuit [2].

-40

-60

[2 -80 tIl "0

-100

-120

-140

Figure 9. PSD of the modulator for a 12. 3M H z input tone at the maximum stable amplitude.

is as follows. When <Pre! and <Pem is high, the two differential capacitors, Cb, are charged to Vre!p - Vcmand Vre!m - Vem respectively. Upon turning OFF the switches <Pre! and <Pem and turning ON the reset switch <Prst, the nodes Vxand Vyare set to Vdd/2. When <Prst goes low and <Pclk goes high, the nodes Vxand Vy are connected to input Vinp and Vinm. Thus, the differential voltage across the nodes Vx and Vy is set to (Vinp - Vinm) - (Vre!p - Vre!m), which creates an imbalance in the latch. After giving enough regeneration time, the data is latched into C2 M 0 S. On account of the high input range of the ADC and LBS size, the offset requirements of the comparators in the first stage are highly relaxed. Further, the residue amplifier at the input of the fine stage relaxes the offset requirement on the fine stage comparators.

V. SIMULATION RE SULT

The 4th order CT-L.E ADC has been designed in the O.lSp,m CMOS process. Fig. 9, 10 shows the PSD of the

Table II SUMMARY OF SIMULATED ADC PERFORMANCE

Signal Bandwidth/Clock Rate 25MHzl500MHz Quantizer Range 2.4V"".dif f Maximum Stable Amplitude (MSA) -1.468dBFS Dynamic Rangel SNR 75.83dBI75.1dB Processl Power Supply Voltage 0.18tlm I 1.8V Power Dissipation 27.5mW Figure of Merit O.l1pJjlevel

4

12

10

8 <iI '" So ..: 6 z VI

4

0

·90 -80 ·70 -60 -50 40 ·30 -20 -10 0 ADe Input (dBFS)

Figure 10. Simulated SNR and dynamic range.

modulator output of a 12.3MHz input tone for an amplitude that results in the peak SNDR and simulated SNR and dynamic range respectively. A 64K point Hann window is used in the the PSD computations. The measured SNR of the modulator for a 12.3MHz input tone is 75.1dB. The measured dynamic range of the modulator is . Table II summarizes the simulated performance of the modulator. The modulator presented in this paper achieves O.llpJ /level. The modulator dissipates around 27.5mW power from a 1.8 V supply and achieves a FoM of O.llpJ /level.

VI. CONCLUSION

A novel CT-L.EM using a two-step quantizer is proposed and designed in a O.lS{Lm CMOS technology. The proposed modulator achieves a high dynamic range with very wide conversion bandwidth using a 5-bit two-step quantizer. ELD greater than one clock cycle was successfully compensated using a fast loop around the quantizer. The CT loop-filter coefficients are systematically computed by incorporating the opamp non-idealities. The simulation results of the proposed CT-L.EM exhibit a peak SNR of 75.1dB, a dynamic range of 75.S3dB with a MSA of -1 .46SdBFS .

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