52 • 2011 IEEE International Solid-State Circuits Conference

ISSCC 2011 / SESSION 3 / RF TECHNIQUES / 3.1

3.1 Spur-Free All-Digital PLL in 65nm for Mobile Phones

Robert Bogdan Staszewski1, Khurram Waheed2, Sudheer Vemulapalli2,Fikret Dulger2, John Wallberg2, Chih-Ming Hung2, Oren Eliezer2

1Delft University of Technology, Delft, The Netherlands, 2Texas Instruments, Dallas, TX

After the first-ever all-digital PLL (ADPLL) [1] for Bluetooth radios has provenbenefits of CMOS scaling and integration, demonstrators for more challengingwireless standards have emerged [2-6]. In the ADPLL, however, the digitally-controlled oscillator (DCO) and time-to-digital converter (TDC) quantize the timeand frequency tuning functions, respectively, which can lead to spurious tonesand phase noise increase. As such, finite TDC resolution can distort data modu-lation and spectral mask at near integer-N channels, while finite DCO step sizecan add far-out spurs and phase noise. Also, a major underreported issue is aninjection pulling of the DCO due to harmonics of the digital activity at closely-spaced frequencies, which can also create spurs. This work addresses all theseproblems and demonstrates RF performance matching that of the best-in-classtraditional approaches.

The finite TDC resolution tinv of 10 to 20ps produces low-enough flat quantiza-tion noise for satisfactory RF operation with ADPLL bandwidths of up to 150-300kHz. However, at integer-N channels, and especially when the TDC resolutionis an integer multiple of the DCO period, the quantization noise is ill-shaped andcan concentrate within the loop bandwidth. To solve the problem, FREF dither-ing of up to several tinv is used by delaying the FREF clock by means of slowingdown the edges [6,7] through adjustment of an inverter driving strength to itsload capacitance ratio. Unfortunately, degrading FREF clock edges not only addssignificant noise but also makes it more sensitive to various aggressors. Figure3.1.1 shows the proposed noise-free method, in which the crystal oscillator (XO)slicer combines the programmable edge delay and performs time shift Δtcd bydynamically adding intentional mismatch transistors Mcd1,2 to the differentialinput pair Mp1,2. This way, the programmable voltage offset ΔV = ~30mV getsconverted to coarse dither time offset tcd = ~100ps through the sinusoidal wave-form slope at the origin. The coarse dither, when engaged at near integer-Nchannels by synchronously toggling at 2.4MHz rate, uses only two levels, -Δtcdand +Δtcd, so its transfer function is perfectly linear. The exact Δtcd value is notcritical as long as it spans several tinv. The high toggling rate places the result-ing mixing products outside of the higher-order ADPLL loop filter.

A second supplementary method, fine dithering, is added by connecting 16 unit-weighted transistors Mfd1-16 in parallel with Mbp2 to change the mirroring ratio,thus affecting the bias current of the differential pair, and ultimately the delay of~9ps/LSB. They are digitally-controlled by 3rd-order ΣΔ MASH sequence.

Figure 3.1.2 shows the top-level diagram of the multirate ADPLL, which featuressupport of modulating samples of much higher rate than the reference clock. Infact, FREF does not play any role in the data modulation. Consequently, XO couldbe free-running and the reference frequency adjustment performed through thefrequency command word (FCW). The phase error φE samples at FREF rate getconverted to channel-dependent DCO/16 rate by the sample-rate converter(SRC) and merged with the modulating samples of the same rate. The fraction-al bits get further dithered by the ΣΔ modulator operating at DCO/8 rate. Thisway, the injection-pulling spurs of the prior implementations [1,2], with the inputat FREF rate, are avoided.

The single DCO gain-normalization multiplier of the prior implementations getssplit into two parts: a fine-precision multiplier in the data modulation path and acoarse multiplier (right bit shift) of the filtered φE. This allows making hitlessperiodic normalization adjustment which could be problematic if φE had a largedc component.

The ADPLL operates in the phase domain by counting the number of the DCOclock edges (variable phase – RV[i]), sampling it on FREF (RV[k]) and compar-ing it to the accumulated value of FCW (reference phase – RR[k]). Fine resolu-tion of RV is obtained through the TDC-based interpolator, whose normalizedoutput ε[k] = [0,1) signifies the position of the FREF edge with respect to the twoneighboring DCO edges.

The retimed FREF clock, CKR, which is used for the φE generation and filtering,is obtained in a metastability-free manner by speculative resampling of FREF bythe rising and falling DCO clock edges, and using the path (CKR_P or CKR_N),which is farther away from metastability, based on the arbitration signalSEL_EDGE from the TDC. The arbitration signal is simply a tapped delay of aquarter of the DCO period. A similar speculative mechanism is used for 3 LSBbits of the variable phase RV that are counted asynchronously in a carry-ripplemanner. Finally, the LSB bits of RV get merged with 5 MSB bits of RV, which isbased on a synchronous counter.

Figure 3.1.3 reveals a technique to lower spurs due to injection pulling. They arelikely to happen when the higher harmonic of the digital baseband (DBB) clockfalls into the vicinity of the DCO LC-tank resonant frequency. The coupling mech-anism could be magnetic (DCO inductor, bondwires), capacitative (long parallelwires), through the substrate, through ground/supply common IR drop, etc. Theinjection-pulling force gets reduced when the DCO itself is used to clock theDBB, rather than the accompanying PLL. In addition, applying clock ditheringfurther reduces the spurious tones by at least 5dB.

Figure 3.1.4 demonstrates effectiveness of the coarse dithering in both CW andGSM modulated modes. The carrier is 200kHz and 400kHz away from the 46th

harmonic of the 38.4MHz FREF. Since the DCO LC tank resonates at 2× of thehigh-band frequency, the injection-pulling spurs will be 400kHz and 800kHzaway from the carrier, respectively. The quantization noise, however, has a com-plex pattern, which is analyzed in [8]. Engagement of the coarse dithering elim-inates the ill-shaped quantization noise (mainly causing modulation distortion)and injection pulling (mainly causing spurs).

Figure 3.1.5 shows a typical measured far-out phase noise in the receive bandsof GSM-850 and GSM-900 during the 2-point GFSK modulation of the DCO, aspart of a design-of-experiments (DoE) with 7 IC’s to fully cover the manufactur-ing process corners. The higher bands (DCS-1800 and PCS-1900) also showsimilar behavior. It proves the virtually spurious-free ADPLL operation that guar-antees GSM-compliant SAW-less transmit operation. Note that the GSM spec of-112dBc/100kHz corresponds to -162dBc/Hz with RBW=100kHz.

The table in Fig. 3.1.6 summarizes the ADPLL performance, when used as aGSM transmitter, which is equal to or better than the best-in-class conventionaldesigns. The transmitter data is also given since the ADPLL is intimately tiedwithin the 2.5G transmitter. Estimated area of the ADPLL is 0.35mm2, which ismostly occupied by the DCO. The current consumption is 32mA and 38mA inlow-band and high-band, respectively. Figure 3.1.7 shows the chip micrographof the transceiver implemented in TI’s 65nm digital CMOS.

References:[1] B. Staszewski et al., “All-digital phase-domain TX frequency synthesizer forBluetooth radios in 0.13μm CMOS,” ISSCC Dig. Tech. Papers, pp. 272–273, Feb.2004.[2] R. B. Staszewski et al., “All-digital PLL and GSM/EDGE transmitter in 90nmCMOS,” ISSCC Dig. Tech. Papers, pp. 316–317, 600, Feb. 2005.[3] C.-M. Hsu et al., “A low-noise, wide-BW 3.6GHz digital ΔΣ fract.-N frequen-cy synthesizer with a noise-shaping TDC and quantization noise cancellation,”ISSCC Dig. Tech. Papers, pp. 340-341, Feb. 2008.[4] H.-H. Chang et al., “A fractional spur-free ADPLL with loop-gain calibrationand phase-noise cancellation for GSM/GPRS/EDGE,” ISSCC Dig. Tech. Papers,pp. 200-201, Feb. 2008.[5] C. Weltin-Wu et al., “A 3GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction,” ISSCC Dig. Tech. Papers,pp. 344-345, Feb. 2008.[6] C. Weltin-Wu et al., “A 3.5GHz wideband ADPLL with fractional spur sup-pression through TDC dithering and feedforward compensation,” ISSCC Dig.Tech. Papers, pp. 468-469, Feb. 2010.[7] R. Staszewski et al., “Elimination of spurious noise due to time-to-digitalconverter,” IEEE Dallas Circuits and Systems Workshop, pp. 67-70, Oct. 2009.[8] S. D. Vamvakos et al., “Noise analysis of time-to-digital converter in all-dig-ital PLLs,” IEEE Dallas Circ. and Sys. Workshop, pp. 87-90, Oct. 2009.

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ISSCC 2011 / February 21, 2011 / 1:30 PM

Figure 3.1.1: Crystal oscillator slicer with coarse (3-level) and fine (16-level)delay control. Figure 3.1.2: Top-level diagram of multirate wideband all-digital PLL.

Figure 3.1.3: Digital baseband (DBB) clock is synchronous to the DCO clock.Dithering the DBB clock lowers the DBB induced spurs.

Figure 3.1.5: Measured TX WBN in the RX bands in 7 IC’s covering all processcorners: (top) GSM-850: 20-to-45MHz offsets from 848.8MHz; (bottom) GSM-950: 10-to-45MHz offsets from 914.8MHz.

Figure 3.1.6: ADPLL key performance when transmitting in GSM GMSK modeand implementation table.

Figure 3.1.4: Measured effect of coarse dither at 2.4MHz on CW-(top) andGMSK-modulated (bottom) spectra at 200kHz (left) and 400kHz (right) awayfrom 1766.4MHz integer-N channel.

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• 2011 IEEE International Solid-State Circuits Conference 978-1-61284-302-5/11/$26.00 ©2011 IEEE

ISSCC 2011 PAPER CONTINUATIONS

Figure 3.1.7: Chip micrograph.