20th Iranian Conference on Electrical Engineering, (ICEE2012), May 15-17,2012, Tehran, Iran

Improvement of Timing Specifications in Second

Order Electronic Systems Using Programmable

CMOS Posicast Pulse Shapers

M. Rahimi, Shahed University

School of Engineering, Shahed University Shahed University of Tehran

Tehran, Iran marahimi@shahed.ac.ir

Abstract- In this research we present a new programmable

pulse pre-shaper to efficiently reduce the overshoot of second

order electric and electronic systems. In the proposed design,

the input step pulse is passed from the delayed unit. The delay

unit changes the arrival time of input pulse with different

controlled digital input lines values for rising and falling edges.

Then the resulted delayed pulse is added with the original step

pulse with analog adder circuit to prepare the final Posicast

signal. In the proposed circuit the voltage levels are controlled

with two other input code words. The proposed design is

simulated and all the simulations are prepared using 0.18u

CMOS technology with HSPICE. Our experimental results

show that, the proposed delay and adder circuits work linearly

respects to the code word. To show the correctness and

effectiveness of the proposed circuit, the Posicast pulse is

applied on a real CMOS Op-Amp. The Simulation results

show a significant reduction on the overshoot and settling time.

Keywords-component; Overshoot; Posicas; Pulse pre-shaper,' Second order system; Step response

I. INTRODUCTION

Step response of the target system is a good measure on the evaluation of the systems. In this case, the target­parameters are rise time, peak time, settling time and overshoot.

Most of the electronic systems used for amplifications or filtering may be approximately modelled with a second order system. The generated transfer function of a second order system is given by Equation (1). Where � is the damping factor and 'l,\rn is the system natural frequency in the time domain.

-- = --=----------=-B{ ,Ii;) .Ii;

(1)

Settling time and overshoot percent are two parameters for evaluating the speed and stability. In the frequency domain, phase margin is used for evaluating the system

978-1-4673-1148-9/12/$31.00 ©2012 IEEE 309

M. B. Ghaznavi-Ghoushchi, Shahed University

School of Engineering, Shahed University Shahed University of Tehran

Tehran, Iran ghaznavi@shahed.ac.ir

stability which is reciprocal of overshoot percent in time domain. The relation among phase margin and overshoot percent is depicted in Fig. 1 [1].

20 . . -: ...

10

Phase MiJrgln (degrees)

Figure 1. Overshoot percent versus phase margin [2].

Our main goal in this paper is to introduce a programmable pre-shaper system helps to have removed or reduced overshoot. The basic idea of this plane is the delay in input pulse and adding base pulse and delayed pulse. In this plane delay and the amplitude of voltage levels are controlled with input code word.

This paper includes following part: theory of Posicast explained in section 2. Proposed delay and adder circuits are presented in section 3. In section 4, simulation results are presented. In section 5, outputs of the proposed circuits are applied to a real Op-Amp. Finally section 6 concludes the paper.

II. CONCEPTS AND THEORY OF POSICAST

As seen in Fig. 2(a)-dashed, the step response of the under-damped second order system having oscillation.

Generally, the overshoot of a second order system with the step input, can be easily described by two parameters. The first parameter is the time to the first peak arrival which is half of the under-damped response period ( Toll )' The

second parameter is the peak value of I +cS where cS is the normalized overshoot level. The range of normalized overshoot varies from zero to one [1, 2, 3, 4]. As seen in Fig. 2(b) in the Posicast command pulse [1, 2, 3, 4] the original step input command is divided into two parts. The first section is a scaled step command which provides the first peak of the system to precisely meet the desired final value. The second part of the reshaped input is a full scale and time­delayed original step command. The overall effects of the former and the later pluses results in cancel of the remaining oscillatory response. Finally it ensures the system output to be at the desired value [1, 2, 3, 4]. The resulted output is depicted in Fig. 2(a)-solid [1, 2, 3, 4].

yet) 1+0

, ;'

(a)

U(t)

(b)

Figure 2. (a) Step response (dashed), Posicast response (solid). (b) Posicast command [1,2,3,4].

III. PROPOSED DESIGNS

The circuit alters the input pulse into scaled and a delayed section is called input pulse shaper or pulse pre­shaper. The first known circuit level pulse pre-shaper in CMOS technology is introduced and used by authors in [1, 2, 3].

The advantages of previously proposed design is that the generated Posicast pulse [1, 2, 3] were reasonably with sharp edges which in turn eases up controlling the Posicast pulse parameters, the pre-shaper senses the step input pulse in both rising and falling edges in a single integrated circuit. Also in regard to the properties of the mentioned delay and adder circuit, all of the rising and falling edges parameters such as different level of voltage and the time of voltage level can be adjusted with high accuracy, the very negligible delay in the generated Posicast pulse versus the input command pulse is another advantage of it. Also the simple and efficient transistor structure in adder unit yields to have accurate additions in very small fractions of time [I, 2, 3]. But the

310

previously design suffers from drawbacks. The most relevant problem is that effective parameters in Posicast pulse cannot be altered during the dynamic operation of the circuit for reconfigurable application purposes.

Our purpose in this paper is to propose reconfigurable designs for effective parameters modifications during the dynamic activity of the circuit. The four major parameters interested in this research are illustrated in Fig. 3. As shown in Fig. 3, horizontal Delay Parameters HOP (XI, X2), are the difference between the second level applying time and the first level applying time at rising and falling edges. Moreover, Vertical Voltage Parameters (VVP) (Yl, Y2), are the difference between the high level voltage and middle level voltage at rising edge and the difference between the middle level voltage and low level voltage at falling edge respectively. The primary target of this research is to have electronic circuit realizations for reconfigurable CMOS Posicast designs with digital input code words.

Y

J �1 X2

X1 Y2

x

Figure 3. Effective parameters in Posicast pulse.

The overall views of our previous and current works are illustrated in Fig. 4. As shown in Fig. 4(a) the system operates in a static way and there is no variable or reconfigurable parameter. This severely limits the application scope of the system in Fig. 4(a). In Fig. 4(b) the four variable parameters are depicted. These parameters are controlled by digital code words.

Previous work

(a) ...

III I

SL [;Jurwork JflL"': t :�� ,.._. �---p--- -.

-. ---- -�

Digital control word (b)

Figure 4. (a) Shaping step pulse to Posicast pulse in our previous work. (b) Shaping step pulse to Posicast pulse in this work.

Pulse delay is mainly divided into two different categories. Uniform Pulse Delay (UPD) and Non Uniform Pulse Delay (NUPD). In the UPD, as shown in Fig. Sea) the delays of rising and falling edges are both equal. This assumption simplifies the circuit realization by using pure delay elements in the signal path. In the Posicast pulse, difference between the second level applying time and first level applying time at rising edge (Xl in Fig. 3) is not equal with the difference between the second level applying time and first level applying time at falling edge (X2 in Fig. 3). Therefore, as shown in Fig. S(b), it is required that delays at rising and falling edges are not equal at all.

-T1

(a)

-T1

-T1

(b)

-T2

Figure 5. (a) Equal delays at rising and falling edges. (b) Non-equal delays at rising and falling edges.

Block diagram and circuits that the amount of delay at rising and falling edge is controlled with one set of input digital code word, and the amplitude of voltage of first level at rising and falling edge is controlled with one set of input digital code word too, is presented in Ref [S]. Also the full block diagram of proposed pre-shaper is presented in Ref [S].

A. Digitally controlled delay and adder elements

A Digitally controlled delay element is a delay system that delay controlled by digital code words. It is required to have linear delay variations with progressive code word. Since, Xl and X2 in Posicast pulse are not equal Thus, it is required that the delays of rising and falling edges are controlled with different codes. The delay circuit based on the modified design of delay circuit in Ref [6, 7] is presented in Fig. 6.

VDD

M1 �

Inp�

� M4

Figure 6. Proposed delay circuit with modification on Ref [6,7] .

As seen in Fig. 6, delay at rising edge is defined with pO­p IS code word and delay at falling edge is defined with nO-

311

n IS code word. So, amount of delay at rising and falling edge is controlled with different code words and we can have different delay at rising and falling edge. The inputs of the MpO-MpIS transistors (PO-piS) are the outputs of the one decoder, when the input digital code changes, the output of the decoder also changes. So, ON transistor is changed. Since, the sizing (W/L) of the MpO-MpIS transistors are different, and then the value of the equivalent resistance in the path of C capacitor is changed and finally the value of the X2 in Fig. 3 changes. Also, the inputs of the MnO-MnIS transistors (nO-nlS) are the outputs of the one decoder, when the input digital code changes, the output of the decoder also changes and ON transistor is changed. Since, the sizing (W/L) of the MnO- MnlS transistors are different and then the value of the equivalent resistance in the path of C capacitor is changed and finally the value of the X I in Fig. 3 changes.

The adder circuit that the YI and Y2 are controlled with different code words is presented in Fig. 7.

L

VDD

J In-l bM11 IDelayed-11lj M21

m 1--1 � m2-1 Mm1_--=c=t-_�'-'-J

(8)

Delayed-Irlj

---t-------rC::::I.c n 1--1 � n2-1

Mn1_--=c=t-_�-'-J

(b)

In Delayed-I n::[)r-------(>o�

R2

(c) -

(d)

Figure 7. Proposed adder circuit.

Ry2

The structure which shown in Fig. 7(a) generates the first level of Posicast pulse at rising edge. In this structure, the inputs of the Mmi-MmiS transistors (mi-mIS) are the outputs of the one thermometric decoder, when the input digital code changes, the output of the thermometric decoder also changes. Thus, the number of ON transistors are

changed and then the value of the output resistor is changed and finally the amplitude of first level at rising edge changes. So, the difference between the high level and first level at the rising edge (Yl in Fig. 3) is adjustable. The structure which shown in Fig. 7(b) generates the first level of Posicast pulse at falling edge. In this structure, the inputs of the Mn 1-Mn 15 transistors (n I-n 15) are the outputs of the one thermometric decoder, when the input digital code changes, the output of the thermometric decoder also changes. Thus, the number of the ON transistors is changed and then the value of the output resistor is changed and finally the amplitude of first level at falling edge changes. Therefore, the first level at falling edge (Y2 in Fig. 3) is adjustable. The structure which shown in Fig. 7( c) generates high level of Posicast pulse. Supply voltage of inverter in this structure is 1 v. As seen in Fig. 7(d), three produced pulse by above structure will add by one ideal Op-Amp.

IV. SIMULATION RESULTS

All the simulations are prepared using O.ISu CMOS technology with HSPICE.

The simulation results of delay circuit are depicted in Fig. S. As seen the proposed circuit works in good linearity respect to the code word.

-"'-� o .c

------.......... --................ ------

Low To High Delay --_. High To Low Delay

0; 1.5 ----j' a

f-

�

-----------------........ 0.5

Q.5

0C------;-, --------;;"c--------;, Rise Input Code/Fall lnput Code

Figure 8, Delay of rising and falling time of proposed delay circuit

Good linearity of Yl, Y2 for the proposed adder circuit respect to the code word is depicted in Fig. 9.

r=Yil l:::-'sJ

Q.20C-----O-, --------;;;,,------;,g: Y1 Input CodeIY2 Input Code

Figure 9, Linearity of YI and Y2 for the proposed adder circuit

312

The output pulses (Posicast pulse) of the proposed circuit are shown in Fig. 10.

:Eo.s

:E 0.5

t(sl ,.,

I Voul fo, 0-15 Ill. cod. word I

":1. �-----:±:---�---:2;::=-"" I '�.""." '''''�-- I I � 900n 910n 1(1' 'dl

Figure 10, Output pulse of proposed circuit (a) Xl variations, (b) X2 variations, (c) Y l variations, (d) Y2 variations,

V. ApPLYING PROPOSED POSICAST PULSE ON OP-AMP

The block diagram and schematic of an Op-Amp is presented in Fig. 11.

Vinput ZP-Amp

(8)

Vaul

VDD

(b) Figure II, (a) Block diagram of an Op-Amp with negative feedback, (b)

Schematic of a two-stage CMOS Op-Amp,

As seen in Fig. 12, the step response of Op-Amp has oscillation at rising and falling edges. The overshoot and settling time at rising edge is 57% and 95ns, respectively. Also the overshoot at falling edge is 42% and settling time at falling edge is 63ns. To omit the oscillation, generated Posicast pulse by proposed pre-shaper is applied on Op­Amp. The Posicast pulse and the Op-Amp's response to Posicast pulse, is depicted in Fig. 13.

2 Rising edge:

1.5 r\ Overshoot=57% 1\ Settling tlme=95ns I r Falling edge:

1 Overshoot=42%

� \1

I Settling time=63ns

0.5 \ I 1--- 51eplnput ,I \ {\ 0 - - - - Step Response

i! \

-0.55OOn 600n 700n 800n 900n lu 1.1u 1.2u tIs)

Figure 12. Step response of CMOS Op-Amp.

2

1.5 Rising edge:

Qvershoot=S"

Settling time=41ns

1 Failing edge:

[\ Overshoot=1,*,

:E Settling time=12ns

0.5

0 1--- Posie.sl Pulse , I

.....••••..••. Poslcast Response

-0.5 500n 600n 700n 800n 900n lu 1.lu 1.2u

tIs)

Figure 13. Posicast response of CMOS Op-Amp

The results of simulating the step response and Posicast response of Op-Amp are presented in TABLE I.

TABLE!. SIMULATION RESULTS OF THE PROPOSED POSICAST FOR AN OP-AMP.

Input Type Overshoot Improvement Settling Improvement time Rising

57% - 95ns -

Step edge

Falling edge

42% - 63ns -

Rising 5% 91.23% 41ns 56.85%

Posicast edge

Falling 1% 97.62% 12ns 80.96%

edge

As seen in TABLE I the improvement of overshoot at rising edge is 91.23% and at falling edge is 97.62% and the improvement of settling time at rising edge is 56.85% and at falling edge is 80.96%.

VI. CONCLUSIONS

This paper presented a new programmable and fast reconfigurable pre-shaper for Posicast pulse generation unit. In this plane, for Posicast pulse generation, first the input pulse is delayed and then the main pulse and delay pulse is adding. The amount of delay of proposed delay circuit, and amplitude of voltage levels in the presented adder circuit, are controlled with input control code, our experimental results showed that the proposed delay and adder circuits work in good linearity respect to the code word. Finally, the proposed

313

plane has been applied on CMOS Op-Amp. In Op-Amp, the overshoot is reduced at rising edge from 57% to 5% and at falling edge from 42% to 1 %. Also, the settling time is reduced from 95ns to 41 ns and from 63ns to 12ns at rising and falling edges respectively.

REFERENCES

[I] M. Rasoulzadeh, M.B Ghaznavi-Ghoushchi, "A Novel Method for Oscillation Canceling of CMOS Opeational Amplifires Using Posicast," SoC Design Conference, 2010, pp. 408 - 411.

[2] M. Rasoulzadeh, M.B. Ghaznavi-Ghoushchi, "Oscillation controlled electronic systems design using Posicast-based pulse pre-shaping," IEEE International Midwest Symposium on circuits and systems, 2009, pp. 24 - 28.

[3] M. Rasoulzadeh, M.B. Ghaznavi-Ghoushchi, "Design and Implementation of a CMOS Posicast Pre-Shaper For Vibration Reduction of Op-Amps," Proceeding of the World Congress on Engineering and Computer Science 2009.

[4] 1. Hung, "Posicast Control Past and Present," IEEE Multi disciplinary Engineering Education Magazine, vol. 2, no. 1,2007.

[5] M. Rahimi, M.B. Ghaznavi-Ghoushchi, "Reconfigurable CMOS Posicast for control and reduction of Overshoot in electronic circuits," submitted to the international journal of circuit theory and applications, October 20 II.

[6] 1. Dunning, G. Garcia, 1. Lundberg, E. Nuckolls, "An all-digital phase-locked loop with 50-cycle lock time suitable for highperformance microprocessors," IEEE Journal of Solid-State Circuits, vol. 30, no. 4, Apr 1995, pp. 412 - 422.

[7] M. Saint-Laurent, G. P. Muyshondt, "A Digitally Controlled Oscillator Constructed Using Adjustable Resistor," IEEE Southwest Symposium on Mixed- Signal Design, 2001, pp. 80-82.