RF Model of a Back-Gated Graphene Field EffectTransistor

Xuan Anh Nghiem∗, Bernat Terres,†, Christoph Stampfer†, Renato Negra∗∗Mixed-Signal CMOS Circuit Design, RWTH Aachen University, 52074 Aachen, Germany†JARA-FIT and II. Institute of Physics B, RWTH Aachen University, 52074 Aachen and

Peter Grunberg Institute (PGI-9), Forschungszentrum Julich, 52428 Julich, Germany

Email: nghiem@umic.rwth-aachen.de

Abstract—This paper presents the RF characterization andmodeling of a back-gated graphene field effect transistor (GFET)embedded in a coplanar waveguide (CPW). The electromagneticmodel (EM) of the graphene structure includes both channeland metal/graphene contact resistances as well as all involvedparasitic capacitances. The S-parameters of the resulting struc-tures have been measured at room temperature in the frequencyrange from 10 MHz to 67 GHz for back-gate voltages upto 37 V. Measurements show a roughly back-gate independentcontact resistance (∼ 900 Ωμm) and a highly rise in channelresistance from 20 Ω to 2.34 kΩ when increasing the back-gatevoltage from 0 V to 37 V (Dirac point). Moreover, the associatedcapacitance decreases from 4.1 fF to 0.7 fF for the same voltagerange. The simulation results of the electromagnetic model fromthe CPW together with the graphene structure are in reasonablewell agreement with our measurements.

I. INTRODUCTION

Graphene is a two dimensional planar sheet of sp2-bondedcarbon atoms in a honeycomb crystal lattice configuration.

Although bulk graphene shows no energy band-gap, making

it unsuitable for digital applications, this allotrope of car-

bon exhibits extremely attractive electrical properties. A high

intrinsic carrier mobility of around (200, 000 cm2V−1s−1),

a mean free path at room temperature close to 400 nm[1] and a high saturation velocity of ∼5.5×107 cm s−1 [2]

places graphene among the promising candidates for future

microwave nanoelectronic materials.

Since its discovery [3] graphene has attracted great attention

from the electron-device community. This interest comes not

only from its outstanding charge carrier mobility but mainly

from the possibility of downscaling the length of the GFET

channel without encountering most of the unwanted short

channel effects [4]. Threshold-voltage roll-off, drain-induced

barrier lowering or impaired drain-current saturation effects

are the key limiting factors for high frequency applications.

Thanks to its extremely thin conducting channel, of only

one-atom thick, it is possible to dramatically scale down

the length of the GFET channel and therefore obtain higher

cutoff frequencies. Recently, GFETs with a cutoff frequency

of 100 GHz have been reported [5].

A number of works on GFET with either back or top-

gated devices have been published [5]–[8], [10]. However,

apart from its small-signal model [8]–[10], no equivalent

circuit model for GFETs has been discussed before. The role

Fig. 1: a) and b) optical microscope images of the back-gated

GFET device. c) schematic illustration of the GFET on top of

the Si substrate. d) Raman spectrum of the graphene channel.

The presence of a single Lorentzian peak in the 2D-band

proves the single-layer nature of the graphene.

of an EM model is essential for nonlinear microwave and

RF circuits where simulations of more complex electronic

circuitry become essential during the design stage. This paper

introduces the RF model of a GFET considering both channel

and graphene/metal contact resistances as well as all parasitic

capacitances. These results are crucial for the design and

fabrication of hybrid graphene/metal radio frequency devices

where graphene can be embedded to cover specific demands.

II. DEVICE FABRICATION

Samples were fabricated from graphene that was mechani-

cally exfoliated from natural bulk graphite and deposited onto

a highly resistive Silicon substrate with a 285 nm SiO2 layer

on top. The single-layer nature of graphene was identified by

optical contrast under the optical microscope and characterized

by Raman spectroscopy (Fig. 1). Electron-beam (e-beam)

lithography was used to pattern the etch mask (≈ 110 nm

e-beam resist). A reactive ion-based etching process on an

Ar/O2 plasma atmosphere was employed to carve unprotected

graphene and a final e-beam lithography step was used prior

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Fig. 2: GFET transfer characteristic curve showing the source-

drain current Isd as a function of back-gate voltage Vbg .

Curve shows a minimum Ids,min at approximately 37 V which

corresponds to the charge neutrality point of graphene.

to the metallization of the CPW structure with a 50/950 nmCr/Au stack. Optical microscope images of the resulting

structures can be observed in Fig. 1.

The CPW inner conductor has a width of 7.6 μm and

both ground conductors, placed symmetrically 7.7 μm away

from the inner conductor, have a width of 30 μm. The etched

graphene flake has a length, or separation between drain and

source contacts, of L = 3.36 μm and a width of W = 2.7 μm.

The CPW was designed to provide good matching with the

100 μm pitch Ground-Signal-Ground (GSG) patches required

for the on-wafer measurements. The whole Si substrate was

conductively glued on the copper cladding side of a FR4

substrate connecting the Si back-gate of the GFET device with

the FR4 substrate.

Additionally, a reference 70 Ω CPW with the same di-

mensions but without the graphene channel, i.e. with short-

circuited drain and source contacts, was fabricated on the

same Si substrate. This reference sample was used during

the through-reflect-line (TRL) calibration and was essential

to extract the contributions of the fixture structure. These de-

embedding techniques were required in order to resolve the

RF equivalent circuit of the GFET structure.

III. MEASUREMENT AND RF MODELLING OF THE

GRAPHENE CHANNEL AND THE METAL/GRAPHENE

CONTACTS

A. Device measurements and substrate parameters extraction

The DC measurements were carried out with an Agilent

N6705A Power Analyzer. Fig. 2 shows the transfer characteris-

tics curve (source-drain current Ids vs. back-gate voltage Vbg)

of the GFET device. During the measurements, the source-

drain voltage Vsd was set to 20 mV while sweeping the Vbg

from 0 V to 40 V. The transfer characteristics curve shows

a bipolar behavior with a charge neutrality point (Ids,min)

shifted towards 37 V. This observed p-doping is most likely

due to EBL resist residues and it is the responsible for hiding

the expected V-shaped trace characteristic of graphene.

Fig. 3: Measured S21 as a function of frequency (10 MHz -

67 GHz) for different back-gate voltage Vbg .

For the HF characterization, samples were measured using

an on-wafer Karl-Suss PM8 probe station coupled to an

Agilent N5247A PNA-X Microwave Network Analyzer. An

impedance standard substrate (ISS) from Cascade Microtech

was used during the calibration of the system following

Short-Open-Load-Thru (SOLT) calibration technique. The S-parameters of the GFET as a function of back-gate voltage

(0 V-37 V) are shown in Fig. 3. By comparing the EM

simulations with the measurements of the reference CPW, the

electrical parameters of the silicon substrate were extracted.

Consequently, the results have shown the best fit between

simulations and measurements for a silicon having a relative

permittivity of ε = 11.9 and a resistivity of 40 kΩ · cm. The

285 nm SiO2 layer having a relative permittivity of ε = 3.9and a loss tangent of δ = 0.004 was used in the simulations.

B. Model for the graphene/metal contact and the graphenechannel

In order to get an accurate EM model of the embedded

GFET, the reference CPW sample was modeled including

the contributions of the FR4 substrate. This FR4 substrate

consist of an insulating layer of 1.4 mm covered with a

copper sheet of 35 μm thick. During the co-simulation, the

EM model of the reference CPW and the lumped model of the

GFET-embedded CPW were respectively compared to the S-

parameters measurements for a frequency range from 10 MHzto 67 GHz.The lumped model of the GFET consists of two

graphene/metal contacts (source and drain contacts), which

have only resistive components Rct, in series with the model of

the graphene channel. This graphene channel itself has been

modeled as a voltage-controlled resistor Rg with a parallel

parasitic capacitors Cp. The Cp capacitance embodies the

discontinuity of the metal/graphene transition and the big dif-

ference in thickness between the CPW metal layer (1 μm) and

the graphene (∼ 0.34 nm). The gap distance between source

and drain contacts and other possible graphene capacitances

are included in Cg . The complete lumped model is presented

in Fig. 4.

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RctRct

Cg

CpCp

Rg

S D

Fig. 4: Lumped-element circuit model of the device channel

and contacts including parasitic components.

Simulation

Simulation

Measurement

Measurement

Fig. 5: Simulation vs. measurement of S-parameters for twocases Vbg = 0 V and 37 V.

The co-simulations were performed using the tuning fea-

tures of ADS software. Measured and simulated S-parameters

were fitted for all back-gate voltages. Fig. 5 shows the fitting

for Vbg = 0 V and Vbg = 37 V. The values of the differ-

ent components included in the lumped circuit model were

extracted as a function of Vbg . Fig. 6 shows the graphene

channel resistance, Rg , and the associated capacitance, Cg , as

functions of back-gate voltage Vbg =. As shown in the figure,the channel resistance Rg increases linearly with the back-

gate voltage Vbg from 0 V to 25 V and increases exponentially

when back-gate voltage approaches the charge neutrality point

(Dirac point) at Vbg 37 V. Moreover, the gap and the graphene

capacitance, Cg , decreases linearly with an increase in back-

gate voltage. As expected, the parallel parasitic capacitances,

Cp, are back-gate voltage independent and have a value of

5.1 fF.The model also indicates that the metal(Cr/Au)/graphene

contact resistance is not influenced by the back-gate voltage

and has a resistance value of ∼330 Ω, that is a resistivity

of ∼890 Ωμm. This value is in good agreement with early

reported contact resistance of about ∼800±200 Ωμm [11].

IV. CONCLUSION

In this paper, an RF model of the channel and contacts of a

back-gated GFET was introduced. The method of modelling

based on the co-simulation of EM and channel/contact equiva-

lent circuit models. The results show that the graphene channel

Fig. 6: Extracted graphene channel resistance and its associ-

ated capacitance as functions of applied back-gate voltage.

resistance and the associated capacitance changed with back-

gate voltages while the metal(Cr/Au)/graphene contact remains

unchanged and corresponds to a resistivity of ∼890 Ωμm. In

the p-doped region, as the gate voltage increases from 0 Vto 37 V, the graphene channel resistance (Rg) increases from

20 Ω to 2.34 kΩ and the associated capacitance (Cg) deceases

from 4.1 fF to 0.7 fF. The model provides insights into the

behavior of the back-gated GFET and paves the way for the

next generation top-gated GFET modelling.

ACKNOWLEDGMENT

This work has been supported by JARA-FIT, the UMIC Re-

search Centre, RWTH Aachen University, the the Vietnamese

Ministry of Education and Training (MOET) via 322 project

and German Academic Exchange Service (DAAD).

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