Sonoma State UniversityRohnert Park, California 94928–3609Email: [email protected]
Abstract— This paper proposes a technique to analyze dis-tortion in analog CMOS integrated circuits. The proposedtechnique captures a transistor’s nonlinearity using a two-dimensional Taylor series with coefficients that depend on thetransconductance-to-current ratio (gm/ID) of a transistor. Toexplore the effectiveness of the proposed technique, a common-source amplifier is designed. The harmonics of the amplifierare calculated using both the gm/ID technique and Cadence’speriodic steady state (PSS) analysis over a wide range of gm/ID .The results indicate a close match (i.e. a discrepancy less than 2dB from gm/ID=8 to 30) and show that the proposed techniquecan indeed be incorporated in a gm/ID design flow.
I. INTRODUCTION
gm/ID design methodology is a powerful technique thatallows designers to quickly size up transistors. The gm/IDdesign methodology was originally proposed in [2]- [3] andextended to incorporate noise analysis in [4]. A survey of thepublished literature indicates that there is no prior publicationon gm/ID based distortion analysis. This paper describes aprocedure to include distortion as part of the gm/ID designflow. Section II describes the underlying principles of gm/IDdesign flow, introduces a two-dimensional Taylor series ap-proximation, and describes means of obtaining gm/ID basedTaylor series coefficients. Section III analyzes the distortionof a common-source amplifier as a means to compare gm/IDbased design to Cadence simulation. Section IV describes thelimitations of gm/ID based distortion analysis.
II. THEORY
A. Intuition of gm/ID Design Principle
Figure 1a shows a transistor which has a transconductance(gm), a drain-to-source conductance gds, and a current (I)when biased at a gate-to-source voltage (VGS) and a drain-to-source (VDS). If an identical device is connected in parallelso that both devices are biased at the same VGS and VDS ,both devices have the the same gm, gds and the same ID.Since the devices are connected in parallel, they can be treatedas one device with an aspect ratio of 2W/L. The effectivetransconductance over current ratio is gm/ID for both themerged device as well as the stand alone device because gmand ID are doubled. The drain-to-source transconductance isalso doubled for the merged device. As a result, the intrinsicgain (gm/gds) is identical for both the stand alone device and
the merged device. It can therefore be stated that as long astransistors are biased at the same gm/ID, they will have thesame gm/gds. This observation is true for two small signalparameters whose ratio depend solely on the gm/ID and noton the width of a transistor.
WL
VDI
VG
(a)
WL
WL
VD2I
VG
(b)
2WL
VD2I
VG
(c)
Fig. 1: Transistors biased at the same gm/ID
Once a transistor of a given width (W ) is characterizedover a range of gm/ID, the gm/ID based parameters canbe generalized to a transistor of an arbitrary width. gm/IDmethodology will hold as long as a parameter of interest scaleswith W [6].
B. Taylor Series
There are two types of nonlinear behaviors in circuits: hardnonlinearity and soft nonlinearity [5]. Hard nonlinearity ispresent when the input voltage becomes too large and clippingoccurs at the output. The distortion caused by hard nonlinearityis very large. Few applications can tolerate hard nonlinearity.This paper will instead focus on circuits that exhibit primarilycharacteristics of soft nonlinearity.
Devices that exhibit soft (weakly) nonlinear behavior canbe described by means of a power series. For a weaklynonlinear MOS transistor, the drain-to-source current (ids) isas a function of the gate-to-source voltage (vgs and the drain-to-source voltage (vds and can be written as the followingtwo-dimensional Taylor approximation [1]:
where the Taylor coefficients are derived from the derivativeof IDS :
gmk =1
k!
∂kIDS
∂V kGS
(2)
gdsk =1
k!
∂kIDS
∂V kDS
(3)
xpq =1
p!q!
∂p+qIDS
∂V pGS∂V
qDS
B (4)
gmk represents the derivatives of IDS with respect to VGS .The first derivative of IDS with respect to VGS (gm1) rep-resents the transconductance of the transistor. gm2 representsthe derivative of gm1 with respect to VGS . gdsk representsthe derivative of IDS with respect to VDS . gds1, in particular,represents the drain to source transconductance. It is inter-esting to note that ids depends not only on the powers ofvgs and vds, but also on cross-terms (i.e. x11, x12 and x21).The cross-term x11, for example, represents the dependenceon the transconductance on the drain-source bias voltage andcan become significant at high gm/ID. x12 and x21 are higherorder derivatives of x11.
C. Determination of Taylor Series Parameters
Transistors from IBM’s CMRF8SF 0.13 µm CMOS pro-cess are used because they have excellent model-hardwarecorrelation. The numerical values of gmk, gdsk and xpq areobtained from Cadence simulations (using the setup shownin Fig. 2) by approximating ∂kIDS/∂V
kGS by ∆kIDS/∆V
kGS ,
∂kIDS/∂VkDS by ∆kIDS/∆V
kDS ,and ∂p+qIDS/∂V
pGSV
qDS by
∆p+qIDS/∆VpGS∆V q
DS . It is important to choose ∆VDS and∆VGS carefully in order to obtain close approximation ofthe derivatives. The optimum value for ∆VGS and ∆VDS
is obtained by comparing harmonics calculated using Taylorseries approximation to harmonics obtained using Cadence’sPeriodic Steady State (PSS) analysis. ∆VGS = ∆VDS = 1mV is chosen. Table I shows gmk, gdsk and xpq for a 800nm transistor biased at VGS = 0.412V and VDS = 0.6V. Thewidth of the transistor is doubled in order to investigate Taylorcoefficients’ sensitivity to W . Table I shows that gmk, gdskand xpk are doubled with W is doubled, suggesting that gmk,
TABLE I: gm/ID-based Taylor coefficients.
Parameters WL
= 0.66µm0.8µm
WL
= 13.2µm0.8µm
gm1(A/V ) 0.831µ 1.681m
gm2(A/V 2) 1.311m 2.649m
gm3(A/V 3) -2.802m -5.660m
gds1(A/V ) 26.36µ 53.35µ
gds2(A/V2) -7.09µ -14.39µ
gds3(A/V3) 4.486µ 9.119µ
x11(A/V 2) 0.169m 0.342m
x12(A/V 3) -76.27µ -154.00µ
x21(A/V 3) 175.07µ 353.4µ
gdsk, and xpq are proportional to W . Consequently, a ratioformed by any two Taylor series coefficients (e.g. gm1/gds1) iswidth independent and depends only the gm/ID of a transistor.Distortion of a weakly nonlinear circuit can be approximatedusing the gm/ID technique as long as the Taylor series containenough terms.
III. DESIGN EXAMPLE
A. Distortion of a Common-Source Amplifier
The distortion of a common-source amplifier (shown in Fig.3) is analyzed in order to evaluate the accuracy of the pro-posed technique and to understand Taylor Series coefficients’dependence on gm/ID. The width (W ) and the gate-to-sourcevoltage (VGS) of the transistor are adjusted in order to maintaina bias current of 100 µA over a wide range of gm/ID. Using(1) and expressing vds in a Taylor series approximation of vgs,the drain-source vds can be expressed as [1]
vds = c1vgs + c2v2gs + c3v
3gs (5)
where c1, c2, c3, and RL are as follows:
c1 = −gm1RL (6)
c2 = −(gm2 + gds2c21 + x11c1)RL (7)
c3 = −(gm3 + gds3c31 + 2gds2c1c2
+x11c2 + x12c21 + x21c1)RL
(8)
RL = RD||1/gds1 (9)
A plot of the small signal gain (c1) versus gm/ID is shownin Fig. 4. Since gm/gds increases with gm/ID, c1 increaseswith gm/ID. The small signal gain of the amplifier c1 isimportant in the calculation of the harmonics because c2 andc3 also depend on c1 as well as the load resistance (RD).
Figure 5 shows a break-down of c2 in terms gm2, gds2,and x11. gds2 is not a significant contributer of c2 while gm2
and x11 are significant contributers to c2. Although not shownin Fig. 5, gm2 and x11c1 are opposite in phase. |gm2| and|x11c1| are equal at gm/ID = 5, resulting a null in c2 atgm/ID = 5. Both non-cross terms and cross terms contributeto c3 in (8). A break-down of c3 due to contributions from thenon-cross terms (e.g. gm3, gds3, and gds2) are shown in Fig. 6.
62
−+ VDDW
L
RD
−+vgs
−+VGS
Fig. 3: Common source amplifier.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30−5
0
5
10
15
20
25
Current Efficiency, gm/ID (S/A)
20
Lo
g10(c
1)(
dB
)
gm
/ID
CadenceVSB
=0.0 V
0.13 µ mVDS
=0.6 V, length=800 nm
Temperature=27 degrees
Fig. 4: The small signal gain (c1).
gds2 and gds3 do not contribute as much as gm3 to c3. Fig. 6shows that if a one-dimensional Taylor series expansion is usedas opposed to the two-dimensional Taylor series expansionemployed in this paper, c3 ≈ gm3RL. The presence of a nullin gm3 at gm/ID = 16 would falsely imply a null in c3.However, if gds3 and the cross terms are also included, thenthe null of c3 due to gm3 at gm/ID = 16 would disappear.A break-down of c3 due to the contributions from the crossterms (e.g. x11, x12, and x21) are shown in Fig 7. x21 andx11 are significant at high gm/ID. Figure 5 - Figure 6 reveala fundamental trade-off in analog circuits: while it is tempting
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 3010
−3
10−2
10−1
100
101
102
103
Current Efficiency, gm/ID (S/A)
(1/V
)
|c2|
|gm2
RL|
|gds2
c2
1R
L|
|x11
c1R
L|
VSB
=0.0 V
VDS
=0.6 V, length=800 nm
Temperature=27 degrees
Fig. 5: A break-down of c2 according to (7).
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 3010
−3
10−2
10−1
100
101
102
103
104
Current Efficiency, gm/ID (S/A)
(1/V
)
|c3|
|gm3
RL|
|gds3
c3
1R
L|
|2gds2
c1c
2R
L|
VSB
=0.0 V
VDS
=0.6 V, length=800 nm
Temperature=27 degrees
Fig. 6: A break-down of c3 due to non-cross terms accordingto (8).
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 3010
−3
10−2
10−1
100
101
102
103
104
Current Efficiency, gm/ID (S/A)
(1/V
)
|c3|
|x11
c2R
L|
|x12
c2
1R
L|
|x21
c1R
L|
VSB
=0.0 V
VDS
=0.6 V, length=800 nm
Temperature=27 degrees
Fig. 7: A break-down of c3 due to cross terms according to(8).
to bias a transistor at a low gm/ID to reduce distortion, it isdifficult to achieve a high small signal gain at a low gm/ID.Therefore, one must usually compromise in order to achievea balance between sufficient gain and linearity.
B. Harmonic Distortion of a Common Source Amplifier
The harmonics of the common-source amplifier will becalculated next from c1, c2 and c3. If vgs = vm cos(ω1t),it can be shown that vds is equal to
vds(t) =c2v
2m
2+ (c1vm +
3c3v3m
4) cos(ω1t)
+c2v
2m
2cos(2ω1t) +
c3v3m
4cos(ω1t)
(10)
The distortion due to the second harmonic and the thirdharmonic is as follows:
HD2(dB) = 20 log10(c2vm2c1
) (11)
HD3(dB) = 20 log10(c3v
2m
4c1) (12)
Figure 8 shows that the discrepancy is less than 1.75 dBbetween the gm/ID technique and the Cadence simulationfrom gm/ID =8 to 20. The gm/ID technique predicts a
63
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30−120
−110
−100
−90
−80
−70
−60
−50
Current Efficiency, gm/ID (S/A)
h2/h
1 (
dB
)
gm
/ID
CadenceVSB
=0.0 V
0.13 µ mVDS
=0.6 V, length=800 nm
Temperature=27 degrees
Fig. 8: Distortion due to the second harmonic.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30−130
−125
−120
−115
−110
−105
−100
Current Efficiency, gm/ID (S/A)
h3/h
1 (
dB
)
gm
/ID
CadenceVSB
=0.0 V
0.13 µ mVDS
=0.6 V, length=800 nm
Temperature=27 degrees
Fig. 9: Distortion due to the third harmonic.
null at gm/ID = 5 while the Cadence simulation predictsa null at gm/ID = 4. An examination of the data showsthat the discrepancy is unrelated to ∆VGS and ∆VDS usedto calculate the Taylor series coefficients. A better predictionof the null location can be obtained by incorporating higherorder terms in the Taylor series expansion. Figure 9 showsthat the discrepancy is less than 2 dB between the gm/IDtechnique and the Cadence simulation for gm/ID between 8to 20. An examination of the data suggests that the discrepancyat gm/ID = 24 can be further improved by reducing ∆VGS
and ∆VDS used to calculate the Taylor series coefficients.
IV. LIMITATIONS
A. Taylor Series Approximation
The drain current (ids) is approximated by a two-dimensional Taylor series. The approximation becomes lessaccurate as vgs increases in magnitude. Table II shows theamplitude of the first harmonic (h1), the second harmonic(h2), and the third harmonic (h3) of vds as vgs increasesin magnitude. The harmonics calculated using gm/ID basedparameters are compared against periodic steady state analy-sis(PSS) results generated using Cadence. h1 is proportionalto |Vgs|, h2 is proportional to |vgs|2, and h3 is proportional to|vgs|. The discrepancy between the third harmonic calculatedusing the gm/ID method and Cadence when vm is 1 µVcan be attributed to the error setting of the simulator. The
error tolerance of the PSS simulator needs to be adjustedwhen calculating harmonics with amplitude less than 1 fV.The default error tolerance settings are used in this paper. Thediscrepancy at vm = 100 mV shows the limitation of theTaylor series approximation as vm increases. With an inputsinusoid of 100 mV, the peak to peak of voltage of h1 isapproximately 0.947 V using the gm/ID technique and 0.89V using Cadence. The source-bulk voltage is zero for datashown in Table II. If VSB 6= 0V, then a three-dimensionalTaylor series expansion should be used model distortion dueto vsb .
B. Frequency DependenceThe two-dimensional Taylor series approximation ignores
any frequency dependence introduced by reactive elements.While this approach may be sufficient for low frequencycircuits, the approximation becomes less accurate as fre-quency increases. In high frequency circuits, the frequencydependence of reactive components can be calculated using aVolterra series as opposed to Taylor series expansion.
V. CONCLUSION
This paper describes a procedure to incorporate distortionanalysis in a gm/ID design flow. A two-dimensional Taylorseries approximation is used to model a transistor’s nonlin-earity. To explore the effectiveness of the proposed technique,harmonics of a common-source amplifier are analyzed. Theresults showed a close match between the gm/ID techniqueand Cadence’s PSS analysis, making it possible to incorporatethe proposed technique into the existing gm/ID design flow.
REFERENCES
[1] S. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta,Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling, IEEE J. Solid-State Circuits, Vol.43, No.6, NO.6, June 2008.
[2] F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based method-ology for the design of CMOS analog circuits and its application to thesynthesis of a Silicon-on-Insulator micropower OTA,” IEEE Journal ofSolid-State Circuits, vol. 31, No.9, pp. 1314-1319, September 1996.
[3] D. Flandre, A. Viviani, J. P. Eggermont, B.Gentinne, and P. G. A. Jespers,“Improved Synthesis of Gain-Boosted Regulated-Cascode CMOS StagesUsing Symbolic Analysis and gm/ID methodology,” IEEE Journal ofSolid-State Circuits, vol. 32, No.7, pp. 1006-1012, July 1996.
[4] Ou, J., “gm/ID based noise analysis for CMOS analog circuits,” Cir-cuits and Systems (MWSCAS), 2011 IEEE 54th International MidwestSymposium on, pp.1-4, 7-10 Aug. 2011.
[5] W. Sansen, “Analog Design Essentials”, Springer, 2008, ch. 18, pp. 521-522.
[6] C. Daigle, “A basic introduction to the gm/ID-based design methodol-ogy”, EE214 class notes, Stanford University.
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