2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

Quantum Capacitance: The Deciding Factor in Nanometre Regime for CNTFET

Sanjeet Kumar Sinhal, Saurabh Choudhury Department of Electrical Engineering,National Institute of Technology, Silchar,

e-mail: sanjeetksinha@gmail.com".saurabhI971@gmail.com2

Abstract- Carbon nanotube based FET devices are getting more and more importance today because of their high channel

mobility and improved gate capacitance versus voltage characteristics. In this paper we compare and analyse the effect

of gate capacitance on varying oxide thickness for silicon MOSTFET and CNTFET. It is seen that in nanometre regime

quantum capacitance plays the major role in deciding the gate

capacitance of a CNTFET and we find a favourable

characteristics of decreasing gate capacitance with the decrease

in the oxide thickness which is impossible to get in silicon MOSFET.

Keywords-MOSFET, CNTFET, oxide-thickness, quantum

capacitance, inversion layer capacitance

I. INTRODUCTION

Device scaling has been the driving force towards technological advancements. Dimension of individual devices in an integrated circuit followed Moore's law [I]. Today silicon based MOSFETS (Metal Oxide Transistor Field effect transistor) have technology sizes less than 60nm are common in the world of electronics. As the size become smaller, scaling the silicon MOSFET becomes increasingly harder. Further scaling has faced serious limits related to fabrication technology and device performances. This limits include quantum mechanical tunneling of carriers through the thin gate oxides, quantum mechanical tunneling of carriers from source to drain and from drain to body, control of the density and location of dopant atoms in the MOSFET channel and source drain region to provide high on off current ratio, the finite sub-threshold slope. Many solutions are proposed to overcome these limitations. Some solutions include modifications on the existing structures and technologies with a hope of extending their scalability. Other solutions involve using new materials and technologies to replace the existing silicon MOSFETs. Researchers currently focused on identifying alternatives which would enable continued improvement in the performance of electronics systems are high dielectric constsnt (High-K), metal gate electrode, double gate FET. High-K dielectric materials are useful for gate insulators as they can provide efficient charge injection into transistor channels and reduce direct tunnelling leakage currents. Nanoscaled alternatives to bulk silicon transistors are therefore being pursued. Ultrathin body devices such as FinFETs have received an increasing attention in recent years. The very large scale integration (VLSI) systems depends on silicon MOS

ISBN No. 978-1-4673-2048-1112/$3 1.00©20 12 IEEE

technology, Industry Technology Road Map has predicted that in the nano regimes, the expected high density will encounter substantial difficulties in terms of physical phenomena and technology limitations, possibly preventing the continued improvements in figures of merit, such as low power and high performance.

These limits can be overcome to some extent and facilitate further scaling down of device dimensions by modifying the channel material in the traditional MOSFET structure with a single carbon nanotube [2]. Despite all the challenges associated with scaling, silicon based semiconductor technology will continue to scale down in the future. However, research is progressing toward improving carrier transport in the transistor channel region [3]. One possible option is to use carbon nanotubes (CNTs) to realize high channel mobility devices

II. STRUCTURE OF A MOSFET AND CNTFET

A metal-oxide-semiconductor field-effect transistor (MOSFET) is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an oxide, such as silicon dioxide.

Oxide Dielectric

Constant

Sio2

Source Channel

Fig. l. Single Gate MOSFET

Electro Masses

In Silicon

Drain

A carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material

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2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

instead of bulk silicon in the traditional MOSFET structure. The exceptional electrical properties of carbon nanotubes arise from the unique electronic structure of graphene itself that can roll up and form a hollow cylinder.

Fig. 2. A schematic animations of a carbon nanotube that can be formed by roll ing up graphene

CNTFET uses CNT as their semiconducting channels. A single-wall CNT (SWCNT) consists of one cylinder only, and the simple manufacturing process of this device makes it very promising for alternative to MOSFET. Most single­walled nanotubes (SWNT) have a diameter of close to 1 nanometer, with a tube length that can be many millions of

times longer. The structure of a SWNT can be conceptualized by wrapping a one-atom-thick layer of graphite called graphene into a seamless cylinder.

An SWCNT can act as either a conductor or a semiconductor, depending on the angle of the atom arrangement along the tube. This is referred to as the chirality vector and is represented by the integer pair (n ,m). A simple method to determine if a CNT is metallic or semiconducting is to consider its indexes (n, m). The nanotube is metallic if n = m or n - m = 3i, where i is an integer. Otherwise, the tube is semiconducting . The diameter of the CNT can be calculated based on the following.

D eN T = .,f3a. a ..J nZ + m2. + mn 1:[.

where ao = 0.142 nm is the inter-atomic distance between each carbon atom and its neighbor. The I-V characteristics of the CNTFET are similar to MOSFET. The threshold voltage is defined as the voltage required to turn-on the transistor. The threshold voltage of the intrinsic CNT channel can be approximated to be of first order as the half band-gap is an inverse function of the diameter [4]. Similar to the traditional silicon device, the CNTFET also has four terminals. As shown in Fig. 3, the undoped semiconducting nanotubes are placed under the gate as channel region, while heavily doped CNT segments are placed between the gate and the source/drain to allow for a low series resistance in the ON-state [5]. As the gate potential increases, the device is electro-statically turned on or off via the gate. Although CNT's have unique properties such as stiffuess,

strength, and tenacity compared to other materials especially to silicon, but it still experiencing lack of technology for mass production and high production cost.

Intrinsic CNT , regions ,--....L...-L.---lL...-..L.-_ """ (under the glHe+-+-.

Heavily

Doped CNT

Segment for

SourcelDrain

Fig.3. Schematic diagram of a CNT transistor [4] Top view.

The gate-to-source voltage that generates the same reference current is taken as the threshold voltage for the transistor that has different chirality. CNTFETs provide a unique opportunity to control threshold voltage by changing the chirality vector, or the diameter of the CNT. Fig. 4 shows the threshold voltage of both P-CNTFET and N-CNTFET

obtained from simulation for various chirality vectors (various n for m = 0) [6].

O.�

� 0.4 I-w LL I- 0.2 z u

'0 co 0 � � "C -0.2 "0 � IJ) co � -0.4

-O.�

...

o Calculated Vth of PCNTFET

o Simulated Vth of PCNTFET

* Simulated Vth of NCNTFET

o Calculated Vth of NCNTFET

¢ 0 ------- :------

o ---.--:-- ------:---

1 LO----�1L2----�1L4-----1�6-----1�8�--� 20�--� 2L2� Chirality Vector n (with m=O)

Fig. 4. Threshold voltage of CNTFETs versus n (for m � 0) as reported in [6]

A synthesis process for fabricating SWCNTs with the desired (n, m) chirality structure has been proposed in [7]. The CNTFETs are particularly attractive due to possibility of near ballistic channel transport, easy application of high-k gate insulator and novel device physics. Although most of the work on CNTFETs has concentrated so far on their d.c. properties, the a.c. properties are technologically most relevant. Theoretically, it is predicted that a short nanotube operating in the ballistic regime, and the quantum capacitance limit should be able to provide gain in the THz range [8].

Comparison of CNTFET-based logic circuits to CMOS logic circuits is necessary to establish means of evaluation for performance metrics such as current density,

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2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

device switching speed, propagation delay through the gates, switching energy, operating temperature, cost. However, the technology is not sufficiently mature to enable meaningful comparisons as the positioning techniques must still evolve to enable high-yield volume manufacturing and contact technology must be improved to reduce the impact of contacts on circuit performance.

III. QUANTUM CAP ACIT ANCE

Quantum capacitance (C,Q) is associated with the properties

of channel material. The quantum capacitance first introduced by S. Luryi [9]. Since the density of state is finite in a semiconductor quantum well, the Fermi level needs to move up above the conduction band edge as the charge in the quantum well increases. This movement of Fermi level requires energy and this conceptually corresponds to quantum

capacitance. c,Q physically originates in the Fermi level (Ep) penetration into conduction band. A sketch of the conduction band diagram in strong inversion is shown in figure-5. The total gate capacitance can be expressed as a series of insulator

capacitance (C[ll'::) and inversion layer capacitance (C'['Il v) [10]. On the assumption that only the first electron sub band in the channel is occupied, the inversion layer capacitance can be represented as a series of the quantum capacitance (C,Q) and

the centroid capacitance (C"'$'Il c), The centroid capacitance is related to the finite average distance of the electron channel from the insulator/channel interface[II]. The insulator capacitance is inversely proportional to the insulator thickness. Ideally the inversion layer capacitance is much larger than the insulator capacitance in the strong inversion condition and gate capacitance approaches the insulator capacitance.

- - - - - - - - - - EF

� c Q

Metal Insulator

Fig. 5. Conduction band diagram in strong inversion

This ideal gate capacitance scaling does not hold for deeply scaled devices. As insulator thickness approaches the

nanometer range, the insulator capacitance becomes comparable to the inversion layer capacitance, which means that the quantum capacitance and the centroid capacitance start to impact the gate capacitance.

When centroid capacitance is not considered and assumed all charges to be located at the same position inside semiconductor layer, induced channel charge in a MOS structure actually needed to deliver an amount of energy equal

'Qs' 'Qs � to -- + - to the MOS, where Qs is total electron charge ct1U" 'B a'Q in channel. The first term is related to the required energy for the electric field in the oxide layer and the second term corresponds to the required energy in the semiconductor layer which occurs due to the finite density of state of the

semiconductor. Normally C[ll':: is much smaller than c,Q' so

the second term is considered negligible but as device scaling

approaches a few nanometer scale , C i'Il.:: becomes very comparable to or even bigger than c,Q ' and c,Q should be

considered carefully in these scaled down devices.

IV. SIMULATION

Simulation result of single gate MOSFET at different gate voltages for different oxide thickness at a constant drain voltage of 1 V and is shown in Table 1. It can be observed from the table that in single gate MOSFET as the oxide thickness goes down from l.5 nm to 0.7 nm the quantum capacitance increases significantly as the gate voltage increases from 0.5 V and above. This increment in quantum capacitance is observed up to a gate voltage of 1 V. Fig. 6 shows the bar diagram representation of quantum capacitance against gate voltage. It is also observed from the simulation that at a very low gate voltage such as 0 V and 0.083 V the value of quantum capacitance is same for all oxide thicknesses considered here.

TABLE I

Single Gate MOSFEr

At Drain Voltage = 1 (V)

Gate Quantum Capacitance (F/cm2)

Voltage Tox= Tox= Tox= Tox=

(V) O.7nm O.9nm 1.2nm 1.5nm

0 2.lOE-lO 2.lOE-lO 2.lOE-lO 2.lOE-lO 0.083333 3.58E-09 3.58E-09 3. 57E-09 3.57E-09 0.166667 6.00E-08 5.98E-08 5.95E-08 5.93E-08

0.25 8.31E-07 8.03E-07 7.65E-07 7.32E-07 0.333333 4.41E-06 4.01E-06 3. 56E-06 3.21E-06 0.416667 8.47E-06 7. 74E-06 6. 86E-06 6. 17E-06

0.5 1.08E-05 1.02E-05 9.25E-06 8.47E-06 0.583333 1.19E-05 1.15E-05 1.07E-05 1.00E-05 0.666667 1.24E-05 1.21E-05 1.16E-05 l.l1E-05

0.75 1.26E-05 1.25E-05 1.21E-05 1.17E-05 0.833333 1.27E-05 1. 26E-05 1.24E-05 1.21E-05 0.916667 1.28E-05 1. 27E-05 1. 26E-05 1.24E-05

1 1.28E-05 1. 27E-05 1. 27E-05 1.25E-05

In the result shown in Table I, the input parameters for single gate MOSFET such as body thickness (which is of silicon) is l.00E-08 m and insulator dielectric constant is 3.9

at 30011 K temperature are considered. The step gate voltage is considered for simulation is 0.083V, where the initial gate voltage is 0 V and the final gate voltage is 1 V. These considerations are same for all oxide thickness (0.7nm , 0.9nm,

226

2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

l.2nm, l.5nm). In bar diagram shown in Fig. 6 we considered only three range of gate voltages such as 0.66 V, 0.75 V and 1 V for all oxide thicknesses.

l.30E-OS

1.2SE-OS

1.20E-OS LISE-OS

1.10E-OS

LOSE-OS

1.00E-OS 0.7 nm 0.9 nm 1.2 nm 1.5 nm

0.66V

.0.7S V

.1V

Fig.6. Bar Diagram: Quantum Capacitance Vs Gate Voltage for different oxide thickness in MOSFET

Waveform representation of gate voltage Vs. quantum capacitance is shown in Fig. 7, through this waveform representation we can easily conclude that after decreasing the gate oxide thickness the quantum capacitance increases for the different gate voltages.

1.50E-OS

E 1.00E-OS v

....... .... a S.OOE-06

O.OOE+OO

Single Gate MOSFET

o Lf1 "! o

Lf1 Lf1 ......

ci r-: o

-- 0.7nm - 0.9nm

- 1.2nm - 1.Snm

Fig.7. Value of Quantum Capacitance Vs. Gate Voltage for different oxide thickness in MOSFET

Whereas in case of CNTFET under identical simulating condition as in case of single gate MOSFET we observe that as the oxide thickness goes down from l.5 nm to 0.7 nm the quantum capacitance decreases, when we apply gate voltage from 0.5 V and above . This change in quantum capacitance is observed up to gate voltage of 1 V, which is shown in Table 2 as well as in bar diagram in Fig. S.

In the result shown in Table 2, the input parameters for CNTFET such as nanotube diameter is 1.00E-09 m and

insulator dielectric constant is 3.9 at 3000 K temperature are considered. Here the step gate voltage is also considered for simulation is 0.OS3V, where as the initial gate voltage is 0 V and the final gate voltage is 1 V. These considerations are also same for all oxide thickness (0.7nm, 0.9nm, l.2nm, l.5nm).

In bar diagram shown in Fig.-S shows characteristics of oxide

thickness at different three gate voltages 0.66 V, 0.75 V and 1 V. The same characteristics are shown in Fig. 9 in waveform representation.

TABLE [[

CNTFEr

At Drain Voltage = 1 (V)

Gate Quantum Capacitance (F/cm)

Voltage

(V) 0

0.083333 0.166667

0.25 0.333333 0.416667

0.5 0.583333 0.666667

0.75 0.833333 0.916667

I

3.50E-12 3.00E-12 2.50E-12 2.00E-12 1.50E-12 1.00E-12 5.00E-13

O.OOE+OO

Tox=

O.7nm

1.37E-16 2.32E-15 3.88E-14 5.09E-13 2.30E-12 3.67E-12 3.37E-12 3.21E-12 2.74E-12 2.43E-12 2.24E-12 2.1IE-12 2.02E-12

Tox= Tox=

O.9nm 1.2nm

1.37E-16 1.37E-16 2.32E-15 2.32E-15 3.87E-14 3.86&14 4.96&13 4.82E-13 2.18E-12 2.04E-12 3.57E-12 3.42E-12 3.78E-12 3.82E-12 3.38E-12 3.56&12 2.91E-12 3.12E-12 2.56&12 2.74E-12 2.33E-12 2.47E-12 2.18E-12 2.29E-12 2.08E-12 2.16&12

Tox=

1.5nm

1.37E-16 2.32E-15 3.85E-14 4.70E-13 1.94E-12 3.20E-12 3.81E-12 3.67E-12 3.28E-12 2.89E-12 2.60E-12 2.39E-12 2.24E-12

.0.66 V

.0.75 V

.1V

0.7 nmO.9 nm1.2 nm1.5 nm

Fig.8. Bar Diagram: Quantum Capacitance Vs Gate Voltage for different oxide thickness in CNTFET

CNTFET

5.00E-12 - 4.00E-12 E 3.00E-12 �

!::. 2.00E-12 u 0 1.00E-12

-0.7nm - 0.9nm - 1.2nm

O.OOE+OO -1.5nm <:> <:>., <:>., <:>., ').

Fig.9. Value of Quantum Capacitance Vs. Gate Voltage for different oxide thickness in CNTFET

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2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

V. CONCLUSION

In this paper quantum capacitance versus gate voltage for different oxide thickness is discussed for single gate MOSFET and CNTFET and a brief comparison is given. Through result shown above, we can conclude that in nanoscale regime, CNTFET devices is advantageous over single gate MOSFET due to lesser and lesser quantum capacitance, while in single gate MOSFET the value of quantum capacitance goes on increasing which leads increased propagation delay and hence performance degradation.

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[3] S. Datta, et. aI., "85nm Gate Length Enhancement and Depletion mode InSb Quantum Well Transistors for Ultra High Speed and Very Low Power Digital Logic Applications," IEDM, Page(s): 783-786, Dec. 2005.

[4] J. Deng and H. -S. P.Wong, "A compact SPICE model for carbon- Nanotube field-effect transistors including nonidealities and its application-Part II: Full device model and circuit performance benchmarking," IEEE Trans. Electron Device, vol. 54, no. 12, pp. 3195-3205, Dec. 2007.

[5] J. Appenzeller, "Carbon nanotubes for high- performance electronics Progress and prospect, electronics Progress and prospect, 2008.

[6] Y. Ohno , S. Kishimoto, T. Mizutani, T. Okazaki, and H. Shinohara, "Chirality assignment of individual single-walled carbon nanotubes in Carbon nanotube field-effect transistors bymicro-photocurrent spectroscopy," Appl. Phys. Lett., vol. 84, no. 8, pp. 1368-1370, Feb. 2004.

[7] B. Wang, P. Poa, L. Wei, L. Li, Y. Yang, and Y. Chen, "(n,m) Selectivity of single-walled carbon nanotubes by different carbon precursors on Co- Mo catalysts," J. Amer. Chem Soc., vol. 129, no. 9,pp. 9014-9019,2007.

[8] Castro , L. C. et al. "Method for predicting feT for carbon nanotube FETs. " IEEE Trans. Nanotechnol.4, 699-704 (2005).

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[10] S. Takagi and A.Toriumi,"Quantitative understanding of inversion-layer capacitance in Si MOSFET's,"Electron Devices, IEEE Transactions on, vol.42, pp. 2125-2130, 1995.

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