A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic

Massimo Alioto*, Gaetano Palumbo**, Melita Pennisi** *DII - Università di Siena, Siena, Italy

and currently also with EECS – University of Michigan, Ann Arbor, USA **DIEEI – (Dipartimento di Ingegenria Elettrica Elettronica e Informatica)

Università di Catania, Italy malioto@dii.unisi.it, gaetano.palumbo@dieei.unict.it, mpennisi@diees.unict.it

Abstract—In this paper, a simple topology to reduce delay variations in domino logic gates is discussed. According to a previous analysis by the same authors, the feedback loop implemented by the keeper transistor and the output inverter gate is responsible for a delay variability increase, compared to static CMOS logic. The proposed strategy reduces the loop gain associated with this feedback loop, and hence its impact on delay variations. As a result, delay variations associated with the keeper insertion are lowered by approximately 50%, with no penalty in area, noise margin and nominal performance.

I. INTRODUCTION In nanometer technologies, intra-die process variations

determine large delay variations that represent a timing overhead that limits the potential performance improvements offered by Domino logic [1]-[9]. Recently, the effect of process variations on the delay of dynamic logic was investigated at the circuit level of abstraction by the same authors [10]. In particular, it was shown that Domino delay variability is typically doubled compared to the static logic counterparts, since [10]

- delay variations at the dynamic node (i.e., from input to node X in Fig. 1) is essentially the same as the overall delay variability (i.e., from input to OUT in Fig. 1);

- variations in the keeper transistor Mkp and the precharge transistor Mpre have negligible impact on delay variability at the dynamic node X.

Thus, the only remaining cause of variability increase compared to static CMOS logic is the positive feedback loop that is implemented by the keeper transistor and the output inverter in Fig. 1 [10]. Also, as will be shown in Section II, the delay variability associated with the feedback loop becomes more pronounced when scaling the technology, and hence needs to be reduced.

Until now, various circuit solutions have been proposed to limit the impact of process variations on Domino logic [11]-[15]. In particular, the approach in [11], [12] and [15] is based on the temporary reduction of the keeper strength (and hence of the already low noise margin) for a fraction of the clock cycle. The approach in [13] actively compensates only variations that are fully correlated in both NMOS and PMOS transistors (i.e., layout-dependent variations), while being ineffective against other important random variability components (e.g., Random Dopant Fluctuations) or variations

Fig. 1. Schematic of a Domino logic gate. that affect NMOS and PMOS transistors in different ways. Similarly, the work in [14] compensates only fully-correlated variations through a keeper with digitally programmable strength, and has a large overhead that is acceptable only when adopted in large regular structures like register files.

In this paper a simple keeper topology that replaces the standard PMOS keeper is adopted to reduce delay variations while keeping the same silicon area, delay and noise margin. This topology reduces the delay sensitivity to process variations by reducing the loop gain, under an appropriate sizing strategy discussed in Section III. The topology and the sizing strategy are then validated in Section IV.

II. DELAY VARIATIONS IN DOMINO LOGIC GATES The generic scheme of Domino logic gates is reported in

Fig. 1. In this figure, the ratio Kkeeper between the saturation current of the keeper and that of the PDN must be kept lower than unity to avoid an excessive delay increase, and typically ranges from 0.1 to 0.5 [11]. As was shown in [10], the delay variations in Domino logic are due to 1) process variability within the PDN, 2) the presence of the positive feedback loop implemented by the keeper and the inverter gate. Interestingly, the feedback loop in Fig. 1 is responsible for an increase in the delay variations even when transistors in the loop (i.e., keeper and inverter transistors) do not experience any variation.

As a starting point for a quantitative analysis, the delay standard deviation (mean value and variability) is summarized

in Table I (Table II) for various logic gates with different loads (expressed as multiple of the input capacitance Cinv,min of a minimum inverter) in 65 nm CMOS technology, assuming Kkeeper=0.1. From these tables, the delay variability σ/μ tends to decrease when increasing the fan-in, and decreases when increasing CL (mainly due to the mean value of delay increase, as the standard deviation increases only slightly). Table I also shows the percentage increase of the delay standard deviation due to the keeper insertion (i.e., compared to the reference case without keeper), as indicated in brackets. As discussed in [10], this increase is basically due to the presence of the keeper, or equivalently the associated feedback loop. The approach herein proposed is to reduce the amount of feedback in this feedback loop by reducing the loop gain, while keeping the same keeper strength (and hence noise margin, performance).

I. THE PROPOSED KEEPER TOPOLOGY The magnitude of the loop gain in Fig. 1 can be reduced by

TABLE I DELAY STANDARD DEVIATION (PS) IN DOMINO LOGIC WITH/WITHOUT

STANDARD KEEPER AND KEEPER IN FIG. 2 (65-nm TECHNOLOGY, KKEEPER=0.1, IN BRACKETS: PERCENTAGE INCREASE W.R.T. THE CASE WITHOUT KEEPER) σ (ps)

CL=Cinv,min CL=30Cinv,min Tradit. with

keeper

Tradit. without keeper

Prop. keeper

in Fig. 2

Tradit. with

keeper

Tradit. without keeper

Prop. keeper

in Fig. 2

BUF 1.86 (+62%)

1.15 (0%)

1.44 (+25%)

1.99 (+19%)

1.67 (0%)

1.84 (+10%)

NAND2 1.64 (+58%)

1.04 (0%)

1.33 (+28%)

1.87 (+33%)

1.41 (0%)

1.71 (+21%)

NAND3 1.23 (+26%)

0.98 (0%)

1.11 (+13%)

1.81 (+36%)

1.33 (0%)

1.65 (+24%)

NAND4 1.20 (+38%)

0.87 (0%)

1.01 (+16%)

1.72 (+37%)

1.26 (0%)

1.58 (+25%)

NOR2 1.87 (+59%)

1.18 (0%)

1.44 (+22%)

2.01 (+19%)

1.70 (0%)

1.85 (+9%)

NOR3 1.88 (+53%)

1.23 (0%)

1.44 (+17%)

2.03 (+18%)

1.71 (0%)

1.89 (+10%)

NOR4 1.94 (+54%)

1.26 (0%)

1.50 (+19%)

2.07 (+20%)

1.73 (0%)

1.93 (+11%)

NOR8 2.10 (+54%)

1.36 (0%)

1.62 (+19%)

2.19 (+21%)

1.82 (0%)

2.07 (+14%)

NOR16 2.03 (+28%)

1.59 (0%)

1.85 (+16%)

2.42 (+21%)

2.00 (0%)

2.36 (+18%)

NOR32 2.47 (+25%)

1.97 (0%)

2.23 (+13%)

2.83 (+18%)

2.40 (0%)

2.73 (+14%)

TABLE II

DELAY MEAN VALUE, STANDARD DEVIATION AND VARIABILITY IN DOMINO GATES WITH STANDARD KEEPER IN FIG. 1 (65-nm TECHNOLOGY, KKEEPER=0.1)

CL=Cinv,min CL=30Cinv,min

μ

(ps)

σ (from Table I)

(ps)

σ/μ (%)

μ

(ps)

σ (from Table I)

(ps)

σ/μ (%)

BUF 21.0 1.86 8.86 61.9 1.99 3.21 NAND2 28.4 1.64 5.77 63.8 1.87 2.93 NAND3 28.5 1.23 4.32 64.7 1.81 2.80 NAND4 30.0 1.20 4.00 70.2 1.72 2.61 NOR2 22.1 1.87 8.46 62.1 2.01 3.24 NOR3 23.1 1.88 8.14 63.4 2.03 3.20 NOR4 24.3 1.94 7.98 64.7 2.07 3.20 NOR8 28.4 2.10 7.39 70.2 2.19 3.12 NOR16 35.8 2.03 5.67 81.0 2.42 2.99 NOR32 49.6 2.47 4.98 100.7 2.83 2.81

reducing the keeper transconductance Gm,KEEPER (as usual, evaluated in saturation around the bias point corresponding to the inverter logic threshold, i.e. where input and output inverter voltages are equal). On the other hand, the keeper strength is assigned by the targeted noise margin-delay tradeoff. Hence, Gm,KEEPER must be reduced while keeping the same strength (i.e., same Kkeeper ratio) as the standard keeper in Fig. 1, in order to avoid any noise margin and delay penalty.

The simple keeper topology in Fig. 2 can be used to reduce Gm,KEEPER while maintaining the same keeper strength. In detail, the improved keeper is realized by splitting the original transistor keeper transistor Mkp into two transistors Mkp,1 and Mkp,2, where only Mkp,1 is driven by the inverter output. Instead, transistor Mkp,2 operates as an equivalent resistance

( )1

2,

−

⎥⎥⎦

⎤

⎢⎢⎣

⎡−⎟

⎠⎞

⎜⎝⎛≈ tpDD

kpOXp VV

LWCR μ (1)

that represents a source degeneration for the transistor Mkp1. Hence, the effective transconductance of the keeper is immediately found to be

RGG

Gkp

kp

Mm

Mm

effm

1

1

,

,

, 1+= (2)

where Gm,Mkp1 is the transconductance of Mkp,1. As desired, Gm,eff and hence the loop gain are reduced by a factor of (1+Gm,Mkp1R), compared to the standard keeper topology in Fig. 1 without Mkp,2.

At the same time, transistors Mkp,1 and Mkp,2 must be sized to minimize (2) while keeping the same strength, or equivalently by maintaining the Kkeeper ratio. Since these transistors are in series, this condition is simply met by setting the aspect ratio of Mkp,1 and Mkp,2 according to

( ) ( ) ( )kpkpkp WLWLWL /// 2,1, =+ (3)

where the subscript kp refers to the standard keeper in Fig. 1. As is well known, the keeper usually has a small driving capability and its transistor width Wkp is customarily set to the minimum value Wmin allowed by the technology, whereas its length Lkp is greater than minimum. Thus, in the gate with

PDN

CLK

CLK

IN1

IN2...

VDD

Mpre

OUTX

Mkp,2

Mkp,1

Fig. 2. Keeper topology to reduce delay variations.

modified keeper in Fig. 2, transistors Mkp,1 and Mkp,2 are sized with Wkp,1=Wkp,2=Wkp=Wmin and kpkpkp LLL =+ 2,1, . Now, we still have another degree of freedom in the Mkp,1 and Mkp,2 sizes that can be used to keep the loop gain as low as possible, or equivalently to keep Gm,Mkp1R as high as possible from (2). Since Gm,Mkp1R is proportional to Lkp,2 /Lkp,1, we have to size the channel length of transistors Mkp,1 and Mkp,2 so that1 Lkp,1=Lmin and Lkp,2=Lkp −Lmin. This sizing criterion combined with (3) permits to reduce the loop gain while maintaining the same Kkeeper ratio, thereby avoiding any penalty in terms of noise margin and performance.

It is worth noting that the considered keeper is very similar to the keeper based on a single transistor, and its layout is very simple, since it is the series of two transistors with minimum width. As the overall length Lkp,1+Lkp,2 is the same as the channel length Lkp of the original keeper, the increment in the silicon area is negligible.

II. VALIDATION To validate the proposed approach, various Domino logic

gates were simulated according to the simulation setup in [10] in 65-nm CMOS technology, keeping the PDN strength constant and changing the keeper sizes to vary Kkeeper.

We first considered Domino logic gates with Kkeeper assigned to 0.1, which is in the low side of the typical range and leads to a noise margin ranging from 300 to 350 mV for all logic gates and the standard keeper in Fig. 1. As an example, a noise margin of 340 mV for the inverter and 300 mV for the NAND3 gate were obtained with the appropriate sizes of the keeper in Fig. 2 that leads to Kkeeper=0.1 (i.e., Wkp,1/Lkp,1=0.12 μm/0.06 μm, Wkp,2/Lkp,2=0.12 μm/0.48 μm for the keeper in Fig. 4, and Wkp/Lkp=0.12 μm/0.54 μm for the standard keeper in Fig. 1). As expected, the nominal noise margin was confirmed to be consistently the same for both types of keeper with a difference of just a few percentage points. Also, the keeper in Fig. 2 was confirmed to keep the same noise margin variability as the traditional keeper (i.e., the proposed keeper and sizing strategy do not change the noise margin neither in nominal conditions, nor its variations).

Monte Carlo simulations with 2,000 runs were performed to evaluate the delay standard deviation. Numerical results for the proposed keeper are reported in Table I-III. Monte Carlo simulations accounted for the variation in the threshold voltage, mobility, gate oxide thickness, source/drain resistance and channel dimensions. Simulation results confirm that the mean value μ of the delay is basically the same for both the standard keeper in Fig. 1 and the proposed keeper in Fig. 2. This means that the proposed keeper does not introduce any speed penalty at nominal conditions.

In regard to the delay variability, the delay standard deviation and variability with the proposed keeper (see Table

1 This clearly holds in practical cases where Lkp≥2Lmin. In the uncommon case where Lkp<2Lmin, it is easily found that we must set Wkp1>WminLmin/(L-Lmin), Wkp2=Wmin and Lkp1=Lkp2=Lmin in order to satisfy (4) and maximize Gm,Mkp1R.

TABLE III DELAY VARIABILITY σ/μ IN DOMINO GATES WITH PROPOSED KEEPER IN FIG. 2

(65-nm TECHNOLOGY, KKEEPER=0.1) σ/μ (%)

for CL=Cinv,min σ/μ (%)

for CL=30Cinv,min BUF 6.73 2.97

NAND2 4.67 2.67 NAND3 3.84 2.54 NAND4 3.34 2.39 NOR2 6.45 2.96 NOR3 6.22 2.96 NOR4 6.13 2.96 NOR8 5.69 2.94 NOR16 5.14 2.91 NOR32 4.45 2.70

III) are consistently lower than those with the standard keeper (as found from Table II) for all logic gates, as expected. This is especially true in low fan-in gates and in the case of low capacitive load. Hence, the keeper in Fig. 2 under the developed sizing strategy is effective in reducing the delay variability increase associated with the feedback loop.

Although the above results were obtained assuming Kkeeper=0.1, they hold also for different values of Kkeeper. To show the influence of Kkeeper, the same Domino logic gates were also designed and simulated with Kkeeper widely ranging from 0.1 to 0.5. In regard to the mean value of the delay, a higher value of Kkeeper leads to a higher delay because of the increased current contention with the pull-down network. For example, all the gates loaded with Cinv,min (30Cinv,min) were found to be slowed down by 1 ps (4 ps) and 2 ps (8 ps) for Kkeeper=0.3 and Kkeeper=0.5, compared to the case with Kkeeper=0.1. Simulations also confirmed that the keeper in Fig. 2 does not introduce any delay and noise margin penalty at nominal conditions, regardless of the adopted Kkeeper.

Regarding the delay standard deviation, its percentage increase due to the insertion of the keeper with respect to the case without keeper is plotted in Fig. 5 (Fig. 6) versus Kkeeper for CL=Cinv,min (CL=30Cinv,min). From Figs. 5-6, the delay variation always increases for all logic gates when a stronger keeper (i.e., higher Kkeeper) is adopted, regardless of the adopted keeper. This is because a stronger keeper has a greater small-signal transconductance, hence the loop gain increases and hence delay variations are more pronounced. Again, the proposed keeper offers a considerable delay variability reduction over the standard keeper, regardless of the value of

0%

20%

40%

60%

80%

100%

120%

140%

0.1 0.3 0.5

σincrease (%

)

KkeeperBUF proposed keeper BUF standard keeperNAND2 proposed keeper NAND2 standard keeperNAND4 proposed keeper NAND4 standard keeper

(a)

0%

20%

40%

60%

80%

100%

120%

0.1 0.3 0.5

σincrease (%

)

KkeeperNOR2 proposed keeper NOR2 standard  keeper

NOR3 proposed keeper NOR3 standard  keeper

NOR4 proposed keeper NOR4 standard  keeper (b)

Fig. 3. Percentage increase of delay standard deviation of standard/proposed keeper w.r.t. case with no keeper vs. Kkeeper (CL=Cinv,min, 65-nm technology): (a) inverter and NAND; (b) NOR. Kkeeper. More quantitatively, the delay variability increase due to the insertion of the proposed keeper was found to be typically 50% lower than that obtained with the standard keeper in Fig. 1, regardless of the adopted value of Kkeeper.

III. CONCLUSION In this paper, a keeper topology which halves the delay

variability increase associated with the keeper insertion was introduced.

The approach is based on the reduction in the loop gain while keeping the same keeper ratio. Accordingly, the proposed keeper guarantees the same nominal noise margin and its variability as well. Hence, the reduced delay variability is achieved without penalizing the noise margin. Also, the proposed keeper keeps the same nominal performance as the Domino logic with standard keeper. The silicon area penalty introduced by the proposed approach is also negligible.

Extensive Monte Carlo simulations in commercial 65-nm CMOS were performed to validate the approach.

0%

20%

40%

60%

80%

100%

120%

0.1 0.3 0.5

σincrease (%

)

KkeeperBUF proposed keeper BUF standard keeper

NAND2 proposed keeper NAND2 standard keeper

NAND4 proposed keeper NAND4 standard keeper (a)

0%

20%

40%

60%

80%

100%

120%

0.1 0.3 0.5

σincrease (%

)

KkeeperNOR2 proposed keeper NOR2 standard  keeper

NOR3 proposed keeper NOR3 standard  keeper

NOR4 proposed keeper NOR4 standard  keeper (b)

Fig. 4. Percentage increase of delay standard deviation of standard/proposed keeper w.r.t. case with no keeper vs. Kkeeper (CL=30Cinv,min, 65-nm technology): (a) inverter and NAND; (b) NOR.

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