Design and Analysis of Leakage Current and Delay

for Double Gate MOSFET at 45nm in CMOS

Technology

Manorama I, Pavan Shrivastava2 and Shyam Akashe3

ITM University, Gwalior, India E-mail: Imanoramachauhan9@gmail.com;2shrivastavapavanOl@gmail.com ;

3shyam.akashe@yahoo.com

Abstract- In this paper, we present a comparative analysis of Double gate MOSFET (DG MOS) with the conventional bulk Si single gate MOSFET (SG MOS) by using Cadence Virtuoso simulation tool. In our observations leakage current (Iojj), delay are found to be reduced than those of the bulk Si single gate MOSFET, and the Double gate MOSFET gets same drive current based on VGS

as compared to single gate MOSFET and its short channel characteristics get improved. Double gate MOSFET is mainly suggested for low power and high performance application. Total power consumption of inverter, static, dynamic circuit and latch using of double gate shows that leakage current and delay reduced by a factor of over lOx, compared with bulk Si single gate device.

Keywords- Double Gate, 45nm technology, Short channel effect, Static and Dynamic circuit, Latch, Leakage current, delay.

I. INTRODUCTION

Silicon CMOS technology has emerged as the predominant technology in the semiconductor industry. The evolution of CMOS technology is controlled by the Moore's law, which asserts that the number of transistor on Integrated circuit doubles in every 18 months. The continuous scaling of CMOS technology, the progressive reduction of MOSFET dimensions, such as gate oxide thickness, junction depth and the doping densities. Due to the reduction in the channel length and in the gate oxide thickness, become arises more important issues that degrade the device performance in terms of the short channel effect and the leakage current [1] [8]. With a thinner gate oxide, more gate tunneling current arises. For gate oxide scaling at the low level Inm thickness, high K dielectric material are required to curtail severe gate leakage[5].

Double gate MOSFET has been generally recognized as one of the most promising device structure enabling MOSFET to be scaled under 45nm. Double gate device has a unique property of electrical coupling of the two gates, which leads to a better gate control over the channel thus reducing the leakage current, drain-induced barrier lowering effect (DIBL) and short-channel effect [2] [4].We took Vth model reflecting only DG nature and charged sharing term by considering barrier lowering as given by,

978-1-4673-4603-0112/$31.00 ©2012 IEEE

V = V + 21j/ + £5 + p 1- - ........ . qNhXde (Xlh) 1 Ih FB B W Cox Lc

DG device is characterized by the indicative reduction of CMOS circuit leakage. Low power DG circuit design, as correlate to bulk Si technology, reduces leakage current maintaining or even improving performance.

Source Drain

Figure I. DGnFET structure: Leff= effective channel length, toxf = front gate oxide thickness, toxb = back gate oxide thickness , tsi = Si film thickness.

II. THE BASIC DESIGN OF DOUBLE GATE DEVICES AT 45NM

The main idea of a double gate MOSFET (DG MOS) is to have a Si channel of very small width and to control the Si channel by applying gate contacts to both sides of the channel. Fig.l shows the cross section of DG nFET in which front and back gate are electrically coupled and effectively control the SCEs, resulting in reduced drain induced barrier lowering (DIBL) and improve sub-threshold swing (S) [5] [7].

302 Proceedings of 7th International Conference on Intelligent Systems and Control (ISCO 20J 3)

DC Response -/NM1/D -/NMO/D -/NM2/D

150.0-,-------,-------,------,-------,-------,--------,

125.0t---t------t------t----t----:::==t�======1

100.0+---+---+----+�,.L_--+---+-----1

75.0+---+---+---r-r-+----+---+-----1

50.0_t_--+-----trf---+---t----+---I

25.0+---+--+1-+----+----+---+-----1

-25.0+_--+---+----+----+---+-----1 0.0 10 1.5 Vgs 01)

2.0

Fig: 2(a) at Vdd=O.4

2.5 ,.0

1

DC Response

-/NM1/D - /NMO/D -/NM2/D

250-,--------,-------,------,----,--------,--------,

200+----+----+-----1---+----+-=--=1

150+----+----+-----1-7"'----:>+----+----1

100+----+----+--+---A---+----+----I

50.0_t_--+_-�L_b_"----___t---_t_--+_--_I

-50.0+_--+_�--+--_I---+_-�+_--_I 0.0 1.0 1.5

Vgs 01) 2.0

Fig: 2(b) at Vdd=0.7

2.5 ,.0

Figure 2. Cadence virtuoso tool predict Ids-Vgs characteristics at Vds= 0.4, 0.7 for 45nm bulk Si and DO nFETs. Dredesigned with Leff=45nm, toxf = toxb = 2.2nm, tsi = 8nm.

In the double gate technology the front gate and back gate are electrically coupled , it is most suitable for low power circuits by reducing standby power even with an increase in performance. Here, we design symmetrical DGnFET with Leff = 45nm, toxf = toxb = 2.2nm, tsi = 8nm. In this study, we observed that Ioff» IG due to the relatively thicker oxide for extremely short Leff is used to mitigate gate/oxide tunneling current. In the double gate device the body is lightly doped because of it the reverse/forward bias source/drain-to-body junction and trap assisted tunneling currents are imperceptibly small [8] [9].

III. THE ANAL YS[S OF CMOS CIRCUlTS

We examine in specific leakage current and delay for inverter, distinctive static and dynamic CMOS circuits, and latches with 45nm DG devices, equate with bulk Si devices.

A. CMOS Inverter

Fig: 3 Shows delay versus Vdd for unload inverter with fluctuate VDD = (0.7, 0.8, 0.9 and 1.0) for 45nm bulk device and DG devices as obtained from cadence virtuoso tool. In the calculation for delay at the different Vdd, the delay is reduced in the device up to 25% as compared to the bulk SG device. Hence, the speed of DG device is improved as compared to the bulk Si device.

For Vdd= 0.7v, DG device is faster by 25%. Lower Vt would grow performance and noise margin for the circuits such as that pass gate, stack devices and SRAM read / write access transistor where device use substantial procedures of time in linear operation during switching transient [13].

400 350

'2.- 0 � 0 g 0

100 50

o 0.7 0.8 0.9 1

VDD

Figure 3. Delay versus VDD for unload inverter ring oscillator with bulk Si and DO devices designed for equal delay or equal Ioff at vdd=0.7v DO CMOS

device design trade off performance and power is indicated

Fig: 4 Display virtuoso tool intimate Ioff at VDD=0.7v versus Leff for bulk Si and DG CMOS inverter which yield the equal delay for Leff= 45nm. As in the graph Leff is deposit from 45nm to 60nm. As we scale the Leff from 45 to 60nm, we noticed that the Ioff in DG Inverter is 50% fewer as compared to the SG Inverter. Ioff reduction is noticeably increased as Leff is scaled due to much less SCEs.

Fig: 5 Display Ioff versus temperature (T) for bulk Si and DG inverter. In CMOS circuits Ioff current doubles in every 100C rise in temperature. But in the double gate circuit the Ioff is lower as compared to the bulk Si circuit. Ioff is lower in DG device by approx 50-70x and as the temperature increases, the alteration becomes more distinguishable. It is to be correspondence that Ioff for DG devices are much less sensitive to temperature deviation due to less Vt reduction for higher T.

Design and Analysis of Leakage Current and Delay for Double Gate MOSFET at 45 nm in CMOS 303

DC Response DC Respo .... se

-/NM2jO -/NMZ/O

B.25 4.125

8.2

8.15 4.075

8.1 4.05

�e.05 �4.025 .s

i lO 8.0 '.0

7.95 '3.975

7.

7.85 '3.:925

7.8 3.9 45.0 47.5 50.0 52.5 55.0 57.5 60.0 45.0 47.5 50.0 52.5 55.0 57.5 60.0

Leff (E-9) Leff (£-9)

Figure 4(a) Figure 4(b)

Figure 4. Length Versus Leakage Curve, (a) For Single Gate Inverter, (b) For Double Gate Inverter

DC Response

-/NMot/O ••. 0-.---------------------------, 50,0

"' S , O

10.0

�'JS.O i'lo,O

25 . 0

20.0

� 5.0

1 0 . 0+-___ �---��---�---�-------I 25.0 5 0 , 0 75.0 1 000 1 2: 5 . 0 150,0

tomp (C)

Figure 5(a)

DC Response

-/NM2/D

175.0,----------------------,

150.

125.

�100. .s lO

'0.

2 ••

o,+-------�------�------____ ------�------� 25.0 50.0 75.0 100.0 125.0 150.0

temp (C)

Figure 5(b)

Figure 5. Leakage Versus Temperature Curve, (a) For Single Gate Inverter, (b) Double Gate Inverter

d� ___ 1_ dEg(sl) dtPB _ dQd - + s ..................... 2

dT 2q dT dT dT Qd is depletion charge density per channel;

Q --qN (e++)t for bulk Si andQ __ qNA(ejf)tsi d- A � d d-

2 [6][7].

B. Static Circuit

In the Fig: 7 we see that at different different VDD the delay of DG two input NAND is lower than the SG two input NAND. It means that DG NAND is 25-30% faster than the SG NAND.

One of the productive ways to decrease Ioff in CMOS circuit is to stack! turn off the device relatively than to use a single off devices. In this paper, Fig: 8 displays the leakage current characteristics for two input NAND cicuit with SG devices and DG devices for input patterns AB=

(00),(01),(10),(11).

In the 1st case AB=OO the both pFETs are on, pFETs have worst delay be in existence, thereby much reducing Ioff by � 70X. Due to less DIBL and S, the leakage current in stack devices expressively lower in DG devices by �35X for all the input pattern except 00. In the case of (01) and (10) Ioff is

almost same due to reduced DIBL, but in SG devices the Ioff is deviated by �5X. Input pattern AB is 11 the nFETs are on and here best delay is in existence so high Ioff is flow as comparison to the other input patterns. In DG devices the Ioff is less sensitive to input patterns. This makes the DG CMOS devices applicable for nanoscale circuit design.

A-------I Output

B------I

Figure 6. Schematic of Two input NAND

304 Proceedings o/7th International Conference on Intelligent Systems and Control (ISCO 2013)

The incalculable of power consideration, done in the early phase of the design cycle in stack gates, considerably reduced. We already know that the same leakage current flows through stacked nFETs as gate twmeling current is much smaller due to comparative thicker oxide. In the stack devices, reverse body effect will not arise in the DG devices as the body is floating, which could reduce loff but would considerably demote performance [14] [16].

600

"'"" 500 VJ 0. '-' � 400

Q) Q 300

200

100

0

0.7 0.8 0.9 1

VDD

Figure 7. Delay versus VDD for SG and DG two input NAND gate.

140 120 100

80 60 40 20

o

T /

/- ...

// .// -•

AB(OO) AB(Ol) AB(10) Ab(l1)

Input pattern(AB)

SG

DG

Figure 8. loff characteristics with respect to the input pattern of two input

NAND circuit and compare indicate in between SG and DG devices at VDD= 0.7. Both bulk Si and DO devices have equal performance when two inputs

are switching varying from 0 to VDD.

This fig: 9 displays the leakage current characteristics for three input NAND with SG and DG devices for (ABC) = (000),

(001), (010), (011), (100), (101), (110), (111). In the characteristics graph in between SG and DG shows the equal performance in the critical path. The leakage current considerably lowers in DG over � 1 OX for all input patterns. In case of(101), (011), (110) only one nFET is off and the loff is same in DG due to reduced DIBL, but in SG the loff is varied by �8X. The difference between best and worst case, in SG circuit loff is �60X but in DG circuit loff is �20X.

100

80 "'"" 60 <C 0. '-' 40 � 0 20 ......

0 _DG

Figure 9. loff characteristics for three input NAND, SO NAND and DO

NAND devices at VDD= 0.7v for (ABC) = (000), (001), (010), (Oil), (100), (101), (l 10), ( Ill). Both SO and DO devices has equal performances when

the three inputs are switching from 0 toVDD.

C. Dynamic Circuit

Purpose of dynamic circuit is to develop the circuit performance. However they endure leakage current and noise problem, particularly in nanoscale technologies. To conclude this, DG CMOS could be renovating.

"'"" 30 � t:: '-' .... 20 <l.l � 0 p...

10 <l.l b/) (Ij

.!<: (Ij <l.l 0 .....:l

0.7 0.8 0.9 1

VDD

SG

Figure 10. Leakage power versus VDD for DO and SO dynamic circuit in comparable performance .

Output

Figure I I. Schematic of Dynamic Circuit

Fig: 10 shows schematic of Dymanic circuit and leakage power consumption VDD for SG and DG device designed for the comparison of the circuit performance. This graph shows, DG device consumes � 1 0-15X lower leakage power for VDD= 0.7 to l.0 as compared to SG device. In the DG dynamic circuit

Design and Analysis of Leakage Current and Delay for Double Gate MOSFET at 45 nm in CMOS Technology 305

leakage power is anaesthetized to the input pattern due to the less DIBL. Due to this appreciable deceleration of leakage power DG technology would be much more competent use in dynamic circuit.

700

600

�500 VJ

8400 �

Q) 300 Q 200

100

o

0.7 0.8 0.9 VDD

Figure 12. Delay versus VDD for SO and DO dynamic circuitand in comparable performance.

Supply versus delay graph clearly shows that as Vdd increases the delay reduces. However the delay in DG MOSFET is observed to be 25% to 30% less than that of the SG MOSFET.

D. Latch

Latches circuits are very fundamental elements due to storage capability and power consumption. Because of this, Latches form an informative portion of total chip power.

In the Fig: 13 shows the graph in between VDD and leakage power, in this graph DG device consumes �5-8X lower leakage power for VDD= 0.7 to l.0 as compared to SG device. In the DG dynamic circuit leakage power is anaesthetized to the input pattern due to the less DIEL. Due to this appreciable deceleration of leakage power DG technology would be of much more competent use in latch.

20

� 15 5 � 10 SG 0 0. 5 0.) DG OJ) eo

"" 0 eo 0.) -l

0.7 0.8 0.9 1 VDD

Figure 13. Leakage power versus VDD for SO and DO latch in comparable performance.

A

Figure 14. Schematic Latch

Fig: 14 shows schematic of latch circuit and leakage power consumption VDD for SG and DG device designed for the comparison of the circuit performance.

IV. COMPARATIVE RESULTS OF SG AND DG CiRCUITS

The SG Circuits and DG Circuits have been simulated using the cadence virtuoso tool. The resulting waveform of Leakage Current versus Leff or temperature and delay versus input pattern or VDD clearly indicates that the DG Circuits show improved performance over the SG Circuits in terms of speed and power consumption. The comparison of different parameters of the two MOSFETs at 45 nm technology has been tabulated in table 1,2&3.

TABLE I. COMPARISON IN BETWEEN SO AND DO INVERTER WITH RESPECT To V ARIOUS PARAMETERS

S.No Parameters SG Inverter DG Inverter

1. Leakage Current W.r.t

8.2 4.1 Left=45nm(pA)

2. Leakage Current W.r.t

14 20 Temperature=27°C(pA)

TABLE II. COMPARISON IN BETWEEN SO AND DO CIRCUIT FOR DELAY AT VDD= 0.7

S.No Circuit SG Circuit Delay(ps) DG Circuit Delay(ps)

I. CMOS 1 nverter 343.34 285.45

2. Two Input NAND 302.48 235.68

3. Dynamic Circuit 368.45 250.34

306 Proceedings a/7th International Conference on Intelligent Systems and Control (ISCO 2013)

TABLE III. COMPARISON IN BETWEEN SG AND DG DYNAMIC AND LATCH CIRCUIT WITH RESPECT To VDD = 0.7V.

S.No Parameters SG Dynamic Circuit DG Dynamic Circuit SG Latch DG Latch Circuit Circuit

1. Leakage Power (nW) at

Vdd=0.7v

V. CONCLUSION

6.94

Cadence virtuoso tool simulation study with favorable 45nm DG devices is presented. In concluding scaled technology, CMOS circuit leakage current would be considerably reduced by DG circuits. The circuit power and circuit performance have been discussed, the 45nm DG inverter could offer � 40 X lower leakages current, 25% faster performance due to near lower DIEL. Due to lesser leakage current Leff reduces that's why DG circuit will be much more scalable. In the SG circuit, the Ioff is 1.5nA at the room temperature and in DG, it is 2.5pA. We studied and evaluated the leakage current dependence of input patterns for static circuits in DG circuit. The Ioff varies in negligible quantity as compared to the SG devices in input pattern. It is also contemplated that 45nm DG CMOS technology would favour much lower leakage power by � 1 OX for dynamic circuit and latches, compared with bulk Si counterpart technology. Here we concluded that DG is in anaesthetized state which would craft subnanoscale CMOS circuit design more elastic.

ACKNOWLEDGMENT

This work is supported by ITM University, Gwalior, India in Collaboration with Cadence System Design, Banglore, India.

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