THE 8th INTERNATIONAL SYMPOSIUM ON ADVANCED TOPICS IN ELECTRICAL ENGINEERING May 23-25, 2013

Bucharest, Romania

A Novel ESD Protection Structure used to Enhance the Safety of the MOSFET Integrated Circuitry

Dumitru-Paul Bicleanu1, Ana-Maria Nicuta1, Alexandru Salceanu1, Member IEEE

1“Gheorghe Asachi” Technical University of Iasi, Faculty of Electrical Engineering pbicleanu@ee.tuiasi.ro, nicuta_ana@ee.tuiasi.ro, asalcean@ee.tuiasi.ro

Abstract—The Electrostatic Discharge Phenomenon represents a threat for electronic equipment, especially for the semiconductor devices.

The present paper is focused on a novel Electrostatic Discharge Protection circuit designed to provide a secure path for the transient signals. Another innovative element in this work represents the combination between the MOSFET transistors and the Transient Voltage Suppressor diodes, with different passive components. The software platform used for simulations was PSPICE.

The research undertaken in this paper is useful in electronic industry, in order to find and to choose the correct components for each of the protected circuits. Thus it could be reduced or even eliminated the effects of electrostatic discharges.

I. ELECTROSTATIC DISCHARGE PHENOMENON The effects of electrostatic discharge (ESD) phenomena

become significant issues for high-tech industries and integrated circuits. One of the most important problems related to the ESD effects in MOSFET integrated circuits consists in the chip miniaturization. As the sizes have decreased below 30 nm, electrostatic integrity and device variability become difficult to control, degrading circuit performance [1].

In order, to characterize the device or to extract the parameters that influence its functionality, was developed a new testing method based on Time Domain Reflection (TDR) configurations [2-6]. Based on the obtained results, it can be modeled a protection circuit that will provide a barrier between the main circuit and the ESD pulse. The protection element should never interfere with normal circuit functions [7-9]. There are wide varieties of protection structures and components used in electronic industry to decrease the ESD effects. The ESD phenomenon could appear at any pin of an IC. The protection devices should avoid the excessive overvoltage, which can harm [10] the connected circuits. In order to assure the integrity of the protected circuits, the protection structures need to be connected in parallel with the node and acts as a switch when ESD phenomenon appears.

II. THE FUNCTIONALITY OF MOSFET INTEGRATED CIRCUITS

MOSFET integrated circuits are widely used in microelectronic industry, automotive industry, in power supplies. In MOSFET technology the most encountered ESD protections are Gate-Grounded (GG) NMOS configuration, Silicon Controlled Rectifiers (SCR), Transient Voltage Suppressor (TVS) diodes or Zener diodes.

In this framework, it will be discussed as a protection structure, a combination between TVS diodes and ggNMOS transistors, with different passive components. A ggNMOS configuration consists in the connection of all electrodes to the ground, excepting the drain. This configuration is characterized by low voltage and low on-resistance (2-5 Ω) [10], [11]. A low on-resistance means low power dissipation. While testing the susceptibility of the MOSFET integrated circuit to the ESD phenomenon, a good mode to observe the associated changes is the snapback conduction one. It presents the parasitic bipolar action intrinsic in the structure of the ggNMOS, (Fig. 1). It functions in the next way: when a positive ESD pulse is applied to the drain junction n+ the device is forced into a high impedance state (reverse biasing) until the breakdown voltage (Vbrv) is reached [10]. Reaching the Vbrv voltage means that the bipolar parasitic transistor will be turned on. The parasitic bipolar transistor described in Fig. 1 is turned-off in normal function conditions. This phenomenon is because both pn-junctions of the NMOS transistor are reversed biased. In this case, Isub = 0, resulting Vb = 0.

II.1. Avalanche Breakdown of Drain pn-junction of NMOS transistor

Breakdown voltage represents the avalanche multiplication of the charge carriers.

The avalanche breakdown phenomenon consists in the increasing of drain voltage. Thus, the electric field across the drain-substrate depletion region [12], [13] it will increase high enough, leading to the appearance of avalanche multiplication. Whereas the avalanche multiplication, electron-hole pairs are generated: the electrons will flow to the drain because of its high potential, while the holes flow to the substrate [14] (it has a lower potential).

Fig. 1 Cross-section of a ggNMOS transistor and its parasitic intrinsic

BJT transistor.

978-1-4673-5980-1/13/$31.00 ©2013 IEEE

Electrons flow from the source to the drain (when the BJT is ON). In this case, drain current, Id, increases and Vd suddenly decreases till the snapback holding voltage (Vsh) (Fig. 2) is reached. The path current resistance has positive temperature coefficients, [12], [13], during the snapback phenomenon. This is happened due to the thermal effect of the current which flows through any NMOS region. In case that the drain-source voltage still increases in parallel with drain current, then the NMOS device will enter in the thermal breakdown, Figs. 2 and 5. In thermal breakdown situation, the current path resistance has negative temperature coefficients. The current concentrates in certain localized fingers of NMOS and destroys them [12].

During snapback phenomenon the BJT transistor is in on-state. In this way the drain’s pn-junction goes to the avalanche breakdown region.

In avalanche mode, the drain current will increase. In n+ diffusion, the positive temperature coefficient of the drain resistance prevents the current concentration in a certain region. This resistance is named Ballast Resistor.

II.2. Circuit model designed for the avalanche and snapback description

One way to protect the MOSFET integrated circuits consists in using a NMOS transistor in gate ground configuration (Fig. 1).

In Fig. 3 it is represented the electronic circuit model for a NMOS transistor with its parasitic components. This circuit is used for ESD breakdown simulation. The tests are performed with Very Fast Transmission Line Pulse (VF-TLP) method.

The diodes Dbd and Dbs, are formed by the Drain-Substrate Junction, respectively Source-Substrate Junction. These two diodes form an intrinsic bipolar transistor, whose regime will trigger the breakdown phenomenon of the MOSFET transistor.

The base resistance is composed by Rb and Rbs resistors, connected in parallel. Rb resistor is the specific resistor in the case that the hole current flows from the drain. When the hole current flows from the substrate, the base resistance varies and is represented by Rbs [15].

With a precise gate bias and a good controlling of drain current, NMOS transistor has as a “four stages” behavior. The first two stages are the linear region, respectively the saturation region. The characteristic waveform of these two regions is modeled by standard SPICE MOS equations [1], [16-20]. If drain voltage Vd continues to increase, than the avalanche breakdown phenomenon, for the MOSFET device, will appear. As it is presented in [1], [12], [16], a further growth of the drain voltage will lead to secondary snapback and device destruction. The secondary breakdown is the thermal breakdown, [21-22], because of the critical junction temperature appeared as a consequence of current flow.

The principals components used to simulate the snapback effect of a MOSFET transistor are a simple NMOS transistor, a parasitic intrinsic BJT transistor, a current source to generate enough current for the avalanche phenomenon and a substrate resistance (Fig. 3). The substrate resistance and the current through it give the expression for the substrate (bulk) to source voltage.

Fig. 2. Snapback phenomenon when the BJT transistor is on-State.

M

C

E

BulkQ

B

Iav al

Ids

Id

Ibulk

Ic

Ib

.

.

.

..

Rb

CGD

CGS

CBD

Rg

Rbs

G

Dbd

S

D

CBS

Bulk

Rd

Rds

Rs

Dbs

Fig. 3. Circuit model for NMOS transistor and its parasitic components.

The substrate current is equal to the hole current generated

by the impact ionization less the base current of the parasitic intrinsic transistor [23].

The avalanche current is expressed as a function of multiplication factor and surface drain current, respectively BJT collector current.

( ) ( )cdsaval IIMI +⋅−= 1 (2)

This expression respects the Ebers-Moll or Gummel-Poon equations. The multiplication factor represents a relation between drain voltage and the saturation voltage Vsat.

⎟⎟⎠

⎞⎜⎜⎝

⎛−

−⋅−=

dsatd VVKK

M2

1 exp1

1 (3)

Multiplication factor is given by the Miller formula [16].

The parameters K1, K2 are fitting parameters, relating the connection between drain depletion width and impact ionization coefficients.

Actually, the drain current from Fig. 3 is compound from drain-to-source current, collector current of the BJT transistor and the avalanche (source) current.

avalcdsd IIII ++= (4)

III. ANALYSIS OF MOSFET BREAKDOWN PHENOMENON IN PSPICE

Fig. 4 presents a snapback simulation of a MOS transistor in PSPICE. It is illustrated the saturation region, which ends at the breakdown voltage threshold (Vbrv = 25 V). While the drain current increases, after the saturation region, will begin the first breakdown region characterized by a higher drain voltage. Consequently, with drain voltage increasing, in breakdown region will appear the phenomenon of oxide breakdown. Thus, more quantity of energy will migrate from drain to source, through the formed channel, causing the mal- functioning of the MOSFET device.

The drain current equation for saturation region depends of the MOSFET dimensions (channel length and device width).

This region is characterized by the condition Vds>Vgs-Vt and the equation is:

( ) ( )dstgsp

d VVVL

WkI χ+−= 1

22 (5)

where oxp Ck μ= and tV = threshold voltage.

( )bsbbtt VVV ϕϕγ −++= 0 (6)

The pk factor is an important parameter in circuit design [24], representing the mobility of the charge carriers and oxide capacitance, expressed as µA/V2.

In Fig. 5 there are represented the second two regions, when the classical PSPICE NMOS equations are no longer available. Thus, are presented the point where avalanche region begins. If the drain voltage increases, the snapback region will appear, (known as the thermal breakdown phenomenon).

The applied measurements were performed using the Very-Fast Transmission Line Pulse method, according with the IEC62615:2010 standard.

Fig. 4. Snapback waveform of a NMOS transistor with L = 180 nm

modeled in PSPICE.

The characteristics of this method consist in a very small rise time pulse (10 – 100 ps) and a pulse width between 0.1 – 1 ns. The applied signal was fixed at 2 kV. The breakdown voltage of the transistor is 25 V. To obtain the avalanche and snapback region, the transistor was configured as a gate grounded device (gate electrode connected to the ground).

This method represents one of the most advantageous electrostatic discharge methods for semiconductor devices [2] [7]. According to the IEC61000-4-2 standard, the assurance of the electronic circuit, it is very important. The introduction of VF-TLP method as a testing method for semiconductor devices was utmost importance in the selection of appropriate ESD protection devices [25]. That makes it a good opportunity to provide details about the electronic devices behavior. The VF-TLP delivers high current signal to characterize the behavior of the devices in the current – time domain of ESD events [25].

By comparison with the IEC61000-4-2 standard, the VF-TLP method (IEC62615:2010 standard), there are no correlation between them. The generated waveform is different from a standard to another. Also the DUT behavior is likely different.

IEC62615:2010 is a standard that defines a method for ESD testing with pulse signals of different amplitudes. After, the applied rectangular signal it can be evaluated the voltage - current response of the device under test. This standard helps the engineers to design the necessary protection circuits for electrostatic discharge event.

VF-TLP system provides a rectangular pulse waveform, while IEC61000-4-2 generates a different waveform, as it shown in Fig. 7. Consequently, the major advantage of VF-TLP method represents the well defined and precise controllability of the waveform parameters [25], impedance, pulse width, rise time, amplitude.

IV. RESULTS AND DISCUSSIONS The tests are performed, in order to establish the protection

parameters and components for protection structure. In Fig. 8, High-Voltage Power Supply represents the device

that provides enough power in circuit to test it in conditions of ESD. The pulse provided by the source (HVPS) and the antenna line will go through the attenuator to the dispositive under test (DUT). Then the signal is reflected and turned back to the antenna line through attenuator.

The applied signal is shown in Fig. 6, (green signal). It was chosen a small period of 35 ns with a pulse width of 0.5 ns. It was made a comparison between the MOSFET device, during the ESD stress, without and with protection circuit. As it can be seen in Fig. 6, the red waveform from second window represents the drain current after ESD stress, if the MOSFET device was not protected from ESD strikes. In the third window it is presented the drain current after the ESD stress with circuit protection. The current has decreased with 0.44 A when the protection circuit was connected in parallel with DUT.

In Fig.9 there is presented the setup model of the protection circuit.

Fig. 5. Avalanche region and snapback region (thermal breakdown)

simulated in PSPICE for a NMOS transistor.

Fig. 6. Applied signal on DUT (green), signal from DUT without

protection circuit (red), signal from DUT with protection circuit (blue).

Fig. 7. IEC61000-4-2 standard waveform.

T

Rs

Vs

ATTENUATOR

in out

DUT

inou

t

0

S

HVPS

Fig. 8. Circuit diagram of the VF-TLP testing setup.

Bias Circuit

.Iesd

Iesd

Iesd

Iesd

First Protection Stage

Iesd

Second Protection StageIesd .

PAD

M

M TVS

TVS

INPUTMAIN

CIRCUITM

M TVS

TVS

0

TVS

VDD

TVS

VSS

RbiasESD STIKE PULSE

.

Iesd .

VDD to VSSESD Clamping Circuit

PADOUTPUT

0

C

C

C

C

M

R

R

Fig. 9. Circuit diagram of the protection structure.

The setup circuit includes NMOS, PMOS transistors

grouped two by two, forming a CMOS structure. The transient voltage suppressor diodes have the role to protect the MOSFET transistors, (they lead the excessive current to power line, respectively to ground line).

It is illustrated a VDD to VSS protection circuit developed by the authors, in order to clamp the transient voltages. There

are two protection stages, which are constructed to offer a good safety when a transient signal appears on main circuit.

The Main Circuit is connected between the first and the second protection stage. The First Protection Stage will assure the main circuit safety for the ESD strike from the INPUT PAD. The Second Protection Stage eliminates the transient signals from the return path.

The role of the capacitors connected in parallel with TVS diodes is to eliminate the "ringing" phenomenon. This phenomenon appears because of the inductances from the transistors and diodes pins.

The ESD strike will come through the INPUT PAD. The two TVS diodes before the First Protection Stage have the role to lead the ESD current through the electrostatic discharge clamping circuit, in order to assure a path for the transient signals. The transient voltage suppressor diodes are biased by the Rbias resistance. Also, another role of this resistance is to protect the diodes, limiting the current from the INPUT PAD. First Protection Stage is used to take the transients signals from the INPUT PAD to limit the intensity of the ESD current. The NMOS, respectively PMOS transistors make the connection between the power and ground lines (VDD and VSS), each have a diode connected between the drain and the power line, respectively the drain and the ground line.

The Second Protection Circuit consists in a backup protection circuit, in the case that we will have an ESD current path return. In this case the VDD to VSS ESD Clamping Circuit will be activated. The transistor will be in ON-stage and will lead the transient signals to the VDD and VSS lines. The MOS transistor is activated by the circuit divider realized from two resistors. The resistors used as a biasing circuit for NMOS transistor, limit the excess current, which come from power line (VDD) to the gate.

The clamping voltage of the TVS diode limits the voltage across the protected circuit.

A first advantage of this circuit consists in having two ESD protection circuits and a circuit for VDD to VSS ESD clamping.

A second advantage consists in using of TVS diodes. The features of these diodes are the fast response time and the low clamping voltages. Complementary, the multitude of their applications as protection elements represents another advantage of the TVS diodes.

V. CONCLUSIONS AND FUTURE WORK The present paper, relates a good method for semiconductor

devices testing at the appearance of electrostatic discharge phenomenon. The framework of our innovative performed method is the very-fast transmission line pulse method.

Besides the innovative testing method, the paper presents a novel ESD protection circuit for MOSFET devices.

The above presented method helps us to provide enough power to simulate an electrostatic discharge event, in order to test and to choose the correct protection circuit. It was designed a safety circuit with two electrostatic discharge protection stages and a VDD to VSS ESD clamping circuit. When the ESD strike appears, the protection circuit is triggered and will limit the magnitude of the signal.

To eliminate the perturbations of the used components in the protection circuit, there were connected capacitors between the transient voltage suppressor diodes and power, respectively ground lines. They will eliminate the “ringing” phenomenon produced by the transistors and diodes electrode’s inductances. Thus, the connection of the parallel

capacitors improves the output waveform, filtering the signals from Main Circuit.

As future works, the authors intend to develop new protection circuits aiming to assure a good and safe path for the transient signals, in order to protect the MOSFET electronic circuits.

ACKNOWLEDGMENT

The paper was performed with the support of POSDRU CUANTUMDOC “DOCTORAL STUDIES FOR EUROPEAN PERFORMANCES IN RESEARCH AND INNOVATION” ID79407 project funded by the European Social Fund and Romanian Government.

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