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Very Fine-grained Fault-tolerant Routing Algorithm ofNoC Based on Buffer Reuse Shijian Zhang, Guodong Han and Fan Zhang National Digital Switching System Engineering & Technological R&D Center Zhengzhou, Henan 450002, China [email protected] Abstract-Fault model is the basis of research on fault-tolerant routing algorithm for Network on Chip (NoC). Since the former fine-grained fault model could not distinguish link faults from channel faults effectively, a much more fine-grained fault model is put forward, and a new fault-tolerant routing algorithm named VFFRA-BR (very fine-grained fault-tolerant routing algorithm based on buffer reuse) is proposed in this paper, to improve the utilization rate of the NoC resources. This algorithm adopts the transparent transmission mechanism based on buffer reuse (TTBR) to tolerate internal channel faults of routers. Experimental and synthesis results demonstrate that our algorithm performs better on average throughput, average latency and average hop counts of NoC while keeping a low on- chip resources overhead. Keywords-Network on Chip (No; fault model; fault-tolerant roung; buffer reuse; transparent ansmission I. INTRODUCTION With the CMOS tenology advancing, the size of very large scale integrated (VLSI) circuites continues to scale down, which enables the integration of hundreds of processing elements (PE) on a single chip. Traditional on-chip buses can not scale to meet increasing communications needs between PE. order to overcome the perrmance gap, network on chip (NoC) [1] [2] is being researched. Because of excellent modularity and scalability, NoC is becoming a most promising interconnection solution for multi-core chips. However, with the shrinking of the feature size, the increasing of integration level, and the rising of operating equency, the communication on chip suffers more and more influence, and the failure rate of the chip becomes higher and higher. order to ensure the yield of chip and operating reliability, some measures must be taken to tolerate various faults on chip. According to the timeliness, NoC faults can be divided into ansient and pmanent faults. this paper, we only focus on permanent faults. There may be two kinds of pmanent faults, which are router faults and link faults. Perrming logical processing on different kinds of pmanent faults, i.e., establishing fault model, is the foundation of NoC fault-tolerant mechanisms research [3]. The complexity of NoC fault-tolerant routing algorims is detmined by fault model. A good fault model should reduce the complexity of algorims as far as possible, meanwhile, cause influence on the perrmance as small as possible. According to different granularities, most of current fault 978-1-4673-5000-6/13/$31.00 ©2013 IEEE Supported by Chinese National Programs for High Technology Research and Development (2009AAO 1220I) and Ministry of Major Science & Technology of Shanghai (08dz501600). 758 models can be divided into fault block model and single component (a router or a link) fault model. The granularity of fault block model is faulty block, which is composed of multiple faulty components. Boppana and Chalasani algorim om [4] is the first algorim that adopts fault block model, the algorim divides network into several faulty blocks by fault rings and fault chains, packets that ansmit in network bypass faulty blocks rough the use of fault rings or fault chains. A low cost and reconfigurable routing algorim is presented in [5] by extending conventional tu model, the algorim adopts rectangular fault block model without shared boundaries. The granularity of single component ult model is faulty component, which is a faulty router or a faulty link. [6] describes FTDR with single component fault model, the algorim maps faulty router into four faulty links attached on the router. Basing on the routing table that is updated using 2- hop fault information, FTDR determines the best path to bypass faulty component. LBDR [7] and uLBDR [8] are low cost routing algorims that are implemented by logical circuits. Essentially, both of above algorims adopt single component fault model, fault components are shown rough connectivity bits. Granularities of fault models mentioned above are all at least at the level of component, so partial fault of the router causes abandment of the whole router, even some normal routers are also divided into fault blocks. Actually, the ult routers are oſten partial fault, and they can still work with the remaining nctionality [9]. For this reason, researchers suggest using fine-grained fault model for fault-tolerant design so as to re-enable partial faulty router, thereby improving resource utilization of NoC. This paper is based on fine-grained ult model. IT. RELATED WORK Refining the granularity of the fault model into faulty chnel between port and port in a router, fine-grained ult model keeps the entire router om being discarded because of partial fault. [9], a fine-grained fault model of NoC has been proposed, namely nctional fault model, which highly covers faults in routers. FFBR [10] improves the nctional ult model and categorizes the faults inside a router as four saighess faults and eight tu faults. According to fine- grained fault model, fault maix is used to record chnel faults in [11], based on which a fine-grained fault-tolerance
Transcript
Page 1: [IEEE 2013 IEEE 4th International Conference on Software Engineering and Service Science (ICSESS) - Beijing, China (2013.05.23-2013.05.25)] 2013 IEEE 4th International Conference on

Very Fine-grained Fault-tolerant Routing Algorithm ofNoC Based on Buffer Reuse

Shijian Zhang, Guodong Han and Fan Zhang National Digital Switching System Engineering & Technological R&D Center

Zhengzhou, Henan 450002, China [email protected]

Abstract-Fault model is the basis of research on fault-tolerant

routing algorithm for Network on Chip (NoC). Since the former fine-grained fault model could not distinguish link faults from channel faults effectively, a much more fine-grained fault model is put forward, and a new fault-tolerant routing algorithm named VFFRA-BR (very fine-grained fault-tolerant routing algorithm based on buffer reuse) is proposed in this paper, to improve the

utilization rate of the NoC resources. This algorithm adopts the transparent transmission mechanism based on buffer reuse (TTBR) to tolerate internal channel faults of routers. Experimental and synthesis results demonstrate that our algorithm performs better on average throughput, average latency and average hop counts of NoC while keeping a low on­chip resources overhead.

Keywords-Network on Chip (NoC); fault model; fault-tolerant routing; buffer reuse; transparent transmission

I. INTRODUCTION

With the CMOS technology advancing, the size of very large scale integrated (VLSI) circuites continues to scale down, which enables the integration of hundreds of processing elements (PE) on a single chip. Traditional on-chip buses can not scale to meet increasing communications needs between PE. In order to overcome the performance gap, network on chip (NoC) [1] [2] is being researched. Because of excellent modularity and scalability, NoC is becoming a most promising interconnection solution for multi-core chips. However, with the shrinking of the feature size, the increasing of integration level, and the rising of operating frequency, the communication on chip suffers more and more influence, and the failure rate of the chip becomes higher and higher. In order to ensure the yield of chip and operating reliability, some measures must be taken to tolerate various faults on chip.

According to the timeliness, NoC faults can be divided into transient and permanent faults. In this paper, we only focus on permanent faults. There may be two kinds of permanent faults, which are router faults and link faults. Performing logical processing on different kinds of permanent faults, i.e. , establishing fault model, is the foundation of NoC fault-tolerant mechanisms research [3].

The complexity of NoC fault-tolerant routing algorithms is determined by fault model. A good fault model should reduce the complexity of algorithms as far as possible, meanwhile, cause influence on the performance as small as possible. According to different granularities, most of current fault

978-1-4673-5000-6/13/$31.00 ©2013 IEEE

Supported by Chinese National Programs for High Technology Research and Development (2009AAO 1220 I) and Ministry of Major Science & Technology of Shanghai (08dz50 1600).

758

models can be divided into fault block model and single component (a router or a link) fault model.

The granularity of fault block model is faulty block, which is composed of multiple faulty components. Boppana and Chalasani algorithm from [4] is the first algorithm that adopts fault block model, the algorithm divides network into several faulty blocks by fault rings and fault chains, packets that transmit in network bypass faulty blocks through the use of fault rings or fault chains. A low cost and reconfigurable routing algorithm is presented in [5] by extending conventional turn model, the algorithm adopts rectangular fault block model without shared boundaries.

The granularity of single component fuult model is faulty component, which is a faulty router or a faulty link. [6] describes FTDR with single component fault model, the algorithm maps faulty router into four faulty links attached on the router. Basing on the routing table that is updated using 2-hop fault information, FTDR determines the best path to bypass faulty component. LBDR [7] and uLBDR [8] are low cost routing algorithms that are implemented by logical circuits. Essentially, both of above algorithms adopt single component fault model, fault components are shown through connectivity bits.

Granularities of fault models mentioned above are all at least at the level of component, so partial fault of the router causes abandonment of the whole router, even some normal routers are also divided into fault blocks. Actually, the fuult routers are often partial fault, and they can still work with the remaining functionality [9]. For this reason, researchers suggest using fine-grained fault model for fault-tolerant design so as to re-enable partial faulty router, thereby improving resource utilization of NoC. This paper is based on fine-grained fuult model.

IT. RELATED WORK

Refining the granularity of the fault model into faulty channel between port and port in a router, fine-grained fuult model keeps the entire router from being discarded because of partial fault. In [9], a fine-grained fault model of NoC has been proposed, namely functional fault model, which highly covers faults in routers. FFBR [10] improves the functional fuult model and categorizes the faults inside a router as four straightness faults and eight turn faults. According to fine­grained fault model, fault matrix is used to record channel faults in [11], based on which a fine-grained fault-tolerance

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adapti ve routing algorithm (FF AR) has been presented. Fine­grained fault model refmes the type of faults, therefore improves resource utilization of network, which is very meaningful in resource-constrained NoC.

§f E -EE3�------: :�����. [IT] ,:X [TID

w s�§ Figure I. Link fault in fine-grained fault models

Link faults have become main faults of NoC [3] [12]. Tn current fine-grained fault models [10] [11], a link fault is mapped to six channel faults connected to the faulty link, as shown in Fig. 1. This rough mapping still has room for improvement, for the link is faulty, but six channels as well as buffers at both ends of the faulty link are not necessarily defective. This paper improves the traditional fine-grained fault model, builds a finer grained fault model which can effectively distinguish link faults, channel faults and buffer faults, namely very fine-grained fault model. According to the very fine­grained fault model, very fine-grained fault-tolerant routing algorithm based on buffer reuse (VFFRA-BR) is proposed in this paper.

TTT. NoC ARCHITECTURE AND F AUL T MODEL

A. NoC Architecture

Research in this paper just base on the architecture of 2D Mesh NoC which contains processing elements (PE), network interface (NT), routers and links. PE may be processors, memories, hardware modules defined by user, or other TP cores. Routers are key components of NoC, they constitute the network communication nodes. Two connected routers use two reverse unidirection links to communicate with each other. Fig. 2 shows the NoC architecture of a 4x4 2D Mesh topology with link faults, channel faults and buffer faults.

R: Router X: Faulty SYlnbol

Figure 2. 2D mesh topology

B. Fault Model

This paper improves fine-grained fault model in [11], proposes very fine-grained fault model which can distinguish

759

link faults from channel faults. Very fine-grained fault model is given in detail below.

• For a channel in the router, if a packet cannot be transferred from one port to another, then the channel between these two ports is regarded as faulty channel, channel fault is unidirectional.

• For a link between two routers, if a packet cannot be transferred from one router to the other, then the link is deemed as faulty link, link fault is also unidirectional.

• For a buffer in the router, if the buffer cannot access data successfully between the router and the link, then the buffer is regarded as faulty buffer; a buffer fault is mapped to a link fault and faults of three channels which are connected to the buffer.

• For a drastically broke down router, the router fuult is mapped to eight link faults which are connected to the router.

According to the very fine-grained fault model above, interior registers of routers are used to record fault diagnosis results, fault information recorded by registers covers not only channel faults but also link faults (eight links in total). Tn [11], registers are shown in mode of functional fault matrix, the concrete form of the matrix is similar to matrix shown in Fig. 3. However, functional fault matrix records only channel faults, and the elements of the principal diagonal in the matrix have not any practical significance, in some sense registers of these elements are idle.

I I N P U T

N S

'N E

N 1 0 1 1

OUTPUT S W E 1 1 0 2 0 0 1 0 1 1 1 1

Figure 3. Very tine-grained timlt matrix

This paper improves functional fault matrix in [11], uses a new matrix named very fine-grained fault matrix (VFFM) to characterize very fine-grained fault model. VFFM stores fuult information of eight links in registers of the principal diagonal (see gray box in Fig. 3). The vertical coordinate of VFFM is inputs of the router, and the horizontal coordinate is outputs of the router, and they both include ports of four directions, North (N), South (S), West (W) and East (E).

For VFFM, every element out of the principal diagonal is implemented by a I-bit register, and uses 0 or 1 to represent the status whether fault has happened in the channel between the input port and output port, 0 denotes fault and 1 denotes no fault; any element on the principal diagonal is implemented by a 2-bit register, and uses decimal numbers 0, 1, 2 and 3 to represent the fault status of links, where 0 means both input and output links of the corresponding port are faulty, 1 denotes both input and output links are free of errors, 2 stands for failure of input link and 3 indicates that only output link is defective. Tn Fig. 2, several faults have been diagnosed in or beside the faulty router, include channel fault between North

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port and East port (NE channel), input buffer fault of South port, input and output link faults of West port, VFFM of the faulty router is shown in Fig. 3.

IV. VERY FINE-GRAlNEDFAULT-TOLERANT ROUTING

ALGORITHM BASED ON BUFFER REUSE

A. Transparent Transmission based on Buffer Reuse

In current fme-grained fault models, a link fault is mapped to six channel faults connected to the faulty link. In some sense, this approach of mapping is irrational. Actually, buffers stand on both ends of the faulty link and the six faulty channels may be normal. Very fme-grained fault model can distinguish link faults from channel faults effectively, it is acted as the foundation of buffer and channel reuse.

Figure 4. Workflow of TTBR

On the basis of the very fine-grained fault model, this paper presents transparent transmission mechanism based on buffer reuse (TTBR). TTBR can reuse buffers and channels on both ends of the faulty link. The workflow of TTBR is shown in Fig. 4, if both input and output links of W port as well as NE channel are faulty, and buffers of W port are faultless; meanwhile, preferred output port of the packet from N is E, TTBR will send the packet to buffers of W port first, then transmit the packet to E port transparently through buffers of W.

W port in Fig. 4 is termed as "transparent transmission ports" (TTP). TTP must be ports with faulty bidirection links (ports whose input and output links are both failure), but not all ports with faulty bidirection links can be termed as TTP. A sufficient condition for a port becoming TTP must also contain the following items, that is, the channel between input port and the port with faulty bidirection links, as well as the channel between the port with faulty bidirection links and preferred output port is normal. For packets that need to be transmitted transparently, TTP adopts the same processing method as packets from input links (before links' malfunction).

To use TTBR successfully, this paper makes some improvement on structure of the router. As shown in Fig. 4, an additional channel is added between input and output links, i.e. , self-communicating channel (SCC). Actually, SCC is a short wire with low hardware overhead. SCC is only activated after malfunction of both input and output links (when the value of corresponding element on the principal diagonal is 0).

Link faults have become main faults of NoC, and buffers are among the most important resources in NoC [13]. TTBR reuses normal buffers abandoned in fine-grained fault model to

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tolerate channel faults, improves resource utilization as well as the probability of choosing preferred output port.

B. The priority strategy of router ports

VFFRA-BR adopts the priority strategy presented in [11] to determine priorities of four router ports. According to [11], four ports can be divided into four levels, that is 11, P2' � and

P4 by descending order.

Two (one or zero sometimes) ports that are closer to destination in position are assigned the priority of 11, and they

are preferred output port(s). The input port is assigned the lowest priority of P4 • Excluding 11 and P4 ports, the

remaining port(s) in the direction(s) which is (are) vertical to p. port(s) is (are) assigned the priority of P2 • If there are only

one p., P2 and P4 port, then the last one is assigned the

priority of P3 •

C. Deadlock Avoidance Mechanism

This paper adopts the odd-even tum model [14] to avoid deadlocks in NoC. According to the model, EN (East to North) tum and ES tum are forbidden in routers of odd columns; NW tum and SW tum are forbidden in routers of even columns. VFFM can implement the odd-even tum model conveniently, just according to the odd/even position of the router, map forbidden turns to channel faults (i.e. , set the corresponding elements of VFFM to be 0), then the odd-even tum model is embedded in the very fine-grained fault model.

D. The Description ofVFFRA-BR

On the basis of the priority strategy of router ports, and combining with TTBR mechanism, a deadlock-free fault­tolerant routing algorithm VFFRA-BR is realized. The algorithm is described as follows, where Px ( 1 :s; x :s; 4, x E Z )

indicates the priority of a port:

Algorithm YFFRA-BR:

Step i:For an arriving packet, compare destination address (Xd ,1";J ) with current router address (Xc, Y;). If these

two addresses are equal to each other, then route the packet to NT; else perform the next step.

Step 2: Determine priorities of four ports by using (Xd ,1";J ) and

( Xc , Y;). Let x = 1 and perform the next step.

Step 3:Judge whether the channel between input port and Px port(s) is faulty (by using VFFM). If the channel is normal, then route the packet to Px port(s); else perform

the next step.

Step 4: Judge whether there are ports with fuulty bidirection links in the router. If the ports do not exist, then let x = x + 1 and skip to step 3; else perform the next step.

Step 5:Go through all ports with faulty bidirection links, judge whether there are TTP. If TTP do not exist, then let x = x + 1 and skip to step 3; else perform the next step.

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Step 6:Among all TTP, choose one port at random to execute TTBR mechanism. Route the packet to this port, and then transmit the packet to Px port(s) transparently.

When there is not channel fault between input port and Px ( x may be 1, 2, 3, 4 in order) port(s), VFFRA-BR is equivalent to FFAR [11]. If the channel is faulty, VFFRA-BR will try to adopt TTBR mechanism.

V. PERFORMANCE Ev ALUATlON

A. Simulation Platform

An open-source simulation platform NIRGAM [15] is used to evaluate the performance of VFFRA-BR, NTRGAM is a simulator specially designed for NoC. The detailed parameters of the simulator are listed in Table I . Three performance indicators are compared in our experiment, which are average throughput, average latency and average hop counts. Need of special note is, according to very fine-grained fault model, all faults in NoC can be mapped to link faults and channel faults,

so "failure rate" in Table I represents faulty rate of links and channels. For instance, if "failure rate" is 10%, then link faults and channel faults will be injected into NoC with a probability of 10%, respectively. For the partly or fully defective routers, the XY algorithm all regards them as out of service.

B.

TABLE T.

Parameters Topology

Mechanism of switch

Traftlc pattern

Flit size

Packet size

Number of bufTers

Fault distribution

Failure rate

Algorithms compared

Experimental Results

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DETAILED PARAMETERS

Value 8 x8 2D Mesh

wormhole

uniform

2 bytes

7 fl its

2 fl its

random

0,100/0,200/0,300/0

XY, FFARPll, VFFRA-BR

I-XY DFFAR _VFFRA-BR

r-

r-

r-

I 0.1 0.2 0.3

Fa ilure rate

Figure 5. Average throughput

761

Fig. 5 shows the average throughput of NoC in different failure rates. In the case of no fault, average throughputs of VFFRA-BR and FFAR are approximately equal, but both of them are slightly higher than XY. While in the case of faults, and with the increase of failure rates, the superiority of VFFRA-BR gradually appears. In failure rates of 10%, 20% and 30%, VFFRA-BR can improve average throughput by 3.7%, 10.3% and 18.l % from FFAR, respectively. The reason is obvious: compared with XY, two other algorithms can balance the traffic load by adopting the priority strategy of four ports; besides, TTBR mechanism enables the fauty channel by a store-and-forward step, so VFFRA-BR performs better in average throughput than FF AR.

� 150 _XY(Ofautt) ...... FFAR (0 fault!

VFFRA-BR (0 fault! ..... XY (20% fautts) � rJ) OJ

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•••• FFAR (20% faults) : ..... VFFRA-BR (20% faults) ': .: *

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lin : "::::: .. ···

O L-�----��----�----�� o 1 0.2 0.3 0.4 Packet injection rate (flitslrouter/cycie)

Figure 6. Average latency

Tn failure rates of 0 and 20%, the average latency of NoC is shown in Fig. 6. Tn the absence of failure, XY outperforms because of its simplicity, and curves of two other algorithms are almost overlapped. When the failure rate is increased to 20%, compared with FFAR and XV, VFFRA-BR can improve the average latency by 21.3% and 45.7%, respectively. And here is the reason: without faults, VFFRA-BR is equivalent to FF AR; when the failure rate increases, TIBR improves the probability of choosing preferred output port, which leads to a lower average latency.

20

.l!l c

is 15 " Q. o .c � 10 !" OJ > <{ 5

o

.XY :1 DFFAR .VFFRA·BR

o

Figure 7.

o 1 0.2 Failure rate

Average hop counts

r-

0.3

Fig. 7 shows the average hop counts of NoC in different failure rates. When the failure rate is 0, three algorithms can use minimal path for communication. While in the case of faults, compared with FFAR, VFFRA-BR can forward the packet with fewer hops, which are 9. 1%, 16. 6% and 19. 1% lower than FF AR in three kinds of failure rates. The reason is that TTBR mechanism could use a store-and-forward channel

Page 5: [IEEE 2013 IEEE 4th International Conference on Software Engineering and Service Science (ICSESS) - Beijing, China (2013.05.23-2013.05.25)] 2013 IEEE 4th International Conference on

in place of optimal channel (channel between input port and preferred output port) when the optimal channel is faulty, thus ensuring minimal path for transmission.

C. Synthesis Results

To evaluate hardware overhead of VFFRA-BR, this paper completes the router hardware design and implement of three algorithms in Xilinx Virtex-6 XC6VLX550T FPGA, the design

is described in Verilog HDL with Xilinx ISE Design Suite

13.4. Synthesis results are listed in Table II.

TABLE II. HARDWARE OVERHEAD OF A ROUTER

Algorithms LUTs Registers XY 693 187

FFARllll 1185 402

VFFRA-BR 1249 423

Synthesis results show that XY has the lowest hardware overhead because of absence of fault tolerance; compared with FF AR, for the introduction of the TTBR, VFFRA-BR brings slight increases in LUTs and registers, 5.4% and5.2%, respectively.

VI. CONCLUSION

This paper improves traditional fine-grained fault model of NoC, builds a finer grained fault model, which is named very fine-grained fault model. On the basis of the very fine-grained fault model, very fine-grained fault-tolerant routing algorithm based on buffer reuse (VFFRA-BR) is proposed. VFFRA-BR adopts TTBR mechanism to tolerate channel faults in routers, so as to route packets to preferred output port. Experimental results demonstrate that with the increase of traffic load and failure rate, the advantage of VFFRA-BR becomes more and more obvious. Synthesis results show that the algorithm can improve the performance of average throughput, average latency and average hop counts greatly, while it incurs a little hardware overhead increase. Thus VFFRA-BR provides a fault-tolerant routing solution of high reliability and high performance/price ratio.

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REFERENCES

[1] L. Benini and G. D. Micheli, "Network on chip: a new SoC paradigm," IEEE Transactions on Computer, vol. 35, pp. 70-78,2002.

[2] K. Hofmann, "Network-on-Chip: challenges for the interconnect and I/O-Architecture," in proceedings of the 2012 International Conference on High Performance Computing and Simulation, 2012, pp. 252-253.

[3] Y. Wan, Coding Based Research and Design on Reliability in Network on Chip Interconnects. Master Thesis, Nanjing University of Aeronautics and Astronautics, 2010.

[4] R. V. Boppana and S. Chalasani, "Fault-tolerant routing with non­adaptive wormhole algorithms in mesh networks," in proceedings of the 1994 ACMiIEEE conference on Supercomputing, 1994, pp. 693-702.

[5] B. Fu, Y. Han, H. Li, and X. Li, "Building resilient NoC with a reconfigurable routing algorithm," Journal of Computer-Aided Design & Computer Graphics, vol. 23, pp. 448-455, 2011.

[6] c. Feng, Z. Lu, A. Jantsch, and 1. Li, "A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for Network-on-Chip," in proceedings of the 3rd International Workshop on Network on Chip Architectures, 20 I 0, pp. 672-677.

[7] 1. Flich, S. Rodrigo, and J. Duato, "An eflicient implementation of distributed routing algorithms for NoCs," in proceedings of the Second ACMITEEE International Symposium on Networks-on-Chip, 2008, pp. 87-96.

[8] S. Rodrigo, 1. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, et aI., "Addressing manufacturing challenges with cost-efficient fault tolerant routing," in proceedings of the Fourth ACMITEEE International Symposium on Networks-on-Chip, 2010, pp. 25-32.

[9] 1. Raik, V. Govind, and R. Ubar, "An external test approach for network-on-a-chip switches," in proceedings of 15th Asian Test Symposium, 2006, pp. 437-442.

[10] Y. Zheng, H. Wang, and S. Yang, "A fault-tolerance routing algorithm of NoC based on functional-fault model," in proceedings of the 6th China Test Conference, 20 I 0, pp. 204-208.

[II] Q. Chen, X. Luo, F. Zhang, and L. Liu, "Fine-grained fault-tolerance routing algorithm of NoC based on reuse of partly defective switches," Application Research of Computers, vol. 29, pp. 2586-2588, 2012.

[12] 1. Kim, D. Park, C. Nicopoulos, N. Vijaykrishnan, and C. R. Das, "Design and analysis of an NoC architecture from performance, reliability and energy perspective," in proceedings of the 2005 ACMITEEE Symposium on Arthitecture for Networking and Communications Systems, 2005, pp. 173-182.

[13] S. K. MandaI, R. Denton, S. P. Mohanty, and R. N. Mahapatra, "Low power nanoscale butler management for network on chip routers," in proceedings of the 20th Great Lakes Symposium on VLSI, 20 I 0, pp. 245-250.

[14] G. M. Chiu, "The odd-even turn model for adaptive routing," IEEE Transactions on Parallel and Distributed Systems, vol. II, pp. 729-738, 2000.

[15] L. Jain, NIRGAM: A simulator for NoC interconnect routing and applic­ation modeling version 1.1, http://nirgam.ecs.soton.ac.uklDocumentati­on.php.


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