High-frequency IntNovel Single R

(SR

Udupi R. Prasanna Electrical Engineering University of Texas at Dallas Dallas, USA prasanna.ur@utdallas.edu

Abstract— This paper presents a hybrid modconsisting of singe-reference six-pulse-modufor front-end dc/dc converter and 33% modphase inverter. Employing proposed novel Send dc/dc converter, high frequency (HF) puwaveform is produced, which is equivalent toat 6x line frequency (rectified 6-pulse output ophase ac waveforms) once averaged. It redcomplexity owing to single-reference three-pas compared to conventional three-refereSPWM. In addition, it relives the need of reducing the cost and volume. Eliminating helps in retaining the modulated informatiothree-phase inverter. It needs only 33% (1/3the inverter devices to generate balanced thwaveforms resulting in significant saving iswitching losses of inverter semiconductor instant of line cycle, only two switches are reqHF and remaining switches retains their uniqON or OFF. Besides, inverter devices are when current through them is at its peakswitching loss accounts to be around 86.6%with a standard voltage source inverter standard three-phase sine pulse width modThis paper explains operation and analysis ofinverter modulated by proposed novel moAnalysis has been verified by simulatioPSIM9.0.4. Experimental results demonstratthe proposed modulation.

I. INTRODUCTION Though fossil fuel resources are limited

an alarming rate, the global demand for osignificantly in recent years. Energy consumby transportation sector has risen exponincreasing number of vehicles [1]. Transpofor above 20% of the total energy related econventional vehicles, 10-15% of the converted to traction due to poor perform

terleaved Three-phase InReference Six Pulse ModRSPM) Technique

Akshay Electrical and

National Un

eleak

dulation technique ulation (SRSPM)

dulation for three-SRSPM by front-

ulsating dc voltage o six-pulse output of balanced three-duces the control phase modulation ence three-phase dc link capacitor dc link capacitor

on at the input of 3rd) modulation of hree-phase voltage

n (at least 66%) devices. At any

quired to switch at que state of either

not commutated k value. Drop in % in comparison (VSI) employing

dulation (SPWM). f the HF two-stage odulation scheme. on results using te effectiveness of

d and depleting at oil has increased med and demand nentially due to ortation accounts emissions [2]. In fuel energy is

mance of Internal

Combustion Engine (ICE). Hybrid can boost this efficiency to about 30economy. HEVs reduce CO2 emisscompletely like Electric Vehicles (EEVs is energy storage, since enerstoring options is small as comdecreasing the drive range. Anotcharging of energy storage device [3

Fuel Cell Vehicles (FCVs)transportation systems with zero environment clean. FCVs have the reduce dependence on foreign oil. rather than gasoline and emit no hathat cause climate change. FCVs like EVs. FCVs are free from drivtime limitations. However, cost,storage onboard are the challenges.

The major components of a typin Fig. 1 [1-8]. An auxiliary enrequired for start-up and for storregenerative braking EVs/FCVs btechnology lacks energy storage capcharacteristics and dynamics of fustorage like battery or ultracapacitor

Fig. 1. Architecture of a f

nverter with dulation

y Kumar Rathore d Computer Engineering niversity of Singapore Singapore

kr@nus.edu.sg

Electric Vehicle (HEV) 0-40% by increasing fuel sion but cannot eliminate EVs). Major challenge in rgy density of available mpared to fossil fuels ther challenge is quick 3].

are next generation emission to keep the

potential to significantly FCVs run on hydrogen

armful tailpipe emissions are efficient and quieter ving range and charging safety, and hydrogen

pical FCV are illustrated nergy storage device is ring energy captured by because present fuel cell pability [9]. Based on the uel cell, optimal energy r is selected [10-11].

fuel cell car.

5355978-1-4799-0336-8/13/$31.00 ©2013 IEEE

Fig. 2. Functional diagram of a fuel cell propulsion system.

A 12 V battery is used to supply power to auxiliary loads

in vehicle. The same battery can be used with a bi-directional dc/dc converter [12] to complete the above mentioned tasks as shown in Fig. 2. Since fuel cell stack voltage varies by 100% with change in fuel flow rate, there is a need for converter to regulate dc bus voltage (say at 100 V) and power flow [13-16]. A HF two-stage inverter is employed to convert 100 V into three-phase ac voltage to drive the ac motor to propel the vehicle and is main focus of this paper.

Single stage inverter is the simplest topology with least component count and high efficiency. But low voltage fuel cell stack needs a multi-stage inverter to boost its low voltage to generate three-phase voltage signals [17]. HF modulation is adopted to achieve compact, low cost, and light weight system. Therefore two stage HF inverter consisting of front-end dc/dc converter followed by a standard three-phase pulse-width modulated (PWM) inverter as shown in Fig. 2 is an alternative solution. This paper proposes a hybrid modulation technique that comprises two different modulations for the two stages. Single Reference Six Pulse Modulation (SRSPM) is proposed to control front-end full-bridge dc/dc converter to produce HF pulsating dc voltage having six-pulse information on an average. A single reference signal is used for SRSPM implementation. Second modulation is 33% (or 1/3rd) modulation adopted for a three-phase inverter that produces balanced three-phase voltage. In 33% modulation, only one leg is modulated at a time. It reduces the average switching frequency and limits the switching losses to 33% of the conventional value. Interleaving does not affect the modulation implementation, or in other words the proposed SRSPM is applicable to single full-bridge unit too. Interleaving is shown to improve power transfer capacity. Though similar hybrid modulation technique for inverter control has been proposed earlier [18-19], the front-end dc/dc converter essentially has minimum three full bridges employing standard three-phase SPWM with three references. It results in complex control and has a major issue of circulating current between the bridges passing conducted by semiconductor devices. If one bridge fails, the modulation fails, i.e., the pulsating dc voltage does not contain six-pulse information anymore and hence, the inverter is not able to produce balanced three-phase output. The proposed modulation has unique single reference signal. Even if a bridge fails, the other will maintain six-pulse information in pulsating dc link voltage and inverter is still able to produce balanced three-phase voltage. It is therefore robust and offers higher reliability.

The overall system has the following merits: (a) Elimination of dc link electrolytic capacitor: reduces volume and improves reliability; (b) Reduced average switching frequency of inverter: at any instant of time, only one leg of inverter is modulated at HF keeping other two legs at same switching state. This reduces the switching losses and improves efficiency. Switching losses are further reduced because the devices are not commutated when current is at its peak. (d) Single reference front-end modulation: a single reference signal is used to implement six-pulse modulation to produce pulsating dc voltage at the dc link.

The proposed inverter has better reliability compared to existing topologies owing to single-reference modulation.

In [18-19], three full-bridges at front-end are used and standard three-phase SPWM is employed that uses three single-phase sine references. Three single-phase HF transformers are connected to compute maximum line-to-line and generate pulsating dc voltage with six-pulse information. Modulations of three bridges are mutually dependent to produce pulsating six-pulse waveform at the dc-link of the inverter. In this case, accurate functioning of each front-end full bridge is necessary to maintain six-pulse waveform/information at the dc link and later to obtain balanced three-phase inverter output voltage. From the reliability point of view, failure of a full-bridge results in failure of the system. This is a major weakness of the three-reference modulation demonstrated in [18-19].

This paper proposes a single-reference modulation to do the same task, i.e., producing pulsating six-pulse waveform at the dc link and generate balanced three-phase sine output.

Interleaving (two bridges at front-end) is done to increase the power transferring capacity. However, the proposed modulation scheme works with single bridge too owing to single-reference approach. Devices at symmetrical location in two bridges are operated by identical gating signals. The novelty and merit of this innovation is unique single reference that is developed to contain information of six-pulse waveform. Since, identical single reference is given to both the front-end bridges, in case of failure of one of the bridges; the other bridge still produces the same six-pulse pulsating waveform at the dc link and then the balanced three-phase inverter output voltage. Therefore, single-reference modulation with interleaved front-end offers higher reliability as compared to proposed in [18-19].

In addition, the circulating current between the bridges is eliminated. Conventional modulation [18-19] suffers from circulating current between the bridges (i.e. through semiconductor devices) causing additional losses.

The objective of this paper is to explain steady-state operation and analysis of two stage HF inverter employing proposed modulation scheme, reported in Section II. Design of the converter has been illustrated in Section III. Analysis and design have been verified by simulation results using PSIM 9.0 in Section IV. Experimental results on a laboratory prototype of 400 W are demonstrated in Section IV to validate the proposed modulation scheme.

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Lmb

1:nHF Tr

C

D

M4a

Lma

1:nHF Tr DR2a

CF

DR1a

DR3a

DR4aD4a

C4a

VinCin

M2a

D2a

C2a

iin

A

B

LF

S2

S1 S3

S4

+

-

Va

Vb+-

+-

VRa

+

-

iina

iinb

M1b

D1b

M3b

D3b

C3b

M1a

D1a

C1aM3a

D3a

C3a

S5

S6

DR2b

DR1bDR3b

DR4b

VRb

+

-

Vdc

3-phaseload

C1b

M2b M4b

D2b D4b

C2b C4b

U V W

ipri,a

ipri,b

im,a

im,b

idcisec,a

isec,b

X

YZ

N

Bridge-a

Bridge-b

Fig. 3. Schematic of the proposed fuel cell inverter system.

II. OPERATION AND ANALYSIS In this Section, steady-state operation and analysis of the

modulation technique have been explained. Two full-bridge converters are interleaved at front-end in parallel input series output to increase the power handling capacity as shown in Fig. 3. Both full-bridges are modulated using identical 6-pulse modulation producing HF pulsating dc voltage Vdc, which is fed to standard three-phase inverter. Modulation of the two stages is planned, developed, and implemented so as to reduce switching losses of inverter while making dc-link capacitorless. Three-phase inverter is modulated to shape this HF pulsating dc link voltage to obtain balanced three-phase sine inverter output voltages of required frequency and amplitude after filtering.

The following assumptions are made for easy understanding of the analysis of the converter: 1) All semiconductor devices and components are ideal and lossless. 2) Leakage inductances of the transformers have been neglected.

3) Dc/dc converter cells are switched at higher HF compared to the inverter. Therefore, current drawn by the inverter, idc remains approximately constant over one HF switching cycle of dc/dc converter.

Magnetizing inductances of the HF transformers are denoted as Lma and Lmb in Fig. 3.

A. Modulation The switch pairs M1a - M2a and M3a - M4a are operated

with complementary signals. Gating signal of M1a and M3a are phase-shifted by DTs, where D is defined as the duty ratio of the switch. By varying D, voltage at the rectifier output can be varied linearly. In the proposed modulation, D is generated by comparing reference signal with carrier signal. Reference signal Vref is a six-pulse waveform that is obtained from the rectified output of three-phase line-line

voltage as shown in Fig. 4. As the name suggests, the reference voltage is having frequency of 6x ac line frequency. These six equal pulses (segments) are flagged as T1 to T6. During each of these pulses, only one leg of the inverter is modulated at HF whereas remaining two legs are steady at their switching state. The modulating sequences of the inverter switches S1 to S6 are given in Table 1, which are compared with carrier waveform to get gating pulses for the devices. During time interval T1, S4 and S5 are on, and S3 and S6 are off. S1 and S2 are modulated at HF by using Vab/Vcb as modulating signal. It can be observed from Fig. 4 that only two (1 leg) of six devices (3 legs) are switched at HF resulting in reduction of number of switching instants in a line cycle. Similar procedure is followed for remaining five pulses. In a complete line cycle, each semiconductor device is switched at HF only for 1/3rd of the line cycle. It is also important to note that devices do not commutate when current through them is at its maximum value. This further reduces the switching losses lower than 33%. Modulation given in Table 1 produces low harmonic distortion of the output waveforms as compared to previous method given in [19] that gives unsymmetrical wave shape.

In the proposed method, exact modulating signals are calculated by considering variation in average dc link voltage in six pulse fashion. This modulation technique is very easy to implement by using three-phase line-line voltages as references shown in Fig. 5. Six-pulse modulating signal is obtained from maximum of absolute value of three-phase references, i.e., rectification of balanced three-phase sine ac signals. This reference along with the carrier waveform decides gating signals for switches M1a - M4a. Interleaving at front-end is easy to scale the power transfer capacity due to the proposed modulation. Switches are modulated in similar fashion with same value of D. Modulation given in Table 1 is implemented for inverter by selecting modulating signal in given sequence.

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A. Steady State Operation The converter operation during different intervals of a

HF switching cycle is highlighted by waveforms shown in Fig. 6. Gating signals of dc/dc full-bridge converters are shown, where each switch is operated at 50% duty ratio and complementary to other switch in the same leg. Whenever the diagonal switch pairs are conducting, say M1a and M4a, input voltage Vin appears across the transformer primary and nVin is reflected on secondary side. On the other hand, when other diagonal pair M2a and M3a are conducting, -nVin is obtained across secondary terminals, where n is the turns ratio of the transformer. Another full-bridge is also operated in similar way applying similar gating pulses to symmetrical devices. Bipolar pulsating voltage is converted to unipolar using diode bridge rectifier circuit. Rectifier outputs from two cells are connected in series to add the voltage level. Current through transformer terminals are shown in Fig. 6.

Fig. 4. Modulating waveforms for the proposed converter-inverter topology as shown

in Fig. 3.

Fig. 5. Schematic of complete modulation implementation.

TABLE. 1. MODULATION SIGNALS FOR SWITCHING OF THE INVERTER.

Fig. 6. Waveforms showing gating signals, voltage and current at essential parts of the

full-bridge converter.

Average value of rectifier output voltage at dc link over a switching cycle is obtained as,

inRbRa VnDVV ⋅⋅== 2 (1)

inRbRadc VnDVVV ⋅⋅=+= 4 (2) where D is duty ratio of the converter.

In the proposed modulation scheme, the duty ratio D is generated from Vref which is a six-pulse waveform. Duty ratio varies between its maximum Dmax and minimum values Dmin for required three-phase output voltage as the Vref varies at 300 Hz. Maximum value of voltage obtained at Vdc corresponds to peak of line to line inverter output voltage is obtained at Dmax and is obtained as,

inpeakXY VnDV ⋅⋅= max, 4 (3)

Where, VXY,peak is the peak of line-line output voltage. Magnitude of output voltage can be varied by varying the reference voltage Vref , which changes the range of operating duty ratio Dmin and Dmax.

B. Switching losses As discussed and explained above, it is clear that devices

of the three phase inverter switch at HF only for 1/3rd of the line cycle. Switch is kept in on-state for 1/3rd of the cycle conducting peak current of output line current when output power factor is unity and in off state for rest 1/3rd of line cycle. Similarly, line current is at its negative peak during off-state of top switch and on-state of bottom switch.

1.4

1.6

Vre

f

0

1.5

0

1

S1

0

1

S3

0 0.005 0.01 0.015 0.02 0.0250

1

Time

S5

mod-Amod-B mod-C

T1 T2 T3 T4 T5 T6

1S , 2S Vab/Vcb 1 1 Vac/Vbc 0 0

3S , 4S 0 0 Vbc/Vac 1 1 Vba/Vca

5S ,6S 1 Vcb/Vab 0 0 Vca/Vba 1

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Devices are switching at HF when the line current crosses zero. Total switching loss in the inverter devices Psw,SPM can be analytically calculated as,

( )∫−

⋅+⋅⋅⋅⋅=12

12

, 61216

S

S

T

TSIOFFONXDC

SSPMsw dtfttiV

TP (4)

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛−⋅⋅+⋅⋅⋅=

2312

, SIOFFONXDCSPMsw fttIVPπ

(5)

Where, TS is the time period of the three phase output voltage, VDC is dc link voltage during switching which is equal to 4n*Vin, iX is the output line current given by IX*sin(wt), tON and tOFF are on-time and off-time of the switch and fSI is the inverter switching frequency.

Switching losses for standard sine PWM, Psw,SPWM is calculated in similar fashion where all the six devices at switched at HF.

( )∫ ⋅+⋅⋅⋅=ST

SIOFFONXDCS

SPWMsw dtfttiVT

P0

, 6116 (6)

( ) SIOFFONXDCSPWMsw fttIVP ⋅+⋅⋅⋅=π2

, (7)

Reduction is switching losses is obtained from (5) and (7),

134.0231

,

, =⎟⎟⎠

⎞⎜⎜⎝

⎛−=

SPWMsw

SPMsw

PP (8)

Switching loss in the inverter devices reduces by around 7.5 times for the proposed modulation method as compared to standard sine pulse width modulation (SPWM).

Based on the above analysis, the design equations for the converter were derived and presented in next Section.

III. DESIGN In this Section, design procedure is illustrated by a

design example for the following specifications: Input voltage Vin = 100 V, output phase voltage VO = 110 V at fO = 50 Hz, rated power Po = 400 W, switching frequency of dc/dc converter fSC = 100 kHz and of inverter fSI = 40 kHz.

(1) Average input current is Iin = Po/(ηVin). Assuming an efficiency η of nearly 95%, Iin = 4.21 A. Each full-bridge is sharing half of the load, Iina = Iinb = Iin /2 = 2.1A.

(2) Maximum value of average voltage at dc-link should be above peak value of line-line output voltage.

VVV odc 27023 =⋅⋅= (9)

(3) Turns ratio of the transformers are designed by considering operating duty ratio of full-bridge converter as 0.4-0.425. From (2), value of turns ratio n is calculated as,

in

dc

VDVn

⋅⋅=

4 (10)

Turns ratio of 1.6 is selected allowing safe margin in case of decrease in input voltage below 100V. Transformer primary needs to carry current of Iin/2 = 2.1A.

(4) Rating of full-bridge converter: Switches M1a- M4a and M1b- M4b are rated to conduct current of Iina = Iinb = 2.1A and rated to withstand voltage of Vin =100V. (5) Rectifier diodes have to be able to block a voltage of nVin and current of Idc given by,

min,dc

Odc V

PI = (11)

Here, Idc ≅ 1.71 A. Voltage rating of rectifier diodes, VDR = nVin = 200 V.

(6) Inverter circuit: Voltage across inverter switches is selected based on the maximum voltage across dc link, which is equal to 2n x Vin. RMS current rating of the switches is same as output current IO. For the given specification, voltage rating is equal to 400V and current rating is 1.71A.

(7) Filter design: Filter inductor is calculated such that voltage drop across the inductor is less than 2% of the nominal voltage during full load condition.

OO

OF If

VL⋅⋅

⋅=π2

02.0 (12)

Where, IO is output current. For the given specifications, LF is obtained as 10 mH. Filter capacitor is calculated from cut-off frequency of the low pass filter. For this application, one tenth of inverter switching frequency fSI is selected as the cut-off frequency. Filter capacitor is calculated as,

FCF Lf

C⋅⋅

= 2241

π (13)

Where, fC is the cut-off frequency of the filter. For fC=4 kHz, capacitor CF is obtained as 0.16µF.

IV. SIMULATION AND EXPERIMENTAL RESULTS The proposed modulation scheme has been simulated

using software package PSIM 9.0.4 for the given specifications. Simulation results are illustrated in Fig. 7 to Fig. 9 matching closely with the theoretical predicted waveforms and results.

Modulation for the inverter devices is derived by comparing modA, modB, and modC waveforms shown in Fig. 7 with the carrier signal of 40 kHz.

Switches are commutated at HF for only one third of the line cycle resulting in significant saving in switching losses. It is also observed that only one of the legs is switching at HF, remaining two device legs being connected to either Vdc (off) or 0 (on). In order to generate pulsating dc voltage at Vdc, semiconductor devices are modulated with varying duty ratio generated from six-pulse signal, Vref shown in Fig. 7.

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Fig. 7. Simulation waveforms showing modulating signals.

Fig. 8. Simulation results showing references (Vab, Vbc and Vca), output phase voltages (Vxn, Vyn and Vzn) and output line current (Ix, Iy and Iz)

waveforms at rated load under normal operating condition.

Fig. 9. Simulation output showing voltages VAB, VCD and Vdc at rated load

under normal operating condition.

Fig. 10. Simulation results showing references (Vab, Vbc and Vca), output

phase voltages (Vxn, Vyn and Vzn) and output line current (Ix, Iy and Iz) waveforms if ‘bridge –b’ fails supplying output power 25% of rated load.

The duty ratio of front end converter varies nearly 15% over frequency of 6x line frequency.

Fig. 11. Simulation results showing references (Vab, Vbc and Vca), output phase voltages (Vxn, Vyn and Vzn) and output line current (Ix, Iy and Iz)

waveforms if ‘bridge –b’ fails supplying output power 50% of rated load.

Fig. 12. Simulation results showing references (Vab, Vbc and Vca), output phase voltages (Vxn, Vyn and Vzn) and output line current (Ix, Iy and Iz) waveforms if ‘bridge –b’ fails at supplying output power rated load.

Fig. 8 shows three-phase reference voltages used to

implement proposed modulation scheme. Figure 8 also presents balanced three-phase output voltages of 110V rms obtained across the load and load currents. LC filter has eliminated HF components resulting in low harmonic contents (distortion) of the inverter output waveforms.

Switches M1a ~ M4a and M1b ~ M4b are controlled using gating pulses generated by comparing Vref with the carrier signal. Whenever diagonal switches are conducting, the input voltage appears across the transformers. During remaining time of the HF switching cycle, voltage across the transformers is clamped to zero. Two identical bipolar voltages are obtained at the secondary of the transformers. These two voltages are rectified to obtain unipolar voltage waveforms. Series connected rectifier output voltage is shown in Fig. 9 as explained in the analysis.

Fig. 10 show the results for power transfer at reduced power if ‘bridge-b’ fails. Owing to failure of a bridge, the output voltage at dc link Vdc is reduced to half. Therefore, the inverter output or motor input voltage is reduced to half and supporting the drive with 25% of the power as shown in Fig. 10 with balanced three-phase output voltages and currents with low distortion. Single-reference modulation still works with excellence as discussed and explained.

0

-1

-2

1

2

Vab Vbc Vca

0

-50

-100

50

Vxn Vyn Vzn

0.025 0.03 0.035 0.04Time (s)

0

-0.5

-1

0.5

1

Ix Iy Iz

0

-50

-100

50

100Vxn Vyn Vzn

0.025 0.03 0.035 0.04Time (s)

0

-1

-2

1

2Ix Iy Iz

0

-50

-100

50

100

Vxn Vyn Vzn

0.025 0.03 0.035 0.04Time (s)

0

-2

-4

2

4

Ix Iy Iz

0

0.4

0.8

1.2modA

0

0.4

0.8

1.2modB

0

0.4

0.8

1.2modC

0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03Time (s)

1.41.51.61.7

Vref

0

-1

-2

1

2

Vab Vbc Vca

0

-100

-200

100

200

Vxn Vyn Vzn

0.01 0.015 0.02 0.025 0.03Time (s)

0-1-2

12

Ix Iy Iz

0

-50

-100

50

100

Vab

0

-50

-100

50

100

Vcd

0.02646 0.02647 0.02648 0.02649 0.0265Time (s)

0

100

200

300

Vdc

5360

It is known that the transformer leakage inductance limits the power transfer capacity from source to load. Theoretically, there is no limit if series inductance between source and load is zero provided components design and selection is done to withstand it. If the HF transformers could be designed with very low leakage inductance, then even a single cell would be able to support nearly rated load.

Fig. 11 and Fig. 12 show the power transfer at 50% and rated load as a result of negligible or very low leakage inductance of the HF transformers. The modulation still works due to single-reference technique and produces balanced three-phase sine output waveforms with low distortion. However, it is clear that the mode changes from high voltage low current to low voltage high current due to failure of one bridge. It is still able to drive the vehicle to home or garage, which adds a valuable feature to the power electronics system in vehicle and improves the reliability making it fault tolerant. In case of other applications, the power electronics system still resumes the power from source to the load and helps to maintain the continuity and thus improve the reliability of power electronics.

A laboratory prototype of 400 W has been tested at Vin = 100 V, and Vo = 110 V ac rms at 50 Hz. Gate signals for both converter and inverter are generated using single Xilinx Spartan-6 FPGA. Single sine lookup table has been used to generate gating pulses to both full-bridge converters and three-phase inverter switches. Hence, synchronization of gating signal is not an issue. Experimental results are demonstrated in Figs. 13-17.

Fig. 13 shows gating signals that are driving top IGBT switches (S1, S3 and S5) of the inverter. It can be observed that inverter devices are switching only for 1/3rd of the line cycle and remain either on (1/3rd) or off (1/3rd) for the rest of the line cycle. It can also be seen from the waveform that at a time only one leg is switching at HF. For bottom switches (S2, S4 and S6), gating signals are complimentary to corresponding leg top switch with a dead gap. Three-phase balanced output voltages Vxn, Vyn and Vzn across the load are shown in Fig. 14. This validates the operation of the proposed modulation scheme and matches closely with the simulation results. Three-phase load currents ix, iy and iz are given in Fig. 15 along with a line voltage Vxy. It justifies the proposed single-reference modulation scheme. Whenever the diagonal switch pairs in front-end full-bridge are conducting, say M1a and M4a, input voltage Vin appears across the transformer primary and corresponding voltage is reflected on secondary side. Similarly -Vin appears across the transformer when other diagonal switches like M2a and M3a are conducting. Transformer primary voltage VAB is shown in Fig. 16. This voltage is stepped up by transformer and rectified by a full bridge diode rectifier to produce a unipolar HF pulsating dc voltage Vdc as shown in Fig. 17 that has envelop of six-pulse waveform. Likewise current drawn by the inverter Idc has similar envelope having frequency of 300 Hz. These waveforms can be seen in HF window in Fig. 17(b) in zoomed form. Voltage across the HF transformer primary winding VAB and current ipri,a

through it are illustrated in Fig. 17. Due to variation in duty ratio as a function of six pulse reference Vref, current through the transformer has bipolar six pulse envelope. The input current drawn from the source is of a 300-Hz frequency with HF components riding over it. The low-voltage electrolytic capacitor placed at the input absorbs this low-frequency pulsation and blocks to appear across the source.

Fig. 13. Experimental waveforms showing gate signals to inverter top switches demonstrating 33% modulation (X-axis: 5ms/div and Y-axis:

10V/div).

Fig. 14. Experimental waveforms of three phase output voltages (X-axis:

5ms/div, Y-axis: 100V/div).

Fig. 15. Experimental result showing of three phase output currents (top,

scale: 0.5A/div) along with the line-line voltage (bottom, scale: 200V/div) (X-axis: 5ms/div).

Fig. 16. Experimental waveforms: VAB (scale: 100V/div), VDC (scale:

200V/div) and IDC (scale: 1A/div) (X-axis: 2µs/div).

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(a)

(b)

Fig. 17. Experimental results (a) voltage across primary of the transformer

VAB (scale: 100V/div), current through primary of the transformer IPRI,A (scale: 10A/div) and output phase voltage VXN (scale: 200V/div) (X-axis: 5ms/div) and (b) VAB (scale: 100V/div), VDC (scale: 200V/div) and IPRI,A

(scale: 5A/div) (X-axis: 2µs/div).

Experimental results demonstrate validation of the proposed SRSPM scheme. It can be observed that the experimental waveforms coincide closely with predicted operating waveforms and simulation results. Though the results have been implemented for lower voltage and low power for verification of the modulation technique, this can be scaled to medium voltage and medium to high power inverter finding applications in electric vehicles, solid-state transformer, and three-phase systems.

V. SUMMAR AND CONCLUSION This paper proposes a novel modulation technique

named SRSPM to control front-end full-bridge converter to generate HF unipolar pulsating voltage waveform at dc link having six-pulse information if averaged at HF cycle over line frequency. Six-pulse is meant for six-pulse waveform that results after rectification of three-phase balanced ac waveforms at 6x of line frequency. It permits the next three-phase inverter devices to switch at HF during 33.33% (1/3rd) of the line cycle and at to stay at steady switching state of ON for 33.33% and OFF for rest 33.33% of line cycle. It results in low average switching frequency or 66.66% reduction in switching transition losses and improved efficiency. Compared to three-phase inverter, reduction in switching loss up to 86.6% is accomplished. It is suitable for high power applications like FCVs and EVs, three-phase uninterruptible power supply, islanded or standalone

microgrid, and solid-state transformer. The proposed modulation eliminates the need for dc-link capacitor and feeds directly HF pulsating dc voltage to three-phase inverter. Experimental results demonstrate the accuracy of the proposed modulation and performance of the system.

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