A 0.4V Ultra Low-Power UWB CMOS LNA

Employing Noise Cancellation

Mahdi Parvizi1, Karim Allidina

1, Frederic Nabki

2 and Mourad El-Gamal

1

1McGill University, 2Université du Québec à Montréal, Montreal, Canada

Abstract—This paper presents an ultra low voltage (ULV), ultra

low power (ULP) and ultra wideband CMOS low noise

amplifier with noise cancelling. A design methodology for

optimizing the trade-off between power consumption and RF

performance for a MOS transistor is employed. A current-reuse

technique is used to lower the power consumption, and an

inductive gm-boosting technique is exploited to increase the gain

and improve input matching at high frequencies. The circuit is

implemented in a 90nm TSMC CMOS technology. Simulation

results demonstrate a 15dB gain, a 6.8GHz bandwidth and a

4.5 -5.3dB noise figure. The power consumption is only 410μW at a 0.4V supply.

I. INTRODUCTION

With the proliferation of wireless sensor network

applications in a myriad of domains such as healthcare,

industry, environmental monitoring and agriculture, ULP

and miniaturized radios have become an active area of

research. Impulse radio ultra wideband (IR-UWB) is a

promising technology that has shown great potential for

ULP, low cost and integrated radio solutions. Accordingly, IR-UWB is suitable for wireless sensor network applications

in which power consumption is the main constraint and

relatively low data rates are required [1]. Furthermore, the

pulsed nature of IR-UWB allows for simple non-coherent

energy detection architectures to be employed, greatly

simplifying the receiver architecture, and reducing the cost

and power consumption of the transceiver.

The low noise amplifier (LNA) is the first active

component in the front-end of the receiver, and is generally

considered as the most power consuming block in non-

coherent IR-UWB receivers. The LNA must provide simultaneous wideband matching, high gain, low noise and

high linearity, all of which requires high power and high

supply voltages. These combined specifications have made

the design of ULP and ULV UWB LNAs a challenging

research topic. Additionally, radio frequency (RF) CMOS

circuits that operate from a low supply voltage are desired

for compatibility with state-of-the-art CMOS processes

where the supply voltage is typically less than 1V. However,

reduced supply voltages pose severe restrictions on the

circuit topologies and the speed of the circuits. A common-gate (CG) transistor can provide wideband

input matching, however, when matched for maximum power transfer its noise figure (NF) cannot be better than

where γ is thermal noise coefficient and α=gm/gd0

[2]. A noise cancelling technique has been used to improve the NF of wideband CG LNAs [3, 4], and this removes the trade-off between matching at the input and the overall noise figure of the LNA. This makes it possible for noise cancelling LNAs to achieve wideband input matching, relatively high voltage gain, and moderately low NF but usually at the expense of high power consumption and high supply voltages [3, 4].

This work is focused on the design of an ULP, ULV, and noise cancelling CMOS LNA using current-reuse and gm-boosting techniques for UWB applications. It is also shown that low power operation and high fT can be achieved simultaneously by biasing the CMOS transistors in the moderate inversion region.

This paper is organized as follows. First, the ULP RF design technique is presented. Then, the proposed UWB LNA and the circuit level implementation are presented and analyzed in section III. Simulation results are provided in section IV and the conclusion is given in section V.

II. LOW POWER RF DESIGN

One approach to minimize power consumption of RF circuits is to bias the transistors in weak inversion region where the value of gm/ID is maximum [5]. However, a transistor biased in weak inversion does not have high fT which would make this approach effective only for circuits whose operation frequency is far below the technology cut-off frequency. Additionally, the effect of parasitic capacitances like Cgs (gate-source capacitance), and Cgd (gate-drain capacitance), must be taken into account at RF frequencies. Therefore, a better figure of merit for RFIC design is presented in [6] where effects of these parasitics are included in fT

.m TRFLP

D

g fFOM

I

(1)

This FOM was introduced for narrow-band designs; however, it is shown in this paper that it is also useful for UWB designs. Fig. 1 depicts FOMRFLP of a NMOS transistor in a 90 nm TSMC CMOS technology versus the inversion coefficient (IC) for a W/L ratio of 600 and a drain-source voltage of 0.2V. The IC is defined in [7] and can be found by

2

1 ,

GS T

T

V V

n UIC ln e

(2)

978-1-4673-5762-3/13/$31.00 ©2013 IEEE 2369

where, VGS is the gate-source voltage, VT is the threshold voltage, n is the sub-threshold slope factor and UT is the thermal voltage, defined by kT/q. The IC is considered a good tool for characterizing the global level of inversion of a transistor. If IC<0.1 the transistor is in weak inversion. If 0.1<IC<10 then the transistor is in moderate inversion and for IC>10 the transistor is in strong inversion. As can be seen in the figure, the maximum FOM occurs in moderate inversion. Selecting an operating point at this optimum region is the basic concept behind the proposed ULP UWB LNA presented here.

III. CIRCUIT DESCRIPTION

This section describes the operating principle of the proposed noise cancelling LNA. The current-reuse noise cancelling structure is presented first. Then, a gm-boosting technique for ULP and ULV LNA design is described.

A. Noise Canceling LNA with Current-reuse

In the conventional noise cancelling LNA topology shown in Fig. 2(a) [3], a CG transistor provides wideband input matching while a common-source (CS) transistor creates a path for noise cancellation of the CG transistor. The wideband input stage of the noise cancelling LNA can be combined with a wideband load to cover a broad band or by a frequency tunable pass band load to operate only at the desired frequency. The benefit of a pass band load is the ability of the LNA to filter adjacent noise or interferers. In addition, this type of noise cancelling LNA architecture realizes single-ended to differential conversion of the input, removing the need for an external balun. This reduces the cost and allows for an improved overall receiver noise figure.

To decrease the current consumption of the noise cancelling LNA this paper proposes a current reuse scheme that is utilized along with a new noise cancelling LNA architecture, shown in Fig. 2(b). The basic idea of the current reuse technique is introduced in [8] and it is altered for use in a noise canceling architecture. The current reuse technique allows the CG and CS branches to share the same current. M1 is a PMOS transistor in a CG configuration to provide wideband 50 Ω input matching, while M2 is a CS NMOS transistor which creates a feed-forward path to cancel the drain current noise of M1. The two branches are AC decoupled from each other by capacitor C1 such that node VX is at signal ground. Therefore, only the DC currents are shared between the two transistors.

The loads of both CG and CS branches are implemented using a parallel RLC resonant circuit. A parallel RL combination was employed for two main reasons: using inductors eliminates the voltage drop across the load so an ULV LNA can be realized, and using resistors reduces the Q factor of the inductors to increase bandwidth of operation at the cost of increased NF. Consequently, inductor L1 resonates with the parasitic capacitance at the drain of M1 with a Q-factor that is determined by resistor R1. The same scenario happens for the load at the drain of M2.

Inductor L3 is chosen to be sufficiently large to act as a current source at the input of M1. Using an inductor instead of a resistor or a transistor for the current source allows the use of a lower voltage supply.

The output balancing criteria is determined using the following formula

1 1 2 2 m mg Z g Z (3)

where the left side of (3) is the gain of the CG stage and the right side is the gain of CS stage. Z1 represents the total impedance at the drain of the CG transistor and Z2 is the total impedance at the drain of the CS transistor. There is a slight difference in the transconductance of M1 and M2 which is due to different sizing and mobility of the devices. It should be noted that higher transconductance for M2 is desirable since it leads to lower NF. Consequently, Z1 is slightly higher than Z2 to satisfy the output balancing criteria. Moreover, the different parasitic capacitances at the output of the CS and the CG stages must be taken into consideration when sizing L1 and L2. Additionally, gm1 has to satisfy the input matching condition such that RS = 1/gm.

The noise factor of this LNA is calculated assuming that the transistors have infinite output impedance and that the gate resistance is negligible for simplicity. The noise factor of this LNA is determined using the following formula

21 1 2 2

2

2 22 2 1 1 2 1

2 2

/1

/ 1 1

m m S

S V

m m S m S

S V S V

g Z g Z RF

R A

g Z g R R R g R

R A R A

(4)

Fig. 1 The figure of merit utilized for low power design at RF frequencies.

0.001 0.01 0.1 1 10 1000

200

400

600

800

1,000

Inversion Coefficient

FO

M (

GH

z.V

-1)

Strong

InversionWeak Inversion Moderate Inversion

M2

M1

L1

L2

R1

R2

L3

RS

VX

Vin

C1

Vout+

Vout-

RS

Rd

M1

Vout+

Rd

M2

Vout-

(a) (b)

Vin

Fig. 2 (a) Conventional noise canceling LNA. (b) Proposed ULV, ULP current-reuse noise cancelling LNA architecture.

2370

where, AV=(gm1Z1+gm2Z2), γ is the MOSFET noise parameter

and = gm/gd0. The second term is the contribution of PMOS transistor, the third term is due to the NMOS transistor, and the last term comes from the load resistors.

B. Inductive gm-boosting Technique

Because of the ULP and the ULV design restrictions and biasing the transistors in moderate inversion region, attaining a high intrinsic fT is not possible in this work. To overcome this challenge, a technique to boost the transconductance of the transistors especially at high frequencies is necessary. The proposed gm-boosting technique involves adding an inductor at the gate of the CG transistor to boost its transconductance at high frequencies without any extra power consumption. To verify this scheme, the effective transconductance (Gm,eff) of the CG transistor is found with and without an inductor at its gate. The Gm,eff of a CG transistor can be found by finding the output current of a device versus the input voltage, and by taking into account the source resistance and parasitic capacitances. The exact Gm,eff of a CG transistor and the high frequency approximation can be found by

,

1.

1

m Tm eff

m S gs S S

gG

g R j C R jR

(5)

From (5), it can be seen that Gm,eff decreases with frequency. However, by adding an inductor to the gate of CG transistor the Gm,eff becomes

, 2,

1 m S gs S g g

mf

s

m e fg R j C R L C

gG

(6)

and at high frequencies this simplifies to

,

1.T

m effS g

GjR L

(7)

Consequently, Gm,eff is boosted at the desired frequency. These simplified models are plotted in MATLAB and shown in Fig. 3. For a CG transistor with gm-boosting, Gm,eff is plotted for multiple values of Lg. As can be seen, Gm,eff decreases with frequency for a conventional CG transistor. However, the proposed gm-boosting technique increases the Gm,eff until the resonance frequency of Lg with Cgs.

The same approach is taken for the CS transistor in the feed-forward path. By adding an inductor in the gate, gm-boosting for the CS transistor can be achieved. By using a similar analysis to the one employed for the CG transistor, the Gm,eff of the CS transistor and its simplified high frequency approximation is given by

, 2

1

1

m Tm eff

S ggs S g gs

gG

jR Lj C R L C

(8)

which is similar to that of the gm-boosted CG transistor.

The proposed gm-boosting technique also improves the input matching condition, especially at high frequencies. The input impedance of the proposed circuit is given by

21 1 1 1

21 1 1 1 1 1

22 2

2

1 1

1 1

1||

o g gs

in

m gs o o g gs

g gs

gs

g Z L CZ

g j C g Z g L C

L C

j C

(9)

where gO1 is the output conductance of the M1 transistor. This equation shows that the effect of parasitic capacitances at the input will be reduced by adding L4 and L5.

The complete circuit schematic of the proposed LNA is illustrated in Fig. 4. The input signal is applied to the source of M1 and the gate of M2, which are biased in the moderate inversion region. Inductors L1, L2 and L5 are on-chip spiral inductors while L3 and L4 are implemented using bond wire inductances to reduce the area of the LNA. Capacitor C1 is an on-chip capacitor.

IV. SIMULATION RESULTS

The circuit is designed in a TSMC 90 nm CMOS technology and simulated using SpectreRF. BSIM4 models are used for the transistors, and parasitics are included in the inductor and capacitor models. The input matching (S11), reverse isolation (S12), output matching (S22) and voltage gain (Av) of the LNA are plotted in Fig. 5. The maximum gain of the LNA is 15dB and its 3-dB bandwidth is between 3.2GHz and 10GHz. The S11 is well below -10dB in this band thanks to resonance at the input and inductive gm-boosting. The S22 is below -10dB as well, and the S12 is less than -35dB. The noise figure of the proposed LNA is shown in Fig. 6. The NF varies between 4.5dB and 5.3dB across the bandwidth.

Fig. 3. Gm,eff of a CG transistor with and without gm-boosting.

M2

M1

L1

L2

R1

R2

L3

L4

L5

RS

VX

Vin

M3

M4

Buffer

M3

M4

Buffer

C1

Vout-

Vout+

Fig. 4 Circuit schematic of the proposed ultra low voltage, low power current-reuse LNA with gm-boosting.

0 2 4 6 8 100.008

0.009

0.01

0.011

0.012

0.013

0.014

Frequency (GHz)

Eff

ective G

m

With gm

boosting

Without gm

boosting

Increasing Lg

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It is important to examine the performance of the noise canceling LNA at different process corners. Fig. 7 illustrates the contribution of the drain noise current of the CG and CS transistors in the bandwidth of operation. As can be seen, the noise contribution of CG transistor is very small (less than 1.5%) between 3GHz and 5GHz. However, it gradually increases at high frequencies. This is due to a phase imbalance between the two outputs which increases at high frequencies and reduces the drain current noise cancellation.

Table I presents a comparison of this work with other LNAs in the literature. A figure of merit expressed in (10) is employed to compare the overall performance of the LNAs. It can be seen that this LNAs consumes much less power and requires a lower supply voltage when compared to other works, while simultaneously achieving a higher FOM. However, it should be noticed that a small variation in performance will be noted when the LNA is fabricated and measured.

10

[ ] [ ]20

( 1)

average

dc average

Gain lin BW GHzFOM log

P mW F lin

(10)

TABLE I. PERFORMANCE SUMMARY AND COMPARISON WITH PRIOR

PUBLISHED WORKS

This work [9]*

[10]*

BW (GHz) 3.2-10 2.6-10.5 3.1-10.6

Power (mW) 0.41 0.99 9

Vdd (V) 0.4 1.1 1.2

Gain (dB) 15 7.9 16.5

NF (dB) 4.5~5.3 5.5~6.5 2.1~2.9

IIP3 (dBm) -2~-7 NA 8.5~-5.5

Technology 90 nm 130 nm 130 nm

FOM 31.5 15.9 15.7 *Measurement results.

V. CONCULSION

This paper presented an ULP and ULV UWB CMOS noise canceling LNA. A design methodology for optimizing the trade-off between RF performance and power consumption for UWB applications was applied. The proposed LNA utilizes a current-reuse structure, a noise canceling architecture and an inductive gm-boosting technique to realize ULP and ULV operation. The circuit is designed in 90 nm CMOS technology from TSMC, and it achieves a 15dB gain, a 6.8GHz bandwidth and a 4.5dB to 5.3dB NF with a power consumption of only 410μW from a 0.4V supply.

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Fig. 5 Simulated voltage gain, S11, S12 and S22 of the proposed LNA.

Fig. 6 Simulated noise figure of the proposed LNA.

Fig. 7 Noise contribution of the CS and CG transistors indicating the effectiveness of noise cancellation at different process corners.

2 4 6 8 10 12-60

-50

-40

-30

-20

-10

0

10

20

Frequency (GHz)

Av,

S11,

S22,S

12 (

dB

)

S12

S22

S11

Av

2 4 6 8 104

4.5

5

5.5

6

6.5

7

Frequency (GHz)N

ois

e F

igu

re (

dB

)

3 4 5 6 7 8 9 100

10

20

30

40

50

Frequency (GHz)

Nois

e C

ontr

ibution (

%)

TT

FF

SS

SF

FS

Common-Source Transistor

Common-Gate Transistor

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