NOVEL COMPRES SORS IN THE

SUB -THRESHOLD REGIME

Himani Jawa Dept. of Electronics and Communication

Bharati Vidyapeeth' s College of Engineering New Delhi

himanijawa@gmail.com

Abstract- With the growing scale of integration, design of circuits with power consumption has become the primary motivation for the development in sub-threshold region. The circuits operating in sub threshold results in ultra-low power due to the use of leakage current which is in the order of nano amperes as the operating current. In many high speed applications, compressors are used to perform the partial product addition needed during multiplication. In this paper two architecture for 4:2 and 5:2 compressors in the sub threshold region is proposed. The paper aims at comparing the power consumption, delay and the power­delay product (PDP) of the two architectures in the sub threshold region. All the simulations have been performed using O.18um CMOS technology parameters.

Keywords- Subthreshold; compressor; Power Delay Product; Power

Consumption

1 . INTRODUCTION

In recent years, MOS devices have been scaled down into nanometer region wherein the sub-threshold conduction has gained significant importance [ 1 ] . The scaling of MOS devices leads to scaling of power supply voltages which influences the power consumption. Sub-threshold conduction has become an inevitable choice due to need of ultra-low power and reliable devices.

Multiplication is the most basic arithmetic operation in microprocessors and digital signal processing applications to perform convolution and filtering. Hence, the demand for high speed, low power multipliers has become prominent. A multiplier can be divided into three stages : partial product generation stage, partial product addition stage and the final addition stage. In the first stage, the multiplicand and the multiplier are multiplied bit by bit to generate the partial products. The second stage involves the use of compressors and is crucial for determining the speed of the multiplier. Hence the design of low-power compressors is advantageous [2] . This paper presents the architectures of 4 :2 and 5 :2 compressors in the sub threshold region by using 1 80nm

978-1 -4799- 1 607-8/1 3/$3 1 . 00©201 3 IEEE 424

Kirti Gupta Dept. of Electronics and Communication

Bharati Vidyapeeth' s College of Engineering New Delhi

kirtigupta22@gmail.com

CMOS technology. The structure of the paper is as follows : In section 2, the operation of the MOS in the sub threshold region along with its advantages is presented. Section 3 focuses on two architectures for both 4 :2 and 5 :2 compressors . Finally in section 4, the performance of the two architectures for a compressor is compared through simulation in terms of power dissipation, delay and power-delay products . Section 5 concludes the paper.

2 . MOSFET IN SUBTHRESHOLD REGION

Sub-threshold region of a MOSFET is the region wherein the MOSFET is supposed to be off but the MOSFET conducts a very small amount of current, that is, sub-threshold leakage current, Isub ' It is the leakage current that flows between the source and drain terminal of the MOSFET when the transistor is in the sub-threshold region, or weak inversion region, that is, for gate-to-source voltages below the threshold voltage. As the MOSFETs have been scaled down, the sub-threshold leakage consumes nearly 50% of total power consumption [4] . The reason is that power supply voltages have also been scaled down along with the scaling of the MOSFET, in order to reduce the dynamic power consumption. So to maintain the performance of the MOSFET, the threshold voltage has to be scaled down in proportion with the supply voltage. The decrease in threshold voltage leads to exponential increase in the sub-threshold leakage current. Sub-threshold current Isub is characterized by the equation,

Isub = 10 exp ( � ) [ 1 - exp (-V dS) (1 ) n.VT VT Where Vgs is the gate-to-source voltage,Vds is the drain-to-

source voltage, n is the sub-threshold slope factor and VT is

temperature equivalent of voltage (k T ) where k is the

q

Boltzmann constant, T the absolute temperature, and q the

electron charge. The factor n of a long-channel uniformly doped device is calculated as

n = 1 + Cb (2) cg

where Cg and Cb are the gate and bulk capacitances respectively.

A MOSFET operating in subthreshold region offers several advantages. The MOSFETs operating in this region generate low levels of the drain current, thereby creates a high-value resistor. These MOSFETs show low dynamic power consumption due to the lowering of power supply and the drain current [5] . Based on these advantages, we propose the implementation of compressors in the subthreshold region to design low-power multipliers .

3 . COMPRESSORS

In a multiplier, there is an intermediate stage that involves the addition of partial product. This is the most crucial stage as it determines the speed of the multiplier. A compressor is used to design the intermediate stage, thus high performance compressor design is essential. A compressor reduces N rows of partial products in two rows wherein N represents inputs of the present stage . Different architectures for compressors in sub-threshold region for 4 :2 and 5 :2 compressors are discussed below:

3. 1 4:2 COMPRESSOR

The 4 :2 compressor compresses 5-bit of partial product into 3 -bits . The block diagram of a 4 :2 compressor is shown in Fig. l . The 5-bits consist of four input bits (X" X2, X3 , X4) of the present stage and a carry from the previous stage (Cin) [3 ] . The three output bits consist of two bit output for the present stage (sum, carry) and one bit output for the next stage (Cout) . The basic equation of 4 :2 compressor is :

X , X , X , X . C 'N

4 : 2 CO M P RESSOR

SUM CARRY C OUT Fig. 1 : Block diagram of 4 :2 compressor

425

Carry S u m Fig. 2 : 4 :2 compressor: Architecture I

(a)

(b) Fig. 3 . MOS implementation of (a) XOR3 (b) CGEN

Here we propose two architectures for 4 :2 compressor. The architecture 1 is a two level implementation. The block diagram is shown in Fig. 2. It has two 3 -input XOR gate (XOR3) and a 3 -input carry generator circuit (CGEN). The functionality of the XOR3 and CGEN can be expressed though following Boolean equations.

XOR3 = Xl (}) X2 (}) X3 (4) CGEN = (Xl ()) X2 ) X3+ XlX2 (5)

where X l , X2 and X3 are the inputs. The MOS implementation of a XOR3 and a CGEN is shown in Fig. 3a and Fig. 3b respectively.

Architecture 2 represents a multi-level implementation. The block diagram is shown in Fig. 4. It has four 2-input XOR gates (XOR2) and a two 2 : 1 multiplexer (MUX). The functionality of the XOR2 and MUX can be expressed though following Boolean equations.

XOR2 = XI Ef) X2

MUX = Xl sel+ selX2

(6)

(7) where X l , X2 and sel are the inputs . The MOS implementation of a XOR2 and a 2: I MUX is shown in Fig. 5a and 5b respectively.

3. 2 5:2 COMPRESSOR

A 5 :2 compressor compresses 7-bits of the partial product into 4-bits . The block diagram of a 5 :2 compressor is shown in Fig. 6. The seven partial product bits consist of five input bits (X) , X2, X3 , X4, Xs) of the present stage and two carries from the previous stage (Cinh Cin2) [3 ] . The four output bits consist of two bit output (sum, carry) for the present stage and two bit (Cout) , Cout2) for the next stage. The basic equation of 5 :2 compressor is :

X) + X2 + X3 + X4 + Xs + Cin1 + Cin2 =Sum + 2 . (Carry + Coutl + Cout2) (8)

The two architectures for 5 :2 compressor are presented. The architecture I is a two level implementation. The block diagram is shown in Fig. 7a. It has three 3 -input XOR gate (XOR3) and three 3 -input carry generator circuit (CGEN) as shown in Fig. 3 . Architecture 2 is a multi-level implementation. The block diagram is shown in Fig. 7b. It has five 2-input XOR gates (XOR2) and a four 2: I multiplexer (MUX) as shown in Fig. 5 .

Fig. 4 . 4 : 2 compressor: Architecture 2 v�

:=::::::E=�- OUTPUT

(a)

426

v 0 0

Sef ---4 r- x ' se l ---4 F- X '

O UTPUT

se l ---1 �� x, ---1 � x,

(b) Fig. 5. MOS implementation of (a) XOR2 (b) 2 : 1 MUX

5 : 2 COM P RESSOR

SUM CARRY COUTl C OUT2

Fig. 6 :Block diagram of 5 :2 compressor

Carry S u m

(a)

(b)

Fig. 7. 5 :2 compressor: a) Architecture 1 b) Architecture 2

4. SIMULA nON

This section fIrst verifIes the proposed architectures for 4 :2 and 5 :2 compressors . Thereafter, the performance of the two architectures presented for both the compressors . All the simulations are performed by using 0 . 1 8 /lm TSMC CMOS technology parameters and with a supply voltage of 600 m V. The waveforms of the input and the output nodes for architecture I of both the compressors are shown in Fig. 8 . It can be observed that both the architectures confIrms to the functionality. The waveforms of other architectures are not shown for the sake of brevity.

I 1 0 ! I I , � I ! �O

I (a)

(b)

Fig. 8. Simulation waveforms for architecture 1 (ARCH- l ) of: a) 4 :2 compressor b) 5 2 compressor

The simulation results for different architectures of 4 :2 compressors are listed in Table I . The performance of the two architectures is compared in terms of delay, power and power­delay product (PDP). It is observed that architecture-2 (ARCH-2) shows a maximum delay reduction of 82.5 percent with respect to the architecture- l (ARCH- I ) . Similarly, the ARCH-2 has reduced power consumption and PDP by 8 .66 percent and 77.06 percent on comparison with ARCH- I of a 4 :2 compressor. The simulation results for the two architectures of 5 :2 compressors are listed in Table II. The results clearly indicate that the architecture-2 based on multi­level implementation has improved performance in comparison to architecture- I .

427

TABLE 1 -- PERFORMANCE COMPARISON OF 4 '2 COMPRESSOR �E ARCH-l ARCH- 2 PARAMETER

SUM 6 . 1 8 1 .09

DELAY CARRY 2.22 1 .49

(ns) COUT 2.3 1 1 . 54

POWER (nW) 1 9.278 17 . 607

PDP (1O-18J) 1 1 8 . 145 27. 1 14

TABLE 11-- PERFORMANCE COMPARISON OF 5 '2 COMPRESSOR

� ARCH-l ARCH- 2

PARAMETER

SUM 6 .6 1 0 .67

CARRY 3 . 1 7 3 . 1 0 DELAY

2.45 1 .45 (ns) Co UTI

COUT2 2.7 1 .62

POWER (nW) 1 57 .07 3 .00

PDP (10-18 J) 1 039. 1 1 9 .33

4. CONCLUSION

This paper presents the design of compressors in subthreshold region. The two architectures for 4 :2 and 5 :2 compressors along with their MOS implementations are proposed. The proposed architectures are functionally verifIed and their performance is compared in terms of delay, power consumption and PDP. It is found that the architecture-2 based on multi-level implementations is more effIcient.

REFERENCES

[ I ] E. Vittoz and J. Fellrath, "CMOS analog integrated circuits on weak inversion operation," IEEE J. Solid State Circuits, vol. SC-12, pp. 224-23 1 , June 1 977 . [2] P. O. Gopineedi, H. Thapliyal, M. B . Srinivas, and H. R. Arabnia, "Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations," in Froc. oj ESA, 2006, pp. 1 60-168 . [3 ] G. Caruso, O. Di Sclafani, "Analysis of compressor architectures in MOS current-mode logic" in Froc. ojiCECS, 2010, pp. 1 3 - 16, 20 10 . [4] R. Chao, Advanced Linear Devices Inc, "Exploiting subthreshold MOSFET behavior in analog applications" in EON, Vol. 57 No. 3 , pp. 20, February 2012 . [5 ] C.H. Chang, 1. Gu and M. zhang, "Ultra Low-Voltage CMOS 4-2 and 5-2

Compressors for Fast Arithmetic Circuits," IEEE Trans. On Circuits and Systems -I, Vol 5 1 , No 10 , pp. l985- 1997, October 2004. [6] W. Ma and S . Li, "A New High Compression Compressor for Large Multiplier," in Froc. oj fCSlCT, pp. 1 877-1 880, 2008. [7] S .Veeramachanemi, K.Krishna, L. Avinash, S .R. Puppola, M.B. Srinivas, "Novel architectures for high-speed and low-power 3 -2, 4-2 and 5 -2 compressors," in Proc. OJ VLSfD, pp .324-329, 2007.