Design  for  Reliability  for  Low  Power  Digital  Circuits  

Sriram  Kalpat  Qualcomm,  USA  

   Lower   power   digital   circuits   in   cellular   phones,   laptop   or   tablet   computers   have  critical  power   consumption   limitations.  Power   consumption  at  process   corners   can  vary   as  much  as  50%.   In  order   to  optimize  high-­‐speed   logic   circuit   designs   for   low  power  needs,  we  need  to  accurately  predict  device  to  product  aging  across  process,  temperature  and  voltage  corners.  In  this  talk,  we  focus  on  the  impact  of  BTI  aging  at  corners,  the  Fmax  guardband  and  its  trade-­‐off  with  power  and  performance.    

978-1-4799-2217-8/14/$31.00 ©2014 IEEE