A Low-Voltage High-Gain Wide-Bandwidth Class-AB Differential Difference Amplifier

Fuding Ge, Brent Thomas

Intel Corporation, Chandler, Arizona, USA fuding.ge@intel.com

Abstract— This paper presents a CMOS low-voltage high gain and wide bandwidth differential difference amplifier (DDA). It is based on a robust two-stage class-AB amplifier with cascode Miller compensation. The first stage is a folded-cascode OTA with improved wide swing biasing circuit and the second stage is class-AB output stage biased with translinear circuit. The two input pairs can be either NMOS or PMOS pair. It achieves a DC open loop gain of 80 dB and unity-gain bandwidth of 20 MHz with 380 µA current drawn from a single 1.5V power supply in 0.13 µm CMOS. Its application for current feedback instrumentation amplifier is discussed.

I. INTRODUCTION Differential difference amplifier (DDA) is a versatile

analog building block [1]-[2], which, for example, can be used to build instrumentation amplifier for sensor applications [3]-[4]. To achieve the fully benefits and advantages of DDA, the designed DDA needs to have high gain and wide bandwidth, just as a high performance operational amplifier does. Most of the published DDA designs, on the hand, are based on relative simple two-stage op-amp [4]-[5], which can not achieve high gain, especially in the sub- or deep sub-micron CMOS technologies, or the design is relative complex [6], thus may be not compact and robust.

This paper presents a low-voltage, high-gain, wide-bandwidth class-AB DDA, which is suitable for deep sub-micron CMOS technology. It is based on a very popular and robust two-stage class-AB amplifier design, with an additional input pair. The first stage is a high-gain folded-cascode OTA and the second stage is a push-pull class-AB output stage, biased by a simple translinear circuit [7], with rail-to-rail output capability. The first high-gain folded-cascode OTA stage is biased with an improved wide-swing current mirror biasing circuit [8]. For some applications, the input common-mode voltage for one input pair may go to one supply rail, for example Vdd, while the other pair may go to the other power supply rail, for example, Vss. To achieve this type of pseudo-rail-to-rail input capability, the two input pairs can use different channel transistors, one input pair consists of NMOS, while the other consists of PMOS.

Fig. 1. DDA Symbol [1]

This paper is organized as follows. Section II describes the design considerations for the proposed DDA. Section III presents simulation results. Section IV describes its applications for instrumentation amplifier. Finally the paper concludes at Section V.

II. DIFFERENTIAL DIFFERENCE AMPLIFIER DESIGN For clarification, the DDA symbol is shown in Fig. 1 [1].

It has for input terminals, which can be classified into two ports, positive port VPP-VPN and negative port VNP-VNN.

The schematics of the proposed class-AB DDA are shown in Fig. 2. Fig. 2 (a) shows a DDA with two NMOS input pairs while Fig. 2 (b) shows a DDA with one PMOS input pair and one NMOS input pair. The other parts are same for the two DDAs. Obviously the two input pairs, based on applications, can be two PMOS input pairs as well.

The improved wide swing biasing circuitry for the folded-cascode OTA consists of transistors from Mb1 to Mb12. The long channel transistors Mb7 and Mb8 are implemented with stacked short channel transistor to get better stable performance over voltage, temperature and process variations. Transistors from Mb13 to Mb18, and transistors M8a, M8b, M9a and M9b form the translinear biasing circuitry for the push-pull class-AB output stage. For single-ended output, transistors M8b and M9b are not necessary. But with these two transistors, we get a more symmetric circuitry.

1176978-1-4244-2342-2/08/$25.00 ©2008 IEEE.

(a) DDA with two NMOS input pairs

(b) DDA with one PMOS input pair and one NMOS input pair

Fig. 2. Schematics of the proposed DDA

The output stage of the differential difference amplifier is realized by a push-pull output stage biased at class-AB state. It has the rail-to-rail output capability. The DDA also utilizes cascode Miller compensation [9], by connecting

compensation capacitor Cc to the amplifier’s output and the sources of the cascode transistors M4c and M6c. In this way we eliminate right-half plan (RHP) zero issue, thus no resistors are needed to cancel or move the location of the

1177

RHP zero. It is also worth to note that there are complementary current mirrors, formed by connections of M3c drain to M3 gate, M5c drain to M5 gate. The extra current mirror is not necessary for single- ended output, but it provides a more symmetric circuit and better high frequency performance.

III. DDA SIMULATION RESULTS AND DISCUSSIONS The proposed differential difference amplifiers are

designed in 0.13 µm CMOS technology with a single 1.5V power supply. Fig. 3 shows the results of AC simulations. Fig. 3(a) shows the simulation test bench for the DDA shown in Fig. 2(b). The negative port, the PMOS input pair, was shorted together and connected to Vss thus it provides no gain. Fig. 3(b) shows the simulated open loop gain and phase with common mode voltage of 1.0 V at the positive port, the NMOS input pair. It can achieve approximately 80 dB DC gain and a phase margin of about 65 degree, with RL=100 KΩ and CL=1.0 pF. The DDA, including its biasing circuit, draws about 380 µA current from a single 1.5V power supply.

Fig. 4 shows DC gain versus the input common mode voltage of the positive port (NMOS input pair of Fig. 2(b)) and the negative port (PMOS input pair). When positive port was tested, the common-mode voltage of the negative port was kept at 0.1 V. When the negative port was tested the positive port was kept at 1.0 V. From the figure we can see the positive port input common mode range (NMOS input pair) is from 0.4 V to 1.7 V and the negative port input common mode voltage range is from -0.2 V to 1.0 V. They are beyond the power supply rails. For some applications this beyond-rail common mode range is very helpful.

IV. DDA APPLICATION: INSTRMENTATION AMPLIFIER One of the applications of the proposed DDA is for

instrumentation amplifier (In-Amp). The popular classic three opamp based In-Amp is shown in Fig. 5(a). It uses three amplifiers, as its name suggested. Opamp1, opam2, R1 and R2 forms a differential amplifier. R3, R4 and opam3 forms a difference amplifier. Normally the differential amplifier provides all or most of the gain while the difference amplifier provides unit or a small portion of the overall gain. This In-Amp has two issues when used for sensor applications. First the input common mode range is quite limited [10]. Second the amplifier’s common mode rejection ratio (CMRR) is dependent on the matching between the two R3-R4 resistor strings, which may require trimming or other techniques to get high CMRR [11].

To overcome these disadvantages of the three opamp In-Amp, an alternative, named indirect current feedback In-Amp, becomes “extremely popular” [10]-[11]. Fig. 5(b) shows the DDA based In-Amp [1]. It is actually an indirect current feedback In-Amp. Its gain can be expressed as:

1

21

2

1

RRR

GGGain

m

m += (1)

Where Gm1 and Gm2 are the transconductance values of the input and feedback ports, respectively. Compared with the three opamp In-Amp, the gain of the DDA based In-Amp depends not only on resistor ratio, but also the input port transconductance values. Since the transconductane is dependent on several design parameters, such as biasing current, input pair transistor size, type of the transistor -NMOS or PMOS, as well on the input and feedback common mode voltage values, it becomes difficulty to determine the exact gain value of the In-Amp by design. This is one disadvantage of this DDA based In-Amp. But for most applications, this is not a concern since normally the system will incorporate some types of gain programming, such as by simply tuning the resistor values of R1 and R2 shown in Fig. 5(b).

(a)

(b)

Fig. 3. AC simulation testbench (a) and gain, phase VS frequency (b)

Fig. 4. DC gain VS the input common mode voltage

1178

(a)

(b)

Fig. 5. Classic three-opamp IA (a) and DDA basaed IA (b)

V. CONCLUSIONS This paper presents the design and simulation results of a

simple, rugged differential difference amplifier with high gain and wide bandwidth. It is built upon a high gain folded-cascode OTA core. Improved wide-swing bias circuitry is developed to improve circuitry robustness. Complementary PMOS and NMOS input pairs are used to implement pseudo rail-to-rail input common voltage range and a push-pull output stage biased at class-AB state is used to implement rail-to-ail output capability. The application of the proposed differential difference amplifier is an indirect current feedback instrumentation amplifier, which can have wide, even beyond the power supply rails, input common mode range.

ACKNOWLEDGMENT The authors thank Yueming He, Syed Naqvi for helpful

technique discussions and Bobby Nikjou for overall project support.

REFERENCES [1] E. Sackinger, W. Guggenbuhl, “A versatile building block: the CMOS

differential difference amplifier,” IEEE J. Solid State Circuits, Vol.22 (2), 2000 PP: 287- 294

[2] S.-C. Huang, M. Ismail, and S. R. Zarabadi, “A wide range differential difference amplifier: A basic block for analog signal processing in MOS technology,” IEEE Trans. Circuits Syst.-II, Vol. 40(5), 1993, PP. 289-301

[3] G. Nicollini, C. Guardiani, “A 3.3-V 800-nVrms noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique,” IEEE J. Solid State Circuits, Vol.28(8), 1993, PP: 915-921,

[4] P. K. Chan, K. A. Ng, “A CMOS analog front-end IC for portable EEG/ECG monitoring applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, Fundamental Theory and Applications, Vol 52(11), 2005, PP:2335 – 2347

[5] H. Alzaher, M. Ismail, “A CMOS fully balanced differential difference amplifier and its applications,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol.48(6), 2001, PP:614 – 620

[6] Chung-Chih Hung, M. Ismail, K. Halonen, V. Porra, “Low-voltage rail-to-rail CMOS differential difference amplifier,” Proceedings of 1997 IEEE International Symposium on Circuits and Systems, Vol.1, 9-12 June, 1997, PP:145 - 148

[7] R. Gregorian, “Introduction to CMOS Op-amps and Comparators,” John Wiley and Sons, 1999, Chapter 4.

[8] D.A. Johns, K. Martin, “Analog Integrated Circuit Design,” John Wiley and Sons, 1997, Chapter 6.

[9] B.K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. Solid State Circuits, Vol.18 (6), 1983, PP629-633

[10] Maxim Application Note, “Three is a Crowd for Instrumentation Amplifiers,” Avaiblable at http://www.maxim-ic.com/appnotes.cfm/appnote_number/4034

[11] B.J. van den Dool, J.K. Huijsing, “Indirect current feedback instrumentation amplifier with a common-mode input range that includes the negative raill,” IEEE J. Solid State Circuits, Vol.28(7), 1993, PP: 743-749

1179