Fig. 1. Block diagram of typical SAR-ADC.

Fig. 2. Typical ECG signal.

Abstract — A moving binary search tree based successive ap-proximation register analog-to-digital converter (SAR-ADC) dedicated for low power biomedical data acquisition system is presented. By performing the conversion based on the previous results, the required ADC conversion cycles is reduced signifi-cantly leading to great saving in power consumption. Simulation results based on typical electrocardiograph (ECG) signals show that the proposed SAR-ADC saves 52.6% of conversion cycles for a 10-bit SAR-ADC, corresponding to a power saving of about 45% as compared to its conventional counterparts, while maintaining the same resolution and accuracy.

I. INTRODUCTION he successive approximation register analog-to-digital converter (SAR-ADC) is popular in the biomedical data

acquisition systems due to its medium-to-high resolution and low power consumption. The block diagram of a typical SAR-ADC is shown in Fig. 1. The dominant power-consuming blocks in the ADC are comparator and digital-to-analog converter (DAC). There are different ways to reduce the power in the SAR-ADC. Applying low power circuit technique is one of the common approaches in minimizing the power. The introduction of low power comparators and DAC structures leads to significant savings in power as re-ported in [1] and [2]. The other alternative in lowering the power is to develop new search algorithms and associated control logics for the ADC. In this paper, we propose a search algorithm and new control logic for the ADC to mini-mize the required conversion cycles and achieve low power.

The paper is organized as follows. Section II explains the idea moving binary search tree and the design of the associ-ated control logic. Section III compares this control logic with its conventional counterpart in terms of conversion cy-cles and power consumption, based on a 10-bit ADC exam-ple. Section IV draws conclusion.

II. DESIGN OF THE SAR CONTROL LOGIC Considering a typical biomedical signal, such as ECG in

Fig. 2, most of its components are located at very low fre-quencies while leaving few components with small magni-tude at higher frequencies. This slow-varying characteristic is very common to biomedical signals. Furthermore, the sam-

pling rate of the ADC is often designed to be higher than Nyquist rate in practical to ensure no aliasing and also keeps noise from folding back into signal band. As a result, only a

small portion of ADC bandwidth is utilized. Such a slow-varying nature limits the difference between two consecutive sampled inputs to a small range as compared to the full scale ADC.

With conventional SAR control logic, an n-bits ADC re-quires at least n conversion cycles to complete the signal conversion [3]. Using binary search algorithm, the ADC suc-cessively approximates the sampled input signal one bit in a conversion cycle, from MSB to LSB. This method is not effi-cient for converting slow-varying signal because the ADC often repeating same redundant procedure but ends up with similar or even same results among MSB bits.

Therefore, we propose replacing the conventional SAR control logic with new control logic to reduce the required conversion cycles and power down the power-consuming parts to minimize the overall power consumption. By incor-porating the proposed control logic, the ADC starts the con-version from previous signal level and performs successive approximation only within the range required to cover the change in signal level. Consequently, the conversion process starts at a point nearer to the target and thus minimized the redundancy in conventional binary search tree.

As compared to conventional fixed binary search tree, this proposed structure is referred as “moving binary search tree”

Wen-Sin Liew, Libin Yao and Yong Lian Department of Electrical and Computer Engineering, Faculty of Engineering

National University of Singapore, Singapore Email: elelws@nus.edu.sg, libinyao@nus.edu.sg, eleliany@nus.edu.sg

A Moving Binary Search SAR-ADC for Low Power Biomedical Data Acquisition System

T

This work was supported by Singapore Agency for Science Technology and Research (A*STAR) under Thematic Strategic Research Programme: Embedded & Hybrid System II.

646978-1-4244-2342-2/08/$25.00 ©2008 IEEE.

Fig. 3. Examples on conventional binary search tree and proposed “moving

binary search tree”.

Fig. 4. Simplified block diagram of the proposed SAR control logic.

Fig. 5. Conversion cycles of ADC using proposed control logic.

because it may start at an arbitrary point and has arbitrary size.

Fig. 3 illustrates the idea of moving binary search tree us-ing a 6-bit ADC as an example. The ADC full scale (FS) is defined from 000000 to 111111. Assume that the previous value of ADC output is 010111 and the current value is 001111. For conventional binary search (traces marked as “A” in Fig. 3), it always starts from half of full scale (FS/2) and requires 6 comparisons to obtain the final result. The operation is:

100000→010000→001000→001100 →001110→001111→001111

On the other hand, the moving binary search tree (traces marked as “B” in Fig.3) starts from previous result and is able to obtain the same result in 4 comparisons. The opera-tion is:

010111→010011→010001→010000→001111 In this case, the size of the moving binary search tree is 4 and the saving achieved is 2 conversion cycles. In other words, previous signal level determines the starting points. The size of the search tree is equal to the required conversion cycle(s).

The starting point of a moving binary search can be placed at any point in the binary search tree, which in turn deter-mines the conversion cycle(s). One of examples illustrating such a case is the trace marked as “C” in Fig. 3. It starts from 111010 to obtain the result of 110000 within 5 comparisons.

To realize the moving binary search tree, the SAR control logic of ADC in Fig. 1 has to be modified. Fig. 4 shows the simplified block diagram of the proposed SAR control logic that implements moving binary search algorithm. Since only digital SAR control logic is replaced while the analog blocks (i.e. DAC, T/H and comparator) remain the same, introducing the proposed design has minimum effect on the original ADC linearity, resolution, effective number of bits (ENOB), etc.

The proposed SAR control logic consists of five main blocks, i.e., cycle counter, range calculator, summer, inter-mediate latch and output latch. The following parts explain these five blocks based on a 10-bit ADC example.

A. Cycle Counter Cycle counter is used to synchronize the ADC operation. It

is implemented by a ring counter. Fig. 5 shows an example about the conversion cycles of an ADC using the proposed control logic. The conversion cycles are very similar to its conventional counterpart except for the followings:

- DAC is reset to previous signal level at the beginning, instead of FS/2.

- There are n conversion cycles reserved for n-bits ADC; however, the ADC only operates throughout the number of cycles equals to size of moving binary search tree.

- The difference between signal levels has to be calculated to estimate the size of moving binary search tree required for next conversion.

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Fig. 8. 1 bit full summer unit.

Fig. 9. 10-bit full summer.

Fig. 6. Difference-calculating circuit.

Fig. 7. Decision-making circuit.

B. Range Calculator Range calculator consists of a difference-calculating circuit

and a decision-making circuit. The difference-calculating circuit in Fig. 6, implemented by full adders, finds the abso-lute difference between two consecutive signal levels using the complement notation and then passes the result to deci-sion-making circuit. The decision-making circuit in Fig. 7 decides the size of binary search tree required to cover the changes in signal level for the following conversion.

The following example illustrates the mechanism of the circuits. For instance, the two consecutive signals are:

ID [10] = 0010110000 (current signal) D [10] = 0010111010 (previous signal)

With the difference-calculating circuit in Fig. 6, the addition is performed using complement notation. The operation is:

ID [10] + !D [10] = 0 1111110101 Here, the MSB is defined as Sign while remaining bits are defined as result, R:

Sign = 0 R [10] = 1111110101 The absolute difference can be obtained by:

(Sign) XNOR (R [10]) = 0000001010 Then, the output of decision-making circuit will be (here, assuming all middle-column registers in Fig. 7 have output of 0 for the time being):

Q [10] = 0000111111 This result means that the moving binary search for next con-version has estimated size of 6. Together with the output from cycle counter, this result decides that the ADC can be powered down for the first 4 conversion cycles while operat-ing only for the remaining 6 conversion cycles.

The decision-making circuit is the core of the proposed idea because it determines the size of moving binary search tree. On one hand, underestimating the size causes inaccuracy

in subsequent conversion. On the other hand, overestimating the size results in less power saving. Therefore, it has to be designed accordingly based on the application, ADC sam-pling rate and input signal characteristics.

For example, a “2-bit stepping” has been used to imple-ment the decision-making circuit in Fig. 7. As a result, an x-bit difference (absolute difference that can be written using only x bits in binary form) triggers a tree size of (x+2), in-stead of x. In other words, the difference is multiplied by 4 times. Also, additional registers are inserted in the middle of the decision-making circuit to store the previous estimated search tree size. Among the previous and current search tree size, the larger one is used for next conversion. Although the above two precautions limit the saving achieved by ADC, but they ensures total accuracy for any kind of input signal within the ADC bandwidth.

Therefore, one may tailor the circuit to achieve more sav-ing. For instance, using only “1-bit stepping” and removing the middle-column registers lead to more saving but reducing the effective bandwidth of ADC.

C. Summer To implement the moving binary search tree which uses

previous result as starting point for conversion, the proposed search tree requires to move “up or down” at any level of the tree. Therefore, a summer which performs both addition and subtration is needed. Fig. 8 shows the circuit for 1 bit full summer unit while Fig. 9 shows the configuration for a 10-bit full summer. During the successive approximation process, the summer performs addition at the selected bit if the comperator result is logical “1” (i.e. sampled analog input > DAC input) or subtration at the selected bit if the comperator result is logical “0” (i.e. sampled analog input < DAC input).

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Table I Saving on Conversion Cycles (10-bits ADC)

Input Signal # of Conversion Cycles Required

# of Conversion Cycles Saved

Constant (any level) 3.00 7.00 Ramp (Slope=1) 4.00 6.00 Sine (1Hz, FS) 4.37 5.63

Typical ECG (FS) 4.74 5.26 ECG (PhysioNet) 4.30 (average) 5.70 (average)

Fig. 12. MATLAB simulation result on ECG signal.

Fig. 10. Intermediate latch.

Fig. 11. Output latch.

D. Intermediate Latch and Output Latch Intermediate latch shown in Fig. 10 drives the DAC during

the conversion. In addition, it retains its result after each conversion for range calcultor and provides this result as the starting point of moving binary search tree in subsequent conversion. The multiplexers in Fig. 10 serve to limit the range of moving binary search tree to avoid the search tree from going beyond upper or below lower limits of the ADC full scale range.

During each conversion process, the output latch (Fig. 10) first provides the preceding result for range calculator and then latch the current result from intermediate latch.

III. SIMULATION RESULTS

A. System Simulation A 10-bit ADC model has been developed in MATLAB.

Simulations are performed using several input signals, in-cluding constant, ramp, sine, typical ECG signal and 48 sets of ECG records available on PhysioNet [4]. The results in terms of conversion cycles are summarized in Table I. These results conclude that the proposed control logic is able to achieve saving on both general and ECG signals.

Fig. 12 illustrates one of the simulation results on ECG signal. The ADC output is accurate as compared to its input. Also, the numbers of cycles used for each conversion tell that saving is achieved for the slow-varying parts using the pro-posed control logic. The proposed control logic requires only 4.74 conversion cycles, instead of 10 conversion cycles, for typical ECG signal. This is equals to a savings of 52.6%, in terms of conversion cycles.

B. Circuit Simulation SPICE simulations of a 10-bit ADC in a CMOS 0.35µm

process are performed to verify the power saving achieved by the proposed control logic as compared to its conventional

counterpart. Simulations are done by replacing only the con-trol logic while keeping all other parts identical. The pro-posed control logic itself requires larger die area and con-sumes more digital power as compared to conventional con-trol logic. However, it reduces the power consumption of ADC by 50% in comparator and 30% in DAC. Overall, ADC using the proposed control logic achieves a power saving of about 45% for typical ECG inputs.

IV. CONCLUSION A new search algorithm and associated control logic have

been proposed for the SAR ADC in low power biomedical data acquisition system. The idea behind the control logic is discussed and implementation example is shown. The proposed design achieves 52.6% savings in terms of conversion cycles on typical ECG signals, which translates a power saving of about 45% in a 10-bit SAR ADC.

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Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007.

[2] B. P. Ginsburg and A. P. Chandrakasan, “An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC,” in Proc. IEEE Int. Symp. Circuits and Systems, 2005, vol. 1, pp.184-187.

[3] R. J. Bakar, CMOS Circuit Design, Layout, and Simulation. Wiley-IEEE Press, 2005.

[4] Goldberger AL, Amaral LAN, Glass L, Hausdorff JM, Ivanov PCh, Mark RG, Mietus JE, Moody GB, Peng CK, Stanley HE. PhysioBank, PhysioToolkit, and PhysioNet: Components of a New Research Re-source for Complex Physiologic Signals. Circulation 101(23): e215-e220 [Circulation Electronic Pages; http://circ.ahajournals.org/cgi/con-tent/full/101/23/e215]; 2000 (June 13).

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