978-1-4244-1694-3/08/$25.00 ©2008 IEEE

Physical Layer Design Automation for RFID Systems

Shenchih Tung and Alex K. JonesUniversity of Pittsburgh

shst8@pitt.edu, akjones@ece.pitt.edu

Abstract

While RFID is starting to become a ubiquitous technol-ogy, the variation between different RFID systems still re-mains high. This paper describes a design automation flowfor fast implementation of the physical layer component ofnew RFID systems. Physical layer features are describedusing waveform features, which are used to automaticallygenerate physical layer encoding and decoding hardwareblocks. We present automated implementations of five pro-tocols related to RFID including Manchester encoding forultra high frequency (UHF) active tags, Pulse Interval en-coding (PIE) for UHF passive tags, and Modified Millerencoding for lower frequency RFID tags. We have targetedreconfigurable devices to allow changes in the design andcompared these implementations with a standard cell ASICtarget.

1 Introduction

Radio Frequency Identification (RFID) systems have be-come a ubiquitous technology with applications includinglogistics, supply chain management, library item tracking,medical implants, road tolling, building access control, avi-ation security, and homeland security. RFID systems con-sist of Radio Frequency (RF) tags and RF readers or inter-rogators. The tags consist of integrated circuits and an RFantenna. A wide range of extensions such as memory, sen-sors, encryption, and access control can be added to the tag.The interrogators query the tags for information stored onthem, which can include items like identification numbers,user written data, or sensory data.Multiple RFID standards exist [2, 6, 10–12] for RFID

hardware, software, and data management including activebattery powered tags and passive RF energy harvesting tagswith frequencies ranging from 125 kHz to 2.4 Ghz. How-ever, most of the RFID systems are being deployed forclosed loop applications and use either proprietary proto-cols or non-intersecting standards with non-reusable tagsand readers. RFID specifications and standards are often

vague enough to create compliant tags that cannot inter-operate among vendors. Thus, in many applications, RFIDtag and reader hardware and software must be specificallydesigned for each particular application, and must be phys-ically modified or re-designed every time the specificationfor the current application is adjusted, as new applicationsare introduced, and/or the standards are modified, new stan-dards are developed, and new compliance testing is intro-duced. This keeps the overall design time long and the sys-tem costs high.This paper presents an RFID design automation system

and power estimation system that allows the design, opti-mization, and verification of new RFID specifications andstandards. This technique also allows the merging of two ormore standards or specifications for interoperability amongstandards and backward compatibility. The resulting RFIDdevice consists of an automatically generated controller andphysical layer hardware block that can interface with exist-ing RF circuitry and antennas.Basic RFID systems, either readers or tags, contain three

major components: an antenna/air interface, a physicallayer encoder and decoder, and a transaction layer con-troller. In this paper we describe a design automation flowfor the physical layer component of the RFID system. Thedesign methodology allows the specification of waveformfeatures of the encoding, which are captured in a textualformat. These features are then used as inputs to parameter-ized hardware blocks and combinedwith automatically gen-erated customized hardware blocks. The result is automati-cally generated encoding and decoding hardware blocks.The physical layer design flow also integrates with a de-

sign automation flow for the transaction level of the RFIDsystem [13, 15–17] and integrated with a commercial off theshelf air interface to create a complete RFID system. Anoverview of the design automation flow is shown in Figure 1with the physical layer design automation highlighted.The remainder of the paper is organized as follows: Sec-

tion 2 contains backgroundmaterial on research and relatedwork pertaining to RFID. The physical layer design automa-tion flow is presented in Section 3 including details on thetextual representation of the waveform in Section 3.1, a de-

1

RFID Tag

RFID Macros and Behavior

RFID Physical Layer Description

RFID Compiler

RFID Physical Layer Generator Interface

VHDL

VHDL

Backend CAD FPGA

COTS Air Interface

Figure 1. Overview of the RFID design au-tomation flow.

scription of the interface with the waveform features libraryin Section 3.2 and an explanation of the final synthesis pro-cess for VHDL generation in Section 3.3. Results are pre-sented in Section 4. Finally conclusions are related in Sec-tion 5.

2 Background and Related Work

There has been an explosion of interest in RFID in therecent years. Some of the open issues in the RFID do-main are the existence of multiple standards, use of highfrequency (HF) or ultra high frequency (UHF), use of nearfield or far field powering and communication, handling ofstored data and their formats, tag orientation, reader colli-sion [5], range, cost, and security concerns [21]. For ac-tive tags, maximizing battery life is an important concern.Recent research has been focused on finding solutions forsome of these issues.Recent advancements in tag hardware contribute to im-

proved range and power consumption [13], improved tagantenna design [4, 22], packaging and tag orientation. Forthe performance characterization of the RFID systems un-der active interference, a test protocol is presented in [20]and its effectiveness is verified. For RFID readers, a solu-tion is developed for the problem of Tx/Rx isolation at thephysical layer [19].Another issue is that proprietary hardware and software

are used in specific application domains. These devicesmust be physically modified or re-designed for adjustmentsin the specification, introduction of new applications, and/ormodifications to relevant standards. A customizable RFIDtag can handle variations in standards and requirements asthey are developed with a significantly shorter time to mar-ket than current ad hoc techniques such as the prototypingdescribed in [14].

3 RFID Physical Layer Design Automation

One of the main components of an RFID system com-munication is the physical layer protocol employed to en-code bits of information. The physical layer features for

the bit encoding mechanism vary across various RFID stan-dards. For example, the ISO 18000 Part 7 active tag stan-dard specifiesManchester encoding [9] to transmit encodeddata RFID interrogators and tags [10] while the ISO 18000Part 6C standard defines different physical layer features oftransactions among readers and tags. Pulse-Interval Encod-ing (PIE) [11] is utilized to encode data transmitted fromreaders to tags and either FM0 [1] or Miller encoding [3]is utilized to encode the backscattered data from tags backto readers [11]. Additionally, many other possible physicallayer encodings can be considered for RFID communica-tions.This section describes how the physical layer decoder

and encoder blocks can be automatically generated from ahigh-level specification of the protocol. This design flowis described in Figure 3. The user describes the waveformfeatures of the encoding scheme such as edge transitions,level detection, pulse width detection, etc. from a phys-ical layer specification. The user can then combine oneor more wave features to represent bits or groups of bits.The physical layer synthesis tool then automatically gener-ates hardware blocks for encoding and decoding the signalin VHDL. These VHDL descriptions are created from thecombination of predefined parameterized hardware librariesand automatically generated hardware blocks for detectingand generating the waveform features in the encoding.

RFID standardBit coding specification

Physical layerwaveform feature

library

SynthesisPhysical layer

waveform features

EncoderVHDL

DecoderVHDL

Figure 2. The generation flow for an RFIDdata encoder and decoder.

3.1 Specification of Waveform

The user describes the features of the encoding schemeusing a textual representation. This representation is createdfrom a physical layer specification such as an RFID stan-dard. It may include edge transitions, level detection, pulsewidth detection, etc. After this file has been created, it be-comes the input into the physical layer synthesis tool shownin Figure 3. The textual file contains three major segments:(1) declaration of the waveform to encode data values, (2)declaration of the preamble waveform, and (3) transmissioncharacteristics for serial to parallel conversion.Manchester encoding [9] is a fixed-bit-window encod-

ing scheme specified in ISO 18000 Part 7 for transactionsamong active RFID readers and tags. The waveforms ofencoded bit ’0’ and bit ’1’ are illustrated in Figure 3(a).The waveform for encoding a bit as either ’0’ or ’1’ is de-

scribed in Figure 4. Sig represents the non-return to zero(NRZ) value of the signal. The keyword after describesthe delay from the beginning of a bit window. The lengthof the bit window is specified by a period T. Changes inthe signal are represented by an & with a non-zero afterparameter. Finally, A specifies how accurately each mea-surement must be as a percentage of T. In the example fromFigure 4, a ’0’ is represented by a 50% duty cycle clockwith a falling edge in the middle of the bit window. Theedge must be within 12.5% of the total period, which means6.75% of the period before or after the expected transition.In this case the transition occurs at 18 ± 2.43µs. A ’1’ issimilar except with a rising edge.

Bit 0

Bit 1

50%

50%

T = 36µs

50%

50%

T = 36µs

(a) Manchester

Bit 0

50%

T = 36µs

50%

Bit 150%

T = 36µs

50%

or

or

(b) Differential Manchester

Figure 3. Continuous waveform for bits ’0’and ’1’ of NRZ encodings.

’0’: Sig = ’1’ after 0 us & ’0’ after 18 us;T = 36 us; A = 12.5%;

’1’: Sig = ’1’ after 0 us & ’1’ after 18 us;T = 36 us; A = 12.5%;

Figure 4. Textual description of ManchesterEncoding

Differential Manchester encoding shown in Figure 3(a)is a modification of Manchester encoding used most promi-nently in token ring networks [8]. At first glance, Manch-ester and Differential Manchester encodings are indistin-guishable as they both require a transition in the middle ofa bit window for synchronization, and may or may not havea transition at the edge of a window. However, Differen-tial Manchester determines its value by examining the level

between windows. As shown in Figure 3(a), if there is antransition between windows this encodes a ’0’ and if thereis no transition this encodes a ’1’.To support this case, we add an Lprev condition to our

waveform representation as shown in Figure 5. Depend-ing on the previous level, our description describes a levelchange for a ’0’ encoded bit and no level change for a ’1’encoded bit. The if statement determines which waveformto consider based on Lprev.

’0’: if Lprev = ’0’ then Sig = ’1’ after 0 us& ’0’ after 18 us;

if Lprev = ’1’ then Sig = ’0’ after 0 us& ’1’ after 18 us;

T = 36 us; A = 12.5%;

’1’: if Lprev = ’0’ then Sig = ’0’ after 0 us& ’1’ after 18 us;

if Lprev = ’1’ then Sig = ’1’ after 0 us& ’0’ after 18 us;

T = 36 us; A = 12.5%;

Figure 5. Textual description of DifferentialManchester encoding.

Pulse-Interval Encoding (PIE) and FM0 encodings aretwo different encodings used in the ISO 18000 Part 6C stan-dard. These encodings are shown in Figure 6. PIE is usedfor the data transmission and FM0 is used for backscatteringthe response, through absorption or reflection of the trans-mitted RF energy.The physical layer characteristics of PIE are shown in

Figure 6(a). Encodings for both ’1’ and ’0’ are based on anactive high pulse followed by a fixed with space called PW.The length of the pulse determineswhether a ’1’ or ’0’ is en-coded. Thus, the period T is different for each value. Unlikeprevious encodings, there is a large amount of flexibility inthe pulse lengths to make a valid PIE encoded value.For PIE encoding, in the textual representation shown in

Figure 7, we introduce the error keyword that allows atransition to take place within a range of times. For exam-ple, 7.5 us error 1.6 us means that the transitioncould occur anywhere from 5.9 µs to 9.1 µs. This is differ-ent from the A which corresponds to jitter associated withthe RF transmission. For the PIE encoding described in theISO 18000 Part 6C standard, there are three possible peri-ods for encoding the values, each is described in a separatestatement in Figure 7. In some cases, the period itself mayfall within a range, which is described by the error key-word.The physical layer encodings for FM0 are shown in Fig-

ure 6(b). Unlike PIE, FM0 is a fixed period encoding. Thedata rate of FM0 can be one of several discrete values as

Pulse0

Pulse1

PW

PW

Bit ‘0’

Bit ‘1’

T0

1.5 T0 < T1 < 2.0 T0

(a) Pulse-Interval encoding (PIE) encoding.

Bit 0

Bit 1

T = {6.25, 3.9, 3.1, 1.5} µs

50%

50%

or

or

00 or

01or

10

11

or

or

(b) FM0 encoding.

Figure 6. Continuous waveform for bits ’0’and ’1’ of PIE and FM0 encodings.

specified by the ISO 18000 Part 6C standard, including 160,256, 320, and 640 kbps. The corresponding bit window pe-riods are 6.2, 3.9, 3.1, and 1.5 µs with the error toleranceof 7%, 10%, 10%, and 15%, respectively. To encode a ’0’,there must be a transition at the middle of a bit window. Toencode a ’1’ there is no transition within a bit window, how-ever, between two adjacent bits, there must be a transitionat the edge of the bit window.The textual representation of FM0 is shown in Figure 8.

The description for FM0 is similar to how DifferentialManchester is described except that each value has four dif-ferent representations corresponding to each of the four datarates. Also the encoding for ’1’ is simpler, as it does nothave a transition within the bit window and as such has no& in the waveform description.Modified Miller encoding [18] is an encoding scheme

that is often employed in near field communication, or com-

’0’: Sig = ’1’ after 0 us & ’0’ after 3.55 userror 0.65 us;

T = 6.25 us; A = 1%;

’1’: Sig = ’1’ after 0 us & ’0’ after 8.3 userror 2.2 us;

T = 10.95 us error 1.55 us; A = 1%;

Figure 7. Textual description of Pulse-IntervalEncoding (PIE).

’0’: if Lprev = ’0’ then Sig =’1’ after 0 us& ’0’ after 3.1 us;

if Lprev = ’1’ then Sig =’0’ after 0 us& ’1’ after 3.1 us;

T = 6.2 us; A = 7%;

’1’: if Lprev = ’0’ then Sig =’1’ after 0 us;if Lprev = ’1’ then Sig =’0’ after 0 us;T = 6.2 us; A = 7%;

Figure 8. Textual description of FM0 Encod-ing.

munication of 10 cm or less [7]. Modified Miller encodinghas a low pulse either at the beginning of the bit window toencode a ’0’ or the low pulse is delayed by half a period toencode a ’1’. However, if a ’0’ is proceeded by a ’1,’ the’0’ is encoded with no low pulse at all. This is shown inFigure 9.

T = 9.4µs

1bit 1/2bit 1/2bit 1/2bit 1/2bit 1bit

bit ‘0’ bit ‘1’bit ‘1’ bit ‘0’ after bit ‘1’

4 µs 4 µs

Figure 9. Continuous waveform for bits ’0’and ’1’ of Modified Miller encoding.

To represent this in our text, we introduce the new fieldVprevwhich corresponds the previously encoded value. Inthe example from Figure 10, the modified Miller encodingis shown for a period of 9.4 µs. To encode a ’0’ we eithersee a pulse at the beginning of the window if the current bitwas proceeded by a ’0’ or no pulse if proceeded by a ’1’.The encoding for ’1’ does not specify a Vprev value.The preamble in a transmission alerts the system that a

transmission packet is beginning. It typically includes a se-quence of several pulses that are different from the encodedvalues in the encoding. The preamble must be matchedexactly before any data transmission can commence. Fig-

’0’: if Vprev = ’0’ then Sig = ’0’ after 0 us& ’1’ after 4 us;

if Vprev = ’1’ then Sig = ’1’ after 0 us;T = 9.4 us; A = 5%;

’1’: Sig = ’1’ after 0 us & ’0’ after 4.7 us& ’1’ after 4 us;

T = 9.4 us; A = 5%;

Figure 10. Textual description of ModifiedMiller Encoding.

ure 11 shows an example preamble using a textual pream-ble description starting with a 15 µs pulse followed by 5 µspulses separated by 10 µs. A typical preamble could con-tinue for several more pulses.

preamble: pre = ’1’ after 0us & ’0’ after 15us& ’1’ after 10us & ’0’ after 5us &’1’ after 10us & ’0’ after 5us....;

Figure 11. Preamble text representation ex-ample.

RFID standards may also specify transmission protocolsbetween readers and tags. Thus, corresponding transmis-sion characteristics must be declared. For example, thetransmission protocol defined in ISO 18000 Part 7 speci-fies that an RFID reader transmits the least significant bit(LSb) first within a byte and sends the most significant byte(MSB) first within a packet. Each byte is followed by a stopbit within a packet. The transmission order determines thesequence of the serial-to-parallel process for receiving andthe parallel to serial sequence for responding.The textual description of each protocol ends with trans-

mission characteristics. For example, the characteristics forISO 18000 Part 7 are shown in Figure 12. This declaresthat in the byte, the LSb is first, in the packet the MSB isfirst, each byte contains 9 bits, and one of these bits is astop bit. Thus, a complete physical layer description filecontains a waveform description, preamble description, anda transmission characteristics description.

transmission: bitOrder=least; byteOrder=most;byteSize=9; stopBits=1;

Figure 12. Serial transmission characteris-tics.

3.2 Waveform Features Library

The physical layer waveform feature library in Fig-ure 3 is a collection of basic hardware-based componentscorresponding to various waveform features. For exam-ple, this set contains a hardware-based edge detector, sam-pling counter, sampling registers, serial-to-parallel hard-ware blocks, first-in-first-out (FIFO) blocks, and other basicblocks as predefined components in the library. These com-ponents are programmable and designed to fit different userdefined parameters specified in the textual description fromSection 3.1. A hardware-based edge detector, for instance,can be used for detecting only a raising edge, only a fallingedge, or either edge. Similarly, a sampling counter can varybased on different sampling rates corresponding to the dif-ferent data toggling rates and/or different duty cycles of bitdata in the description.Waveform variables are parameters that are converted

from the waveform description file. These parameters areused to describe the physical layer characteristics of a en-coding mechanism in the way that the waveform featureshardware blocks can understand. Thus, the synthesis pro-cess translates the textual description into the parametersfor the feature library.A bit window period is a simple example of a waveform

characteristic. A bit window can contain a transition at aparticular time during the period. Similarly, the direction ofthis transition is another characteristic. From Figure 3(a),the Manchester encoding requires a 50% duty cycle wave-form with a period of 36 µs where the direction determinesthe value. A ’1’ has identical features with a ’0’ except thatit is composed of a rising edge at the middle of a bit win-dow as opposed to a falling edge. Because the waveform isa continuous wave, a transition may also occur at the edgeof two adjacent bits depending on the values of these win-dows.The bit rate for a waveformwith a period of 36 µs is 27.7

kbps. Because of the 50% duty cycle, a transition occurs atthe middle of a bit window and logic levels may change be-tween bit windows. Therefore, the data signal toggling rateis 55.4kbps. The sampling rate (fs) must be least two timesfaster than the toggling frequency (ft) of the target signal:fs = 2 × ft. Since the data signal toggling rate is 55.4kbps(ft) the minimal sampling rate is 110.8kbps, or four timesoversampling. However, the A parameter of the descriptiontells us the typical fluctuation that might occur in the sig-nal, which was specified as 12.5%. Thus, a minimum eighttimes oversampling should be used for edge detection andsynchronization.An overview of the general waveform detection circuit

is shown in Figure 13. This circuit contains a preamble de-tection circuit, an edge detection circuit used for synchro-nization with the incoming waveform, a timer circuit for

signaling the controlling state machine to change states, asampling register file for converting levels and edges intodecoded bit values, and a serial to parallel converter forbuilding bytes from the incoming bits. The system clockspeed is also variable based on the required sampling by thecircuit.

Edge

Detector

Edge_out .

Timer Sampling_clk .

Sync_reset .

t0 .

t1 .

tn-1 .

Sampling

Registers

(1st & 2nd level

sampling points )

Sampling_clk .

Data In .

Feature_type .

Serial_to_Parallel

&

Bit Counter

Sampling_clk .

Bit_value .

Byte .

Previous_Value .

FSM

Sampling_clk .

Edge_out .

Sync_reset .

t0 .

t1 .

tn-1 .

Bit_count .

Samp_en1 .

Samp_en2 .

Shift_en .

Bit_count_en .

Data_In .

Sampling_clk .

Samp_en1 .

Samp_en2 .

Shift_en .

Bit_count_en . Bit_count .

Previous_Value .

Bit_value . Feature_type .

start .

Figure 13. General waveform detection cir-cuit.

The data transmission begins after a valid preamble isdetected by the start signal. The edge detection circuitshown in Figure 14 is used to keep in synchronization withthe incoming waveform. Every system cycle in which thevalue changes, it signals the timer that an edge has occurred.

XOR

Figure 14. Edge detection circuit.

The timer circuit shown in Figure 15 controls the sam-pling times to check for levels or value changes in the in-coming waveform. The timer circuit contains a counter thatcounts system cycles until its next sampling window. Thus,the hardware library contains parameters for the number oftime points n to sample, the number of cycles to count be-tween each sample N0, N1, ..., Nn−1, and the bit width ofthe counter which is log2 max(N).The timer signals become inputs into an automatically

generated finite state machine (FSM) controller circuit. TheFSM uses the timer signals and the sampling registers blockto determine the actual encoded values. The sampling reg-isters circuit, shown in Figure 16, samples two data values

Counter

Array of time points

t2 time

t1 time Match t1

Match t2

tn-1 timeMatch tn-1

Figure 15. Timer circuit schematic.

when signaled by the controller and reports back whetherthere has been a rising edge (’0’ followed by a ’1’), a fallingedge (’1’ followed by a ’0’), or a constant level ’1’ or’0.’ Based on these values, the controller traverses states tomatch one of the bit conditions specified in the textual de-scription. It can also base this on one or more previous val-ues seen in the serial stream with the previous valuesignal.

Sampling Register

SamplingRegister

samp_en1

sample_v1

samp_en2

Data_In

Data_In

FeaturesLookup-table

to FSM

sample_v2

Feature_type

Figure 16. Sampling registers circuitschematic.

The controller uses the synchronization signalEdge out to tell the timer when to reset with theSync reset signal. For cases where the bit window isnot fixed, a bit may be determined before all timers haveexpired as with PIE encoded values of ’0.’ The controllercan reset the timer early in these cases to begin looking forthe next bit.

Finally, once a bit is determined it is fed into the serialto parallel circuit. This circuit, shown in Figure 17, hasparameters such as the number of bits per byte and the di-rection of shifting. For MSb first ordering the circuit shiftsbits into the register from the left and for LSb first order-ing the circuit shifts bits from the right. When buffering thewhole packet, a similar shifting technique is used for mostand least significant bytes (MSB and LSB).

L-shift or R-shift (including stop bits)MSb LSb

FIFO or LIFO(LSB) (MSB)

Byte

Figure 17. Serial-to-parallel circuit schematic.

3.3 Physical Layer Synthesis and VHDLGeneration

The synthesis process from the textual description is pri-marily based on discovering sampling points based on thewaveform properties. For example, consider the modifiedMiller encoding from Figure 9. The basic waveforms for ’0’and ’1’ with an inverse pulse indicate sampling both duringthe pulse and outside the pulse. The synthesis process firstselects sampling points in the center of a level region, thusat 2 µs and 6.7 µs for a ’0’ and at 2.7 µs, 6.7 µs, and 9.05 µsfor a ’1.’ First, the 9.05 µs is discarded because the signalis high for all three descriptions. 6.7 µs is retained directlybecause it matches both the ’1’ and ’0’ directly. The 2 µsand 2.7 µs values are determined to represent the same sam-pling window as they are within stable regions for both the’1’ and ’0’ waveforms. As a result, a value within the rangeof 2 to 2.7 may be selected for a sampling point.The controller FSM is generated to detect different se-

quences of features for each encoded bit in a similar man-ner as a numeric sequence detector. For example, if thereis a rising edge between the samples, it is a ’0,’ a fallingedge indicates a ’1,’ and a constant level high is a ’0.’ Bothversions of ’0’ can be checked against the previous value.For a PIE encoding (Figure 6(a)), there are three sam-

pling points to consider. This is demonstrated for the firstdescription for each ’0’ and ’1’ from Figure 7. Accordingto the description, a falling edge occurs between 2.9 and 4.2µs making this a “invalid detection region.” Thus for a ’0,’the sampling points are 1.45 µs and 5.225 µs. Because theperiod is not fixed for a ’1’ and the “invalid detection re-gion” and period completion time overlap, the system canmove into active sampling mode. Because a falling edgehas not occurred by 4.2 µs, one must occur between 6.1and 10.5 µs, therefore a timer indicates when 6.1 µs haveelapsed, then the FSM looks for an edge before a timer in-dicates 10.5 µs. Finally, upon seeing a second edge, theFSM begins a new bit window.The process for encoding these values into the appropri-

ate encoding is a much simpler subset of the detection pro-cess. The process requires a parallel to serial block comple-mentary to the serial to parallel block. Each bit waveformis generated with a very simple controller FSM that uses

timers to traverse states and each state outputs one particu-lar level. This is a fairly straightforward conversion processfrom the textual representation.The VHDL code generation is the final phase of the syn-

thesis flow. The structure of the block is shown in Fig-ure 13. Several of the libraries included are parameterizedwith VHDL generic constructs for specified parametersincluding the timer and serial to parallel blocks. The FSMcontroller is entirely generated by the synthesis engine us-ing a generic for the number of timer signals to include.

4 Results

Hardware was generated for the five encodings, Manch-ester, differential Manchester, PIE, FM0, and modifiedMiller. We implemented these hardware instantiations onseveral different reprogrammable targets we use for RFIDprototyping including a Xilinx Spartan III 400 FPGA, anActel Fusion AFS90 flash-based FPGA, and a Xilinx Cool-runner II CPLD. The Spartan III was selected because wehave a credit card size prototyping boardwith this device fordemonstration. The Fusion was selected because it is rel-atively low power and contains non-volatile programmingbits and memory for passive prototyping. The CPLD wasselected because of its favorable power properties. We alsosynthesized these designs into standard cell ASIC netlistsfor comparison.Performance and area estimates were made from post

synthesis, placed and routed netlist simulation of the de-signs. Power estimation was completed using stimuli fromthe simulation with vendor supplied tools. For the ASICimplementation Area and performance estimates are fromDesign Compiler, power estimates are from post synthesissimulation using Mentor Graphics Modelsim and analysisusing Synopsys Primepower for a 0.16 µm technology.Results for the physical layer synthesis flow are shown

Table 1 with manual results shown in parenthesis for com-parison. Details on the encoders have been omitted becausetheir hardware is trivial compared to the decoders for eachtype of encoding. Based on our studies, the automaticallygenerated designs are very close to manually generated de-signs and in most cases are more efficient.The Manchester and Differential Manchester decoders

have similar architectures. The size and power consumptionare very close to each other. These decoders also require rel-atively low sampling rates of between 1 and 10 MHz. Themodified Miller encoding requires a similar area as Manch-ester encoding but requires considerably more power likelydue to the ten times higher sampling frequency. FM0 andPIE encoding requires significantly higher area (2-3 timesmore) than the other encodings. Due to the increased sam-pling rate and complexity, these encodings require signifi-cantly higher power consumption.

Based on our experiments, the automatically generateddecoding designs on average require approximately 20%less area than hand generated designs. However, in somecases, the simplified state machines (i.e. the decoder con-trol units) that lead to this area reduction actually in somecases cause an increase in energy consumption. As a result,the reconfigurable devices provide a 0.1 to 2mW level so-lution, while the ASIC provides a 0.6 to 5µW solution fordecoders generated by our tool.

Table 1. Statistics of decoder blocks withthe automatically generated value followedby manual design value.

Man Diff Man PIE FM0 MMFreq 1 MHz 1 MHz 10 MHz 4 MHz 10 MHzXilinx Spartan 3 XC3S400: area in cells, power in mWArea 108 (108) 103 (98) 192 (216) 109 (113) 119 (105)Power 0.02 (0.02) 0.02 (0.01) 0.31 (0.39) 0.10 (0.12) 0.25 (0.31)Altera Fusion AFS90: area in cells, power in mWArea 140 (153) 146 (206) 276 (306) 151 (159) 159 (142)Power 0.10 (0.18) 0.11 (0.20) 1.25 (1.02) 0.40 (0.51) 1.06 (1.10)Xilinx Coolrunner II 256: area in gates , power in mWArea 314 (310) 329 (293) 625 (586) 335 (315) 372 (356)Power 0.18 (0.18) 0.19 (0.18) 1.98 (2.13) 0.65 (0.62) 1.62 (1.53)Oki 0.16µm cell-based ASIC: area in µm2 , power in µWArea 3585 (4128) 3998 (4323) 10713 (13414) 5134 (6058) 7299 (7218)Power 0.61 (0.47) 0.63 (0.49) 4.31 (3.98) 1.74 (1.94) 3.71 (4.51)

5 Conclusions

This paper presents a physical layer design automationflow intended for RFID tags. The RFID Physical LayerGenerator automatically generates physical layer encodingand decoding blocks in hardware through the descriptionof waveform features of the encoding. We have imple-mented and compared five different physical layer encod-ings: Manchester, differential Manchester, PIE, FM0, andmodified Miller encodings.

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