+ All Categories
Home > Documents > [IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada...

[IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada...

Date post: 04-Dec-2016
Category:
Upload: farid
View: 223 times
Download: 0 times
Share this document with a friend
6
Power Hardware-in-the-Loop Testing of a 500 kW Photovoltaic Array Inverter James Langston, Karl Schoder, Mischa Steurer, Omar Faruque, John Hauer, Ferenc Bogdan Center for Advanced Power Systems Florida State University Tallahassee, Florida, USA [email protected], [email protected], [email protected], [email protected], [email protected], [email protected] Richard Bravo Southern California Edison Los Angeles, Califoia, USA [email protected] Abstract- The testing of a 500 kW photovoltaic array inverter using power hardware-in-the-Ioop simulation is described. A real-time simulator is used with a DC amplifier in order to emu- late a photovoltaic (PV) array and an AC amplifier to emulate a power grid. The test setup is described in detail and a range of tests that were conducted on the inverter are summarized. I. INTRODUCTION As the penetration level of inverter-based distributed generation (DG) technologies in the distribution utility environment is increasing, the industry (utilities and power developers) is facing the challenge of testing and examining the performance of large-scale (several hundred kW and MW) inverters prior to installation. Typically, laboratory testing using grid simulators and load banks is conducted to evaluate power conversion devices. However, this approach may not be able to reflect the actual field conditions to which an inverter will be exposed. A real-time simulation approach, in conjunction with power hardware interface, is suggested and explored in this paper as an innovative laboratory testing approach with the ability to simulate conditions closer to what might be experienced in the field. Concepts and issues associated with power hardware-in-the-Ioop testing are described in [1]-[5]. In December 2011, PHIL testing of a 500 kW photovoltaic (PV) array inverter commenced at the Florida State University Center for Advanced Power Systems (CAPS). The project, sponsored by Southern California Edison (SCE), was intended to assess the dynamic behavior of a solar PV inverter during voltage and frequency changes, as well short-circuit Barry Mather National Renewable Energy Laboratory Golden, Colorado, USA [email protected] Farid Katiraei Quanta Technology Toronto, Ontario, CA atiraeuanta- technolo.com fault conditions [6]. The test data are to be used by SCE for model development and/or validation to assess the potential impacts of these technologies in the grid. With interest in leveraging the commissioned PHIL test setup for investigation of advanced PV inverter functions, a second phase of testing was sponsored by the National Renewable Energy Laboratory (NREL). NREL currently conducts research on the impacts of high-penetration levels of PV resources interconnected to the SCE distribution system, which includes work to develop models of PV systems, lab testing of advanced PV inverter nctions, and development of impact mitigation strategies for high penetration PV [7]. The NREL-sponsored segment of testing was intended to focus on assessment of inverter functions for reactive power control and system impacts through interconnection of the inverter to a virtual SCE distribution circuit through PHIL simulation. For these tests, a model of an actual SCE distribution circuit was simulated in real-time, such that the voltage at the simulated point-of-common-coupling (PCC) was applied at the terminals of the inverter and the real and reactive power supplied by the inverter was injected at the PCC in the simulated distribution circuit. This way the inverter nctions could be tested for a wide range of operating conditions in a controlled, laboratory setting, while realistically emulating the conditions that would be experienced by the inverter in the field. Herein, the approach for conducting these tests is described, and the conducted tests are discussed. 978-1-4673-2421-2/12/$31.00 ©2012 IEEE 4797
Transcript
Page 1: [IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada (2012.10.25-2012.10.28)] IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics

Power Hardware-in-the-Loop Testing of a 500 kW Photovoltaic Array Inverter

James Langston, Karl Schoder,

Mischa Steurer, Omar Faruque,

John Hauer, Ferenc Bogdan

Center for Advanced Power Systems

Florida State University Tallahassee, Florida, USA

[email protected], [email protected], [email protected], [email protected], [email protected], [email protected]

Richard Bravo Southern California Edison

Los Angeles, California, USA

[email protected]

Abstract- The testing of a 500 kW photovoltaic array inverter using power hardware-in-the-Ioop simulation is described. A real-time simulator is used with a DC amplifier in order to emu­late a photovoltaic (PV) array and an AC amplifier to emulate a power grid. The test setup is described in detail and a range of tests that were conducted on the inverter are summarized.

I. INTRODUCTION

As the penetration level of inverter-based distributed generation (DG) technologies in the distribution utility environment is increasing, the industry (utilities and power developers) is facing the challenge of testing and examining the performance of large-scale (several hundred kW and MW) inverters prior to installation. Typically, laboratory testing using grid simulators and load banks is conducted to evaluate power conversion devices. However, this approach may not be able to reflect the actual field conditions to which an

inverter will be exposed. A real-time simulation approach, in conjunction with power hardware interface, is suggested and explored in this paper as an innovative laboratory testing approach with the ability to simulate conditions closer to what might be experienced in the field. Concepts and issues associated with power hardware-in-the-Ioop testing are described in [1]-[5].

In December 2011, PHIL testing of a 500 kW photovoltaic (PV) array inverter commenced at the Florida State University Center for Advanced Power Systems (CAPS). The project, sponsored by Southern California Edison (SCE), was intended to assess the dynamic behavior of a solar PV inverter

during voltage and frequency changes, as well short-circuit

Barry Mather National Renewable Energy

Laboratory Golden, Colorado, USA [email protected]

Farid Katiraei Quanta Technology

Toronto, Ontario, CA fkatiraei@guanta­technology.com

fault conditions [6]. The test data are to be used by SCE for model development and/or validation to assess the potential impacts of these technologies in the grid.

With interest in leveraging the commissioned PHIL test setup for investigation of advanced PV inverter functions, a second phase of testing was sponsored by the National Renewable Energy Laboratory (NREL). NREL currently conducts research on the impacts of high-penetration levels of PV resources interconnected to the SCE distribution system, which includes work to develop models of PV systems, lab testing of advanced PV inverter functions, and development of impact mitigation strategies for high penetration PV [7]. The NREL-sponsored segment of testing was intended to focus on assessment of inverter functions for reactive power control and system impacts through interconnection of the inverter to a virtual SCE distribution circuit through PHIL simulation. For these tests, a model of an actual SCE distribution circuit was simulated in real-time, such that the voltage at the simulated point-of-common-coupling (PCC)

was applied at the terminals of the inverter and the real and reactive power supplied by the inverter was injected at the PCC in the simulated distribution circuit. This way the inverter functions could be tested for a wide range of operating conditions in a controlled, laboratory setting, while realistically emulating the conditions that would be experienced by the inverter in the field. Herein, the approach for conducting these tests is described, and the conducted tests are discussed.

978-1-4673-2421-2/12/$31.00 ©2012 IEEE 4797

Page 2: [IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada (2012.10.25-2012.10.28)] IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics

RTDS

G Emul� Converter Settings

Simulation of PHIL Setup Monitoring,

Trend Data Logging, Data Ca pture Grid Emulation

Current Reference

Voltage and Current Measurements

Open/Close

Thyristor

Voltage References

Switches Measurements

m Transformer VVS AC CBl

I'V

Vca Vabc-xfmr

L-__ �� ____ } L\ __________________ �------------------�

Solar PV emulation Converter under test Feeder/grid emulation Fig I. Power hardware-in-the-Ioop test setup.

A. PV Inverter II. TEST SETUP

The device under test (DUT) was a standard 500 kW, three-phase solar PV inverter, which operates with a nominal AC voltage of 200 V, and with DC voltage levels between 320 and 500 V. During operation, the negative DC rail is grounded through the unit, so the neutral point of the supply transformer must be ungrounded, as the inverter does not include an isolation transformer. The unit supports both constant power factor and constant reactive power modes of

operation. In addition to the human machine interface (HMI), the inverter provides a serial MODBUS port for remote monitoring and control. Reactive power control modes and set points can be modified through the MODBUS interface.

B. CAPS PHIL Facility The CAPS PHIL simulation facility, described in [8], was

designed for conducting PHIL simulation experiments at the megawatt scale, several examples of which are described in [8]-[13]. The facility includes a 5 MW variable voltage source (VVS) converter, a 5 MW dynamometer set, and a real-time simulator (RTDS) [14] used for simulation and control of the equipment. The VVS, which operates at 4.16 kV with an effective bandwidth of approximately 1.2 kHz, can be operated as a single 5 MW unit or can be split into a 2.5 MW AC unit and a separate 2.5 MW DC unit. The DC VVS, which operates at voltage levels up to

1.15 kV, can be operated in either a voltage or current control mode. The VVS units can be dynamically controlled, receiving instantaneous voltage (or current) reference signals from the RTDS. The RTDS executes electromagnetic transient simulations in real time with typical time-step sizes

on the order of 50 /ls, with small subsystems (e.g. for modeling converters) operating with time-step sizes on the order of 2 /ls. Thus, the facility is designed to support PHIL simulation experiments in which the DUT is interfaced through the power amplifiers and actuators (VVS and dynamometers) to a virtual environment (e.g. a model of a transmission system or distribution circuits), simulated on the RTDS.

C. Conjigurationfor PHIL Test The setup for testing of the PV inverter is illustrated by

Fig 1. The DC terminals of the inverter were connected to the DC VVS, which is used for emulation of the PV array. For these tests, the DC VVS was operated in a current control mode, and a 2.6 n resistive load bank (Rs) was placed in parallel with the DC terminals. A diode was also inserted in series on the positive DC rail in order to ensure unidirectional current flow into the inverter. With the diode inserted, the power source for the inverter can be quickly removed in the event of a problem by setting the DC VVS current reference to zero. On the AC side, the inverter was interfaced to the AC VVS through a 1.5 MV A, 480 V /

4.16 kV step up transformer. To be compatible with the

4798

Page 3: [IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada (2012.10.25-2012.10.28)] IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics

inverter AC voltage rating, the VVS was operated at reduced voltage in order to emulate a 200 V grid connection on the 480 V side of the transformer. The interconnection transformer has an ungrounded-Wye on the inverter side and a delta configuration on the VVS side.

In order to facilitate tests of short-circuit faults at the terminals of the inverter, thyristor switches were connected on the 200 V bus in a Wye configuration. Thyristors are

individually controlled for applying various fault types including single-phase to ground, line to line, and three phase faults. Additionally, a three-phase circuit breaker on the 4.16 kV bus, between the AC VVS and the step-down transformer, was used in some tests to abruptly disconnect

the inverter from the AC VVS under load. The proposed tests were used to examine inverter behavior for sudden unloading and disconnection from the main grid (islanding).

A number of voltage and current measurements were acquired and supplied to the RTDS for monitoring, control, and data recording purposes. On the DC bus, the current into the inverter was measured, along with the rail to rail voltage

on both sides of the diode. The voltage of the positive DC rail with respect to ground was also measured in order to detect ground faults. On the 200 V bus, the individual phase currents out of the inverter were measured, along with each of the line to line voltages. As the neutral point was required to be ungrounded, the line-ground voltage for each phase was also monitored in order to detect ground faults. On the 4.16 kV bus, line to neutral voltages were measured on both sides of the breaker, in order to assess the voltage drop across the breaker when it was opened. Differential probes were used for all voltage measurements, with Rogowski probes used for measurement of AC currents and Hall effect probes

used for measurement of DC currents. The probes were interfaced to the RTDS through GTAI and OADC cards.

While the RTDS can be used for data capture, it is limited in time resolution to the time-step size used for the RTDS case (50 J.!S, in this case). Thus, in order to obtain very high resolution captures (e.g. 1 J.!S resolution) many of the measured signals were also supplied to a separate data acquisition system (DAQ). In the PHIL test setup of interest, the RTDS provides a current reference for the DC VVS, voltage references for the AC VVS, open/close signals to control the thyristor switches, and command signals to the DAQ system for triggering and synchronization of captures. An RTDS script was also used for MODBUS communication with the inverter. The MODBUS link was used to set the operating mode of the inverter (e.g. power factor mode or constant reactive power mode) and control the inverter set points (e.g. requested power factor or reactive power contribution), as well as to retrieve status information from the inverter.

D. RTDS Functions The RTDS case, which was the primary means of control

for the experimental setup, served a number of functional roles for the tests, including emulation of the PV array, emulation of the utility grid, and protection. For emulation of the PV array, the simple voltage-current characteristic of Fig 2 was used. In order to avoid potential interactions between the DC VVS controls and those of the inverter, the

DC VVS was operated in a current control mode, allowing the maximum power point tracking (MPPT) control of the inverter to dictate the bus voltage. As a precautionary measure, the maximum of the two DC bus voltage measurements was used for the voltage feedback, such that the failure of a single voltage sensor would not lead to an excessive current reference from the controls. Additionally, the voltage at which maximum power is achieved has been intentionally chosen near the lower end of the inverters operating range in order to allow for more aggressive over­voltage protection to be implemented for the tests. A scaling factor was used for the resultant current from the V-I characteristic in order to control the available power to the

inverter and introduce the effect of changes in solar irradiation (where Fig 2 illustrates the V -I characteristic at maximum irradiation). Thermal characteristics were not considered for the PV emulation.

1.6 Current (kA) �I--�-�-�-�-�- Power(MW) 0.7

1.4 - - - : - - - � - - - :- - - 0.6

1.2 - - -,- - - T - - - ,- - - - - - T - - - ,- - - -, - - - 0.5

1 - - -I - - - T - - - r - - - - - I - - - r - - -I - - - I - - - 0.4

0.8 - - -,- - - T - - - r - - - - - - - - r - - -, - - - T - - 0.3

0.6 - - -1 - - - -+ - - - f- - - - - - -t - - - f- - - -I - - - -t - - - 0.2

0.4 - - -, - - - + - - - '- - - - - - + - - - '- - - -, - - - + - - - 0.1

0.2 - - - - - - -!- - - - � - - - - - -!- - - - � - - -I - - - -!- - - - I 0

-8.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 -0.1

Voltage (kV) Fig 2. Photovoltaic Characteristic

For emulation of the AC grid connection, the RTDS case was configured for operation in either an open-loop or closed-loop control mode. For the inverter transient testing phase, the open-loop mode of operation was employed, whereby the RTDS generated sinusoidal voltage references to the VVS, with no voltage feedback for correction. Provisions were made for ramping the voltage magnitude and phase angle for individual phases, as well as ramping the frequency of the references. In this way, the controls allowed for emulation of balanced and unbalanced voltage sags and swells of different magnitude and duration, as well as changes in frequency. For the segment of testing focusing on the inverter advanced functions for reactive power contribution, such transient events were of less interest, with emphasis placed on accurate control of the voltage magnitude to track fluctuations over seconds, compensating for voltage drop across the transformers due to significant

reactive power injections. For the latter mode of operation, a proportional-integral (PI) controller was used to track a reference voltage magnitude, and was tuned conservatively to respond to step changes in the voltage reference with a time constant on the order of 50 ms. For the voltage feedback, the median of three line-line RMS voltage measurements was used, such that the loss of a single sensor would not result in a malfunction of the control.

4799

Page 4: [IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada (2012.10.25-2012.10.28)] IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics

Additionally, hard limits were placed on the magnitudes of the references that were sent to the VVS to attempt to preclude the possibility of a controls initiated over-voltage.

For the portion of testing focusing on the inverter reactive power functions, the RTDS was also used for simulation of the distribution circuit representing the virtual environment in which the inverter was interconnected during the tests. Effectively, a fundamental frequency PHIL interface was used to couple the DUT with the emulated system, using two unsynchronized reference frames which are linked through converted three phase reference signals to direct (D) and quadrature (Q) components. As illustrated in Fig 3, the magnitude of the voltage at the PCC (Vmag-sim) was used as

a reference for the closed loop voltage control, such that this magnitude is reproduced at the terminals of the DUT. Simultaneously, the D- and Q-axis currents (Id, Iq) out of the DUT were measured, and these were injected into the simulated distribution circuit at the simulated PCC, completing the PHIL simulation loop. Filters were inserted for the reference voltage magnitude and D- and Q-axis currents, as illustrated in Fig 3, effectively limiting the bandwidth of the PHIL interface to fundamental frequency (i.e. 60 Hz) components. While instantaneous voltages and currents could have been used for the PHIL interface, the associated time delays can lead to stability issues for some conditions. As higher frequency components were not of particular interest for this phase of testing, this more conservative approach for the PHIL interface was employed.

Hardware Vabc-r

PV �werter

V,be Fig 3. PHIL Interface

The RTDS case was also used for protection of the PHIL setup. Protective elements for over-voltage and over-current were implemented for both the AC and DC buses. The protection actions were configured such that, upon receipt of a trip signal from one of the protection elements, the DC VVS current reference was set to zero and the closed-loop voltage control for the AC side was disabled, reverting to open-loop control. In this way any problems or instabilities with the interface could be quickly detected and power flow could be stopped before the problem reached the point of

tripping the inverter or the VVS. The RTDS case was also developed to support a simulation mode of operation, which serves as a method to test and debug controls and protection systems. A simulation model of the entire PHIL test setup (DUT, VVS, etc.), including delays, harmonic distortion, and sensor noise was implemented as part of the RTDS case. When executed in the simulation mode, all measured quantities are taken from the simulated setup, instead of the

actual sensors, and reference values are sent to the simulated amplifiers and equipment. In this way, the same controls and protection functions that are used for the actual tests can be used with the simulated environment to control a mock experiment. This feature provided invaluable benefits over

the testing period, by enabling the debugging and testing of the implemented controls and protection systems within the RTDS.

III. PV EMULATION

Emulation of the PV array was not a focal point for either of the testing phases, as these tests primarily focused on the interfacing of the PV inverter with the grid. Nevertheless, this function was needed in order to dynamically control the available power to the inverter. In general, the employed approach seemed to be acceptable in terms of the needed fidelity for these tests. Some of the results from the 1 s resolution data files for operation at a few constant power levels are shown in Fig 4. In Fig 4, the simulated power vs. voltage characteristics are shown, along with actual voltage and power measurements for (available) power set points (Pset) of 0.06, 0.27, and 0.425 MW. In general, the observed characteristics seemed to follow the characteristics that were simulated, and, thus, the available power to the inverter was controlled. However, particularly at lower power levels, the maximum power point tracking controls (MPPT) for the inverter seemed to select voltage levels somewhat lower than the theoretical voltage for maximum power delivery, resulting in slightly less than maximum power transfer. It is possible that this may stem from the bandwidth limitation of the PV emulation, but this has not yet been fully investigated and is the subject of further analysis. In general, however, the behavior of the PV emulation seemed to be sufficient for the tests that were conducted.

L() 6

'=t 0

(Y) 0

N 6

6

o 6

Power(MW) � Voltage for : Maximum Power

� Pset = 0.425 MW

Pset = 0.27 MW ./ Pset = 0.06 MW �

0.30 0.32 0.34 0.36 0.38 0.40

Voltage (kV) Fig 4. Perfonnance of PV Emulation

4800

Page 5: [IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada (2012.10.25-2012.10.28)] IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics

IV. TESTING

The tests for the SCE-Ied phase were conducted in December 2011. These tests covered under- and over-voltage conditions ranging in duration from 12 to 130 cycles. For each duration, a sequence of tests was conducted in which the deviation in voltage magnitude was gradually increased until the DUT tripped. Of interest in these tests were the magnitude of the deviation and time needed to induce a trip, and the duration between the trip and reclose events. These tests were conducted for both balanced and unbalanced conditions. While a simulated grid was not employed using closed-loop PHIL in these cases (the AC terminal voltage at

the inverter was controlled using open-loop references to the VVS from the RTDS), the under-voltage conditions were similar to staging a remote fault. Other under-voltage tests involved gradually reducing the voltage magnitude over a period of up to 16 seconds to assess the voltage threshold at which the inverter would trip offline. Similar sets of tests involving over- and under-frequency conditions were also conducted, involving frequency deviations up to 0.8 Hz for 12 cycles. All of these tests were repeated at multiple power levels.

Another set of tests involved the application of short­circuit faults at the terminals of the DUT using the thyristor switches, as illustrated in Fig 1. In order to avoid tripping the AC VVS during these tests, the voltage references for the VVS were controlled to minimize the VVS current contributions. For three-phase faults, this simply required

bringing all of the VVS voltage references to zero as the thyristor switches were fired. For unbalanced, line-line faults, this required modification of the phase and magnitude of the voltage references to produce zero voltage across the shorted phases. These tests, which were also repeated at several power levels, served to assess the current limiting behavior of the inverter, as well as durations for tripping off-line.

For the final set of tests conducted under the SCE-Ied segment, the inverter was subjected to opening of the circuit breaker (CBl) on the 4.16 kV bus under load. For these tests, which were also conducted for several power levels, the voltage measurements on both sides of CBl were acquired in

order to study the voltage to which the breaker was subjected during the transient. Also of interest, was the response of the inverter in detecting the island condition, including the magnitude and frequency of voltage at its terminals and the duration of time before shutting down. Thus, the inverter was exposed to a number of transient conditions to assess its response and potential impacts on the power grid.

While the SCE-Ied portion of the testing primarily focused on the transient behavior of the inverter, the NREL-Ied segment sought to explore the reactive power control capabilities of the device and how these functions might behave and interact with an actual distribution circuit. In

particular, a constant power factor mode and a constant reactive power mode were tested. For these tests, the inverter was interfaced with an emulated distribution circuit, and its behavior was studied through a series of tests involving variation in the reactive power control mode and set point, irradiance profile and point of common coupling (PCC) location with the simulated distribution circuit. The

simulated circuit was representative of an actual distribution circuit with a large amount of PV integrated on to the circuit that is located within the SCE service territory. Two different busses, one near the substation and one near the end of the distribution circuit, were used for the PCC in the PHIL tests. Load profiles based on actual loading of the circuit were also used, with load levels being updated at 5 s intervals. The PV power profiles used 2 s resolution and were based on data collected by NREL. Three different profiles, including profiles for low, moderate, and high variability, were used during the tests, as illustrated in Fig 5. In addition to the true PHIL tests, scaled PHIL tests were also conducted using the 500 kW inverter to represent a 2 MW inverter. For these

scaled PHIL tests, the current injections into the simulated system were actually scaled (by a factor of 4) versions of the measured D- and Q-axis current out of the inverter, and the MV A rating of the simulated interfacing transformer was also scaled. Thus, the operation of the inverter was tested for a large number of scenarios with the emulated distribution circuit.

1.0

_0.8 :; � � 0.6 o c.

)5 j 0.4

.� .. 0.2

0.0 o

r-- � 1 "rl

I Y � "- .J'o' '\,.J V'-J -moderate

-smooth -high Time (minutes)

4 6 8 10 12 14 16 Fig 5. Normalized PV Power Profiles

In general, the distribution circuit presented a very low impedance grid connection, and the voltage levels for the buses on the circuit were not dramatically affected by the contributions of the inverter. Nevertheless, the effects of the PHIL simulation on the inverter were notable, as the fluctuations in the voltage at the PCC were significant. This is illustrated by Fig 6, which shows, in the top plot, the voltage in the simulated system at the PCC (Vsim), along with the measured voltage at the terminals of the inverter (Vm) and the VVS voltage reference (Vr). As shown, the

voltage at the terminals of the inverter closely tracks the voltage at the PCC in the simulated system. Similarly, as shown in the bottom plot, the real and reactive power injections in the simulated system (Psim and Qsim, respectively), generally track the measured real and reactive power (Pact and Qact, respectively) supplied by the inverter. The test illustrates the PV inverter operation with a power factor of 0.85 lagging (absorbing reactive power) with the PV power profile of moderate fluctuation. The action of the VVS reference signal further illustrates the role of the PHIL simulation, in that, as more reactive power is consumed by the inverter, the closed-loop voltage controller is actually

required to raise the VVS voltage reference to reproduce the appropriate drop in voltage. This is due to the fact that that the impedance of the transformers in the CAPS facility is

4801

Page 6: [IEEE IECON 2012 - 38th Annual Conference of IEEE Industrial Electronics - Montreal, QC, Canada (2012.10.25-2012.10.28)] IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics

actually higher than the impedance of the simulated transformers, making the voltage sensitivity higher in the lab. In order to compensate and allow the inverter to experience the voltage drop of the simulated system, the VVS reference is actually increased as more reactive power is consumed by the inverter. Thus, the inverter experiences the voltage drop that would be experienced if it was interfaced through the simulated transformers to the simulated circuit. 0.22

0.21

0.5

2 3 4 Time (min)

Active Power (MW), Reactive Power (MVAR)

5

1 -Vsim 1 -Ym

-Yr

1 ··········Qsim o - - - - - T - - - - - -I - - - - - - 1- - - - - - t- - - - - - � -Qact

-0.51 2 3 4 5 Time (min)

Fig 6. Tracking of Voltage and Real and Reactive Power

V. CONCLUSION

6

7

7

The testing of a 500 kW PV inverter using a PHIL simulation approach was described. The approach used a real time simulator to control a DC VVS for emulation of a PV array and an AC VVS for emulation of a grid connection.

The approach used a simple current-voltage characteristic and feedback of instantaneous voltage for emulation of the PV array, operating the DC VVS in a current control mode to avoid potential interactions with the inverter controls. For the grid emulation, tests were conducted in both open-loop control mode, as well as in a closed-loop PHIL mode of operation, in which a distribution system was emulated. However, the PHIL mode of operation made use of a fundamental frequency PHIL interface, thus not accounting for harmonics or very fast interactions. Future efforts may focus on the use of a higher bandwidth PHIL interface suitable for a wider range of tests.

ACKNOWLEDGMENT

This work was supported by Southern California Edison, the U.S. Dept. of Energy (DOE) Office of Energy Efficiency and Renewable Energy (EERE), Solar Energy Technologies Program (SETP), under the Analysis of High Penetration Levels of PV into the Distribution Grid in California Project, award no. DE-EE0002061, with match funding from the Cali­fornia Public Utility Commission (CPUC) California Solar Initiative (CSI) Research, Development, Demonstration and

Deployment (RD&D), and the DOE EERE SETP, under the Implementing the Sunshine State Solar Grid Initiative (SUNGRIN), award no. DE-EE0004682.

REFERENCES

[I] W. Ren, M. Steurer, and T. L. Baldwin, "Improve the Stability and the Accuracy of Power Hardware-in-the-Loop Simulation by Selecting Appropriate Interface Algorithms," IEEE Trans. on Industry Applications, Vol. 44, No. 4, pp. I 2S6-I 294, July 200S.

[2] G. Lauss, F. Lehfuss, A. Viehweider, and T. Strasser, "Power hardware in the loop simulation with feedback current filtering for electric systems," IECON 201 I - 37th Annual Conference on IEEE Industrial Electronics Society, 20 I I, pp. 3725-2730.

[3] S. Lentijo, S. D'Arco, and A. Monti, "Comparing the Dynamic Performances of Power Hardware-in-the-Loop Interfaces," IEEE Trans. Industrial Electronics, Vol. 57, Issue 4, 2010, pp. 1195-1207.

[4] M. Hong, L. Chien-ru, Y. Miura, and T. Ise, "Accuracy evaluation of power hardware-in-the-Ioop simulatin of a boost chopper," 2010 International Power Electronics Conference (IPEC), 2010, pp. 2424-2429.

[5] H. Seo, M. Park, I. Yu, and B. Song, "Perfonnance analysis and evaluation of a multifunctional grid-connected PV system using power hardware-in-the-Ioop simulation," 2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 20 I I, pp. 1945-I 94S.

[6] R. Bravo, R. Yinger, and S. robles, "SCE 3-Phase Solar PV Inverter Test Procedure," Technical Procedure, Souther California Edison, February 2012.

[7] B. Mather, B. Kroposki, R. Neal, F. Katiraei, A. Yazdani, J. R. Aguero, T. E. Hoff, B. L. Norris, A. Parkins, R. Seguin, and C. Schauder, "Southern California Edison high-penetration photovoltaic project - year 1," Tech. Report NRELITP-5500-50S75, National Renewable Energy Laboratory, June 201 I.

[S] M. Steurer, C. S. Edrington, M. Sioderbeck, W. Ren, and J. Langston, "A Megawatt-Scale Power Hardware-in-the-Loop Simulation Setup for

Motor Drives," IEEE Transactions on Industrial Electronics, Vol. 57, Issue 4, pp. 1254-1260, 20 10.

[9] J. C. L1ambes, D. Hazelton, J. Duval, M. Albertini, S. Repnoy, V. Selvamanickam, G. Majkic, I. Kesign, J. Langston, M. Steurer, F. Bogdan, J. Hauer, D. Crook, S. Ranner, T. Williams, and M. Coleman, "Perfonnance of 2G HTS Tapes in Sub-Cooled LN2 for

Superconducting Fault Current Limiting Applications, IEEE Trans. Applied Superconductivity, Vol. 21, Issue 3, Part 2, 2011, pp. 1206-120S.

[10] C. Schacherer, J. Langston, M. Steurer, and M. Noe, "Power Hardware-in-the-Loop Testing of a YBCO Coated Conductor Fault Current Limiting Module," IEEE Trans. Applied Superconductivity, Vol. 19,1ssue 3,Part 2,2009,pp. ISOI-IS05.

[11] K. Schoder, J. Langston, M. Steurer, S. Azongha, M. Sioderbeck, T. Chiocchio, C. Edrington, A. Farrell, J. Vaidya, and K. Yost, "Hardware-in-the-Loop Testing of a High Speed Generator Excitation

Controller," Proc. 20 I 0 ASNE Electric Machines Technology Symposium, Philadelphia, PA, May 19-20,2010.

[12] J. Langston, M. Steurer, K. Schoder, J. Hauer, F. Bogdan, I. Leonard, T. Chiocchio, M. Sioderbeck, A. Farrell, J. Vaidya, and K. Yost, "Megawatt scale hardware-in-the-Ioop testing of a high speed

generator," Proc. ASNE Day 2012, Arlington, VA, Feb. 9-10 2012. [13] S. Woodruff, H. Boenig, f. Bogdan, T. Fikse, L. Petersen, M.

Sioderbeck, G. Snitchler, and M. Steurer, "Testing a 5 MW high­temerature superconducting propulsion motor," Proc. 2005 IEEE Electric Ship Technologies Symposium, 2005, pp. 206-213.

[14] R. Kuffel, J. Geisbrecht, T. Maguire, R. P. Wierckx, and P. G. McLaren, "RTDS-a fully digital power system simulator operating in real time," in Proc. 1995 IEEE Conf. on Communications, Power and Computing, WESCANEX, vol. 2, pp. 300-305

4802


Recommended