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Small-Signal Averaged Model and Carrier-BasedLinear Control of a SEPIC-Type Power Factor

Correction Circuit

Hadi Y. KanaanDepartment of Electrical and Mechanical Engineering

Saint-Joseph University, Faculty of Engineering - ESIBMar Roukoz, Mkalles, Lebanon

hadi.kanaan@fi.usj.edu.lb

Abstract - In this paper, the small-signal averaged model of aDC-to-DC Single Ended Primary Inductance Converter(SEPIC), used in single-phase Power Factor Correction (PFC)applications, is derived. Compared to conventional buck orboost converters, this topology allows a low current ripple at theinput for a relatively low level of the DC-bus voltage. Based onthe proposed model, a carrier-based Pulse-Width-Modulation(PWM) linear control system is developed in order to ensure aunity power factor at the rectifier AC-side and a regulatedvoltage across the DC load. Both current and voltage regulatorsare PI-type. The performance of the proposed control scheme istested through simulations. The system performance isevaluated in terms of source current Total Harmonic Distortion(THD), input power factor and DC-voltage regulation.

I. INTRODUCTION

High power quality achievement is increasingly requiredfor the power supply systems in order to comply with theinternational standards [1]. For this purpose, and especiallyfor single-phase low power applications, switch-mode DC­DC converters, commonly known as Power Factor Correction(PFC) circuits, are designed in order to ensure a high powerfactor at the mains side, and to emulate a purely resistiveoperation of the diode-bridge-based front-end rectifier [2].

Among the conventionally used PFCs are the Boost-BuckDC-DC converters [3]. These PFCs can provide non­pulsating currents at the input and output stages, with areduced level of the output voltage, which make them highlysuitable for such applications. Several single-stage topologiesof Boost-Buck combinations have been introduced in theliterature. The cascaded Boost-Buck converter [4], the Cukconverter [5] and the Single Ended Primary InductanceConverter (SEPIC) [6] are the most common ones. However,the advantages that the SEPIC presents over the otherstructures is, first, the relatively low number of devicescompared to the Boost-Buck converter and, second, the non­inversion of the voltage polarity across the DC load, as in theCuk topology. These features make the SEPIC very attractivein PFC applications.

978-1-4244-2056-8/08/$25.00 ©2008 IEEE

Kamal AI-HaddadDepartment of Electrical Engineering

Ecole de Technologie Superieure (ETS), Canada ResearchChair in Energy Conversion and Power Electronics

Montreal, Quebec, Canadakamal@ele.etsmtl.ca

In this paper, a carrier-based PWM linear control scheme isproposed for the SEPIC-based power factor corrector. PIregulators are calculated to achieve perfect current tracking atthe AC-source and voltage regulation at the DC-load. Thedesign of the regulators is based on a small-signal averagedmodel of the converter, which is also developed in this paper.The performance of the proposed control scheme is thenanalyzed through numerical simulations on Matlab/Simulink.For this purpose, a switching-function-based state model ofthe converter operating in Continuous Current Mode (CCM)in both inductors and Continuous Voltage Mode (CVM) inboth capacitors is implemented, and the control process isapplied under rated operating conditions in order to test thetracking abilities of the controllers.

II. CCM/CVM OPERATION AND AVERAGED MODELING OFTHE SEPIC-BASED POWER FACTOR CORRECTOR

The basic structure of the SEPIC is described in Fig. 1. Inthe most common case of a Continuous Current Mode (CCM)in both inductors L1 and L2 , and a Continuous Voltage Mode(CVM) in both capacitors C and Co , the operating sequencesof this topology are illustrated in Fig. 2. The circuit has twoconfigurations, depending on the state of the main switch Q .

SEPIC Converter

Fig. 1. SEPIC-based PFC.

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iLl L 1 C D----.

vin ~ Vo

(a)

(2.a)

(2.b)

(2.c)

(2.d)

(b)

where Vs and Is represent respectively the RMS-values of themain source voltage and current, D, ILl , I L2 , 10 , V;n , Vo andVc the static or DC values of the duty cycle, the currents ininductors L I and L 2 , the DC load current, the input voltage,and the voltages across capacitors Co and C, respectively. It isclear that, for D < Y2, Vc is greater that Vo.

Applying the small-signal linearization technique to system(1) around the static point (2) and choosing iLl and Vo as thesystem's outputs yields:

III. SMALL-SIGNAL MODEL AND TRANSFER FUNCTIONS

Fig. 2. Operating sequences in CCM/CVM: electrical configuration when Qis turned-on (a) or turned-off (b).

Following these considerations, applying the state-spaceaveraging modeling technique [9] in CCM/CVM mode yieldsthe following averaged model of the converter [7-8]:

For the design of linear control system based on PIregulators, a small-signal model of the converter is required.This is obtained by linearizing system (1) around the staticoperating point defined by:

(3.a)

(3.b)

~iLl ~iLl

d ~iL2=A·

~iL2+B·~d+P,~vin-

dt ~vc ~vc

~vo ~vo

~iLl

[ML1] _

~iL2-C·

~vo ~vc

~vo

0 0I-D I-D

Ll Ll

0 0D I-D

A= L2 L2I-D D

0 0-- --C C

I-D I-D0

1

Co Co RoCo

VoLIDVo Ll

B=L2D

P= 0Vo 0

RoC(l-D)Vo

0

RoCo(I-D)

with:

(1)

diLl () ( )Ll--=Vin - I-d· Vc +vodt

diL2 ()L --=d·v - I-d ·v2 dt c 0

dv C ( ). •C--= I-d'l -d'ldt L1 L2

dvO ( ) (. .) VoC -= I-d· I +1 --o dt Ll L2 Ro

where d(t) denotes the common duty cycle of switch Q , andRo represents the DC load. Here, it is assumed that theconditions (iLl + iL2) > 0 and Vc > 0 always stand; theseassumptions are justified by a suitable choice of inductor L2

and capacitor C [7]. Moreover, in Unity Power Factor (UPF)operation, the current iLl is mainly in continuous mode, andwould be only locally in discontinuous mode at the zero­crossings of the AC source voltage; this latter feature will beneglected as far as modeling and control are concerned.

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and:

c =[1 0 0 0]000 1

It is on the basis of these transfer functions that theproposed control scheme, which ensures unity power factor atthe PCC as well as voltage stabilization at the DC bus, will bedesigned.

In equation (3), A defines the state matrix, B the controlmatrix, P the disturbance matrix and C the output matrix. Inaddition, for any state variable Z E {iLl, iL2 , Vc , vol, ~denotes its assumed small-variation around its static value Z,i.e.:

~=Z-Z

The frequency-domain representation of the converter isobtained by applying the Laplace transform to the stateequations (3). It yields:

Y(s) = C(s14 -A)-I B .D (s)+C(sI4 -A)-Ip.V;n(s) (4)

where 14 denotes the 4-by-4 identity matrix, s the Laplaceoperator, Y(s) = [ILl(S) , VO(S)]T, D(s) and ~n(s) the Laplacetransforms of the output-vector [~iLl , L\vO]T, the control input~d and the disturbance input ~Vjn respectively.

The development of expression (4) leads to the followinginput-output transfer functions:

IV. CONTROL SYSTEM DESIGN

The control circuit is depicted in Fig. 3. It consists of twosuccessive loops: the inner or current one is designed toensure the wave-shaping of the DC input current iLl and,consequently, the improvement of the input power factor,while the outer or voltage loop is aimed to regulate the DCload voltage and to stabilize it around a desired set-point.

Both inner and outer controllers are linear Proportional­Integral (PI) regulators, represented respectively by thetransfer functions H,(s) and Hv(s). The parameters of thecontrollers are calculated using the lead-lag compensationmethod, on the basis of the transfer functions established inthe previous section. They are chosen in order to ensure highdynamic performance in the system bandwidth. Furthermore,to ensure high stability of the control system, the outer loop ischosen to be enough slower than the inner one. In that case,the design of the outer regulator will make use of thefollowing open-loop transfer function that takes account ofthe presence of the inner loop:

G (s) = ILl (s)1 =~ . S3 + tozIS2

+ to;2S + to;3iL1,d - D(s) V;n=O LID S4 + topI S

3+ to~2s2 + to;3 S +m;4(5.a)

LID S3 - OJz4S2 + {j):ss - to;6

K;RoCo(1- D) . S3 + {j)zl S2 + {j):2S + to;3

(6)

with:

(5.b)

V. SIMULATION RESULTS

K j , Kvo and KVl are scaling gains of the current and voltageloops, respectively. The inner control signal Uj given by thecurrent regulator is compared to a saw-tooth carrier in orderto generate a fixed-frequency PWM gate signal for the pair ofswitches.

In addition, in order to emulate a pure resistor behavior, thecurrent reference must have the same shape as the rectifiedsource voltage Vjn , with an adjustable magnitude. An analogmultiplier is used for this purpose. In order to avoid thedistortion of the current reference, the voltage control signalUc should be harmonic-free. This can be achievable by tuningadequately the outer regulator which will have the additionaltask to filter the 120Hz component (at twice the mainsfrequency) in the output DC voltage Vo •

In order to highlight the performance of the Sheppard­Taylor converter in PFC applications, a virtual version of thecontrol system of Fig. 3 has been implemented usingMatlab/Simulink. The numerical values of the structuralparameters and operating conditions are listed in theappendix. The converter is implemented according to itsswitching-function-based model given in [7].

VO S3 - OJz4S2 + OJ;ss - OJ;6

RoCo(l- D) . S4 + OJp1 S3 + OJ~2S2 + m;3s + OJ;4

~to -zS - L

2C

1(j) =--

pI RoCo

2D

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Vc+

Vin c: Q L2 CoVo

i iL2

SQ

vpWM

PI Voltage l/1/1/regulator

"V; * L L +0

Multiplier Pulse-WidthPI Current Modulatorcontroller

Fig. 3. Carrier-based linear control scheme.

REFERENCES

ApPENDIX: NUMERICAL VALVES

[1] IEEE Recommended Practices and Requirements for HarmonicsControl in Electric Power Systems, IEEE Std. 519, 1992.

implemented numerically using the Matlab/Simulink tool,and the tracking and regulation performances of the controlsystem were evaluated.

1+~

Hv(s)=20~s

Vs = 120VPo= 1kWVo* = 5V

fo = 60Hzfs= 40kHzvPWM = IV

L 1 = 1mH, L2 = 10mBRL1 = O.ln, RL2 = O.lnC = 10mP, Co = 10mFK j = In, Krl) = 0.05KV1 = 1/108

1+~

Hi(s)=15~s

Outer voltage PI regulator

Inner current PI regulator

Mains voltage RMS-valueRated load powerVoltage referenceMains frequencyCarrier frequencyCarrier peak value

DC inductorsSeries inductors' resistorsDC capacitorsFeedback scaling gainsFeedforward scaling gain

VI. CONCLUSION

The simulations are carried out using a fixed-step ode5(Dormand-Prince) solver. The step size is 1f.!S. The obtainedresults are given in Fig. 4 for a 1kW-load. The line currentTHD is 7.5% and the power factor is 0.995. The currentripple at the switching frequency is 6.5% (at the positive andnegative peaks of is). The DC output voltage Vo is stabilized atthe reference value of 100V, with a 2.5% ripple at 120Hz.The voltage of the intermediate capacitor C is also stabilizedat 108V, with a 2.3% ripple at 120Hz. Fig. 4 shows also thatiL2 and Vc are always positive, and thus justifies theassumption of a CCM/CVM operation made previously.

In order to test the tracking and regulation performance ofthe proposed control scheme, sudden variations have beenapplied respectively to the set-point Vo*, the DC load Ro andthe source voltage RMS-value Vs . The correspondingsimulation results are presented respectively in Figs. 5, 6 and7.

In this paper, a simple carrier-based linear control designfor a single-phase SEPIC-based PFC has been proposed. ACCM/CVM small-signal averaged model of the converter hasbeen developed for this purpose, and corresponding transferfunctions have been computed. The control scheme consistsof two cascaded loops: the inner loop ensures source currentshaping and, thus, a unity power factor, whereas the outer oneregulates the DC voltage across the load. Both loops employPI regulators. The converter and its control circuit were

[2] B. Singh, B. N. Singh, A. Chandra, K. AI-Haddad, A. Pandey and D. P.Kothari, "A review of single-phase improved power quality AC-DCconverters", IEEE Trans. Ind. Electron., vo1.50, No.5, Oct. 2003, pp.962-981.

[3] S. Funabiki, N. Toita and A. Mechi, "A single-phase PWM AC to DCconverter with a step up/down and sinusoidal source current", in Con!Rec. IEEE-lAS Annual Meeting, 1991, pp. 1017-1022.

[4] R. Redl, L. Balogh and N. O. Sokal, "A new family of single-stageisolated power-factor-correctors with fast regulation of the outputvoltage", in IEEE PESC'94 Rec., pp. 1137-1144.

[5] C.-J. Tseng and C.-L. Chen, "A novel ZVT PWM Cuk power-factorcorrector", IEEE Trans. Ind. Electron., vo1.46, Aug. 1999, pp. 780-787.

[6] L. Petersen, "Input-current-shaper based on a modified SEPICconverter with low voltage stress", in Proc. IEEE PESC'OJ, 2001, pp.666-671.

Source 'vOltage and source current

20

10

o

-10

-20

-30 L--.-_-'---_---'----_--'-_---'-__.L-_--'--_---'----_-----'----_---'-_----..J

o 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05lime (seconds)

(a)

Inner controller output uj

0.8

0.4

0.2

o

-0.2

-0.4

-0.6

-0.8

-1

o 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05Time (seconds)

(c)

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[7] H. Y. Kanaan, K. AI-Haddad and F. Fnaiech, "Switching-function­based modeling and control of a SEPIC power factor correction circuitoperating under continuous and discontinuous conduction modes", inProc. IEEE ICIT'04, Hammamet, Tunisia, December 8-10, 2004, vol.1, pp. 431-437.

[8] H. Y. Kanaan and K. AI-Haddad, "A Comparative Analysis ofNonlinear Current Control Schemes Applied to a SEPIC Power FactorCorrector", in Proc. 3Ft Annual Conference of the IEEE IndustrialElectronics Society (IECON'05), Raleigh, North Carolina, USA,November 6-10, 2005, pp. 1104-1109.

[9] R. D. Middlebrook and S. Cuk, "A general unified approach tomodeling switching-converter power stages", Proceedings of the IEEEPower Electronics Specialists Conf., Cleveland, OH., June 8-10, 1976.

Currents in the input and intermediate inductors30,---,---,----,-------,-----,---,-------,-----,-------,--

25

20

15

10

5

o

o 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05lime (seconds)

(b)

Voltages across the output and intermediate capacitors200 ,---,---,--------,-------,-----,---,-------,---------,-------.---,

180

160

140

120

100

80

60

40

20

0'-----'----------'-----------'--------"----------1---'------'-----------'------'---

o 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05lime (seconds)

(d)

Fig. 4. Steady-state waveforms at the rated load of (a) the source voltage (vs) and the source current (is) , (b) the currents in the input and intermediate inductors(ill and iLl respectively), (c) the inner controller output (Ui) and (d) the voltages across the output and intermediate capacitors (vo and Vc respectively).

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De-load \/Oitage with respect to its reference200

180

160

140

120

100

80

60

40

20

00 0.5 1.5 2.5

lime (seconds)

(b)

32.51.5lime (seconds)

0.5

Source current

(a)

-40 '--- "---- "---- "---- '---__-----JL--__------'

o

-30

Fig. 5. Tracking performance of the linear control scheme: Responses of (a) the source current and (b) the DC-load voltage to set-point offsets from 100V to150V and from 150V to 50V, applied respectively at Is. and 2s.

Source current Voltages across the output and intermediate capacitors160

I Vo ~140 Vc

120;~

"",-,

80

60

40

20

0

15

10

-51

-10

-15

-200 0.5 1.5

lime (seconds)2.5 3 o 0.5 1.5

lime (seconds)2.5

(a) (b)

Fig. 6. Regulation performance of the linear control scheme: Responses of (a) the source current and (b) the voltages across the intermediate and loadcapacitors to sudden variations of the DC load, from IkW to 500W and then back to IkW, applied respectively at Is. and 2s.

Source \/Oitage Voltages across the output and intermediate capacitors..,..,.., 300

C400

250Vc

300

':. ..1\.'.....

200200

100

150

-100

100-200

-30050

-400

-500 00 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

lime (seconds) lime (seconds)

(a) (b)

Fig. 7. Regulation performance of the linear control scheme: Waveforms of (a) the source voltage and (b) the voltages across the intermediate and loadcapacitors to a sudden variation of the source voltage RMS-value, from 120V to 240V, applied at 0.5s.