IEEE SSCS DLP, Colorado, June 15, 2006 Ultra-Low …...1 Ultra-Low Voltage Nano-Scale Embedded RAMs...

1

Ultra-Low Voltage Nano-ScaleEmbedded RAMsKiyoo Itoh, Hitachi Ltd.

IEEE SSCS DLP, Colorado, June 15, 2006

OUTLINE1. Introduction2. Trends & Challenges3. Low-Voltage Limitation of RAMs4. Leakage & Speed Variation of

Peripheral Logic Circuits 5. Memory Cell Size6. Future Prospects7. Conclusion

K. Itoh, Hitachi

2

Trends in RAM Developments (R&D)M

emor

y C

apac

ity/

chip

(bi

ts)

Year

256 K

1970

DRAM

first presentation atISSCC/Symp. VLSI Circuits

1980 1990 2000

16 G

1 G

64 M

4 M

16 K

1 K

SRAM

Year

Mem

ory

Cel

l Are

a (μ

m2 )

19901970 1980 2000

10,000

1,000

100

10

1

0.1

full CMOS

DRAM

SRAMTFT load

poly-Si load

full CMOS

3-D capacitor

ISSCC, Symp. VLSI Circuits

0.01

TFT

TFT

Planar capacitor

K. Itoh, Hitachi

3

Challenges to LV e-RAMs

RAM Cells•Extend low-voltage limitation to sub-1 V-Degraded S/N-Increased leakage

•Reduce cell size

K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001

e-RAM

RAM cellarray

DRAMSRAM

periph.DL

SRAMDRAM

WL VDD

0

"1"

"0"

DLWL

0 VDD

DL

Cs

Peripheral Circuits •Reduce leakage-Increased ISTB & IACT

•Reduce speed variation-Unreliable operations

K. Itoh, Hitachi

4

1. It is governed by soft-error of cells, or S/N of cells and cell-relevant circuits.

2. As long as ECC is used, it is governed by S/N.

3. S/N is determined by •Signal charge & signal voltage of cells, •Flip-flop circuits that DRAMs use for sense

amps, while SRAMs use for cells themselves.

Low-Voltage Limitation of RAMs

ECC: Error Checking and Correcting circuit

K. Itoh, Hitachi

5

Comparisons of Flip-Flop Circuits

SRAM CellDRAM SA

Standby

Active

Margin

Off with all nodes at VDD/2 On with static of all MOSTs

Dynamic sensing of vS i by ratio of M1 & M5

(SN on, then SP on) Static of other MOSTs

Sensitive to VT & ΔVT of Sensitive to VT & ΔVT ofonly two MOSTs, M1 & M2 all MOSTs → Narrow margin

CircuitDLDL

VDD

M1

M5

VDDi

VDD

0DL DL

VDD/2

VDD/2SN

SP

M1 M2

VDD/2 VDD/2

STB ACT

-vS

K. Itoh, Hitachi

6

Signal Charge QS of RAM CellsQS ≅ Soft-Error Qcrt . The larger the QS , the smaller the SER.QS decreases with device and voltage scaling.

QS = CSVDD/2 QS = CSVDD , CS =(C1 + 2C2 )CS ; Intentionally added, C1, C2 ; parasitic, small, andlarge, and needs to be rapidly decrease with devicegradually decreased scaling.with device scaling for SER is always larger than formaintaining large vSIG. DRAM.

WLVDDDL

0Cs

"1"

"0"

DRAM SRAMVDD

DLC1

DL

C2WL

0VDD

K. Itoh, Hitachi

7

Y. Nakagome et al., IBM J. R&D, Vol.47, No.5/6, Sep./Nov. 2003E. Ibe, The Svedberg Laboratory Workshop on Applied Physics,Uppsala, May 3, 2001

Qs reduced with capacitydue to VDD & device scalingSmaller QS of SRAM cell

SER depends on QS

DRAM; decreases with memorycapacity due to large intentionally-added CS & spatial scaling thatreduces charge collection.SRAM; increases with memorycapacity due to rapidly-decreasingparasitic CS despite spatial scaling.Solutions:•Increase in CS (SRAM cells)•Uses of triple well, redundancy,

ECC etc.

SER

Cro

ss S

ecti

on/c

hip

(cm

2)

Memory Capacity (bits)100K 1M 10M 100M 1G

1E-5

1E-6

1E-7

1E-8

1E-9

1E-10

DRAM

SRAM

1

10

100

1000

Sign

al C

har

ge, Q

S(f

C)

Memory Capacity (bits)1G64M4M256K16K

4

DRAM

SRAM

Trench

Stack

Planar

12.56.95.1

Stand-aloneQS =CS VDD/2

ΔCS(α-SER: x10-3.5)

Signal Charge (QS) of RAM Cells

K. Itoh, Hitachi

8

Error Checking & Correcting (ECC)

M. Horiguchi et al., IEEE J. SSC, 23, p. 27, Feb. 1988

ECC word = 128 data bits + 8 check bits, FIT = 10-9/hour

102 106 108104

SER without ECC (FIT)

SER

wit

h E

CC

(FI

T)

10-18

10-16

10-14

10-12

10-10

10-8

10-6

10-4

10-2

102

104

106

108

without ECC

periodic correction

(1 ECC word/7.8 μs)no corre

ction during 10-year period64 Mb

256 Mb

16 Mb

100

100

one upset/ 1 k hours

K. Itoh, Hitachi

9

Minimum VDD (Vmin) of RAMsDRAM SRAM

δVT : VT-mismatch between paired MOSTs, VT0 : Average VT

If only cross-coupled nMOSTs determine the voltage margin during read,VG = VDD –VT0 –δVT ≥ 0, ∴Vmin = VT0 +δVT

VDD

vS > δVT,vS ≅ (VDD/2)CS/CD

∴Vmin = 2δVT CD/CS

=10δVT (CD/CS ≅ 5)

VG =VDD/2 – (VT0

+δVT) > 0 ∴Vmin =2 (VT0 +δVT)

Cell SA Cell VDD

VT0 +δVT

DL DL

VT0

DL DLVDD/2−vS VDD/2

VT0 +δVT VT0

0

CD

DL

Cs−vS

WL

K. Itoh, Hitachi

10

Lowest Necessary VT0 for SA

subthresholdcurrent of M2

(isub)

VDD/2

WLon

SPon

–vS

SNon

DL

DL

0

C

A

B

δVTp

tS

Δv

DL

SP

SN

VDD/2

DL

VDD/2

0

VDD

M1 M2

–vS VTp

• Signal (-vS) is amplified, so DL isdischarged to A. After that, DL isgradually discharged by isub (M2).

• SP is on before DL reaches C.• VT0 (nMOST) ≥ 0.2 V @extra., 25°C,

if tS = 5 ns, Δv = 50 mV, CD =100 fF@ 120°C

K. Itoh, Hitachi

11

•Cross-coupled MOSTs need a high VT to ensure a small retention current through reducing iL.

•VT0 is the average in a chip, because it is the average that determines retention current of the chip.

•VT0 must be quite high and unscalable.

Lowest Necessary VT0 for SRAM Cell

Extrapolated VT0 (V) at 25 ºC -0.2 0 0.2 0.4 0.6 0.8 1.0

100 Lg =0.1 μmW (QT)=0.20 μm W (QD)=0.28 μm W (QL)=0.18 μm

Tj =125 °C100 °C75 °C50 °C

25 °C

high speed(0.49)

low power(0.71)10 μA

0.1 μA

10-2

10-4

10-6

10-8

1-M

b ar

ray

rete

nti

on c

urr

ent

(A)

Extrapolated VT =VT (nA/μm)+0.3 V

K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp. 339-344, Oct. 2004

iL

VT0 +δVTVDD –VT0 –δVT

VDD

DL

K. Itoh, Hitachi

12

VT -Mismatch (δVT)

90 nm bulk

65 nm bulk

45 nm bulk

32 nm bulk

65 nm FD-SOI

45 nm FD-SOI

32 nm FD-SOI

Standard deviation (a.u.)210

σ (VT)σint

σext

σint

σext

σ (VT)

M. Yamaoka et al., Symp. VLSI Circuits 2004

1.VT Variation (ΔVT) as source of δVT

•Extrinsic ΔVT due to implant non-uniformities & Δ (L,W)

•Intrinsic ΔVT due to random microscopic fluctuations of dopant atoms in the channel area.

2.ΔVT & δVT increase with reducing MOST size evenfor a fixed generation.

σint ∝ 1/√LWσ(δVT) ≅ √2 σint

3.ΔVT & δVT increase withdevice scaling.

ΔVT in a chip has no room in time & area to be compensated for.

K. Itoh, Hitachi

13

Larger δVT of SRAM cell

SRAM Cell

DLDL

DRAM SA

Circuit

MOS Size 10 – 20 F 2 1.8 – 2.8 F 2

CircuitCount

in a chip

M/(64 -1024) M

δVT Small Large

64-1024

Relaxed SA layout

DL DL

M

Array

M : memory capacity

K. Itoh, Hitachi

14

Maximum δVT in a chipr : repairable percentage

SRAM Cell

90 65 45 32

400

0

Max

. δV

T (m

V)

100

200

300

10%

1%

0.1%0.01%0.001%

r = 0

F (nm)SRAM 32Mb 64Mb 128Mb 256Mb

LW = 2F 2, tOX = 1.9 nm

DRAM SA

90 65 45 32F (nm)

40

80

120

0

Max

. δV

T (m

V)

20

60

100

10%

1%

0.1%0.01%0.001%

r = 0

512Mb 1Gb 2Gb 4GbDRAM

LW = 20F 2, tOX = 1.9 nm64cells/SA

100 330

K. Itoh, Hitachi

15

Vmin (r = 0.1 %)

DRAM SRAM

*Actual Vmin determined by all MOSTs in a cell.

FD-SOI

1.4

1.2

1.0

0.8

0.6

0.4

0.2

090 65 45 32

512Mb 1Gb 2Gb 4GbF (nm)

Vm

in(V

)

Cell

SA

LW = 20F 2, tOX = 1.9 nm 64 cells/SA, VDD/2 DL pre.VT0 = 0.2 V

0.6 FD-SOI

1.4

1.2

1.0

0.8

0.6

0.4

0.2

090 65 45 32

32Mb 64Mb128Mb256MbF (nm)

Vm

in(V

)

LW = 2F 2, tOX = 1.9 nmVT0 = 0.49 V (HS), 0.71 V (LP)

LP

HS

0.9

1.1HS*

K. Itoh, Hitachi

16

Approaches to LV SRAMs

1. Use ECC & Redundancy.2. Minimize ΔVT & δVT.

•Large cells with largeMOSTs despite losingbit density

•Symmetric cell layout3. Stay at a high VDD (≥1 V)

due to its still large ΔVT& δVT of bulk CMOS.Even so, power-supply control cells needed for small subthreshold current.

4. Extend low-VDD limitation to sub-1-V with FD-SOI.

M. Khellah, et al., ISSCC Dig., pp. 624-625, 2006

13612311295

1.2

1.0

0.8

0.6

0.4

0.2

0

activestandby

Bit Density (Mb/cm2)

Vm

in(V

)

K. Itoh, Hitachi

17

Sources of extrinsic δVT in the conventional cell:•Pattern deformation after processing •Mask misalignment •Local size fluctuationSolution: Lithographical symmetric cell (“Thin” Cell)

K. Osada et al., IEEE J. SSC, vol. 36, No. 11, pp. 1738-1744, Nov. 2001.M. Kanda et al., Symp. VLSI Tech. Dig. Tech. Papers, pp. 13-14, June 2003.F. Arnaud et al., Symp. VLSI Tech. Dig. Tech. Papers, pp. 65-66, June 2003.

Dotted area: after processingdiffused

poly gate

Conv. (2 cells)

M1 M2

LS cell (2 cells)

M1M2

M1 M2

Symmetric Layout for Small δVT

•Reduced δVT by simple patterns suitable for OPC •DLs shielded by power lines

OPC: optical proximity correction

K. Itoh, Hitachi

18

Power-Supply Control Cellsfor small subthreshold currents

K. Itoh, ICICDT2005 Dig.

DL

VDD+δVD

DLVDD (0) 0 (VDD)

• High VT to reduce iL• δVD to offset a high VT

& δVT

Low leak, wide margin & low power with low-VDD DL.Unscalable MOSTs needed.

Boosted Power Supply Source-Line Driving

• Raised source duringSTB to reduce iL withincreased VT of off-MOST

Reduced margin during STB by δVS (>0.3 V)

VDD

ACT δVSSTB

0

source

K. Itoh, Hitachi

19

Source-Line DrivingAlong with reduced DL voltage at active-standby transition

K. Osada et al. ISSCC2003 Dig. pp. 302-303

Electric-field relaxation90% reduction ingate leakage & GIDL

Sub-S backbias90% reduction insubthreshold leakage

G-S backbias100% reduction insubthreshold leakage

Standby

Active

DL0.5 V 1.0 V1.0 V0.0 V 1.5 V1.5 V

DL VSS

1.5 V

WL 0 V

0.5 V 1.5 V

K. Itoh, Hitachi

20

Measured Retention Current of Cell

K. Osada et al. ISSCC2003 Dig. pp. 302-303

Successful Application1.5-V 27-ns 6.42 x 8.76 mm2 16-Mbusing ECC with 3.2-ns/9.7% speed/area penalties.

(1) Leakage still large1.6 μA for 16 Mb despite high VT , thick tox, and S-driving.(2) Reduced QS in standby modeThe cell power-supply decreases by the raised source voltage.Further low-VDD operation may behazardous, even if ECC is used.

Limitations and Challenges

Conv.

Prop.

25ºC

Sub. + GIDL 48.5

PMOSNMOS NMOS

95 fA

PMOS

17 fA

Tunnel 46.5

3 14VT (extrap.) = 0.7 V(N), -1 V(P)tox (electrical) = 3.7 nm

NMOSConv.

102 fA

PMOS

1244 fA

Prop.

PMOSNMOS

90ºC

Sub. + GIDL 1182

Tunnel 62

81Subthreshold currentsensitive to temp.

K. Itoh, Hitachi

21

Source-Line Driving

=VDD –Vmin(STB)

VDD

Vmin(STB) SRAMarray

δVS

+

VREF

ACT STB

M. Khellah, et al.,ISSCC Dig. pp. 624-625, 2006

Vmin(STB) : Min. VDD to retain the data of all cells in the array.

Lower VT0 → Larger δVS

→ Higher VT0 with deeper body bias (ΔVT)→ Lower iL

to reduce leakage & its variation while retaining the data

VD

istr

ibu

tion

VDDVmin(STB)

VT0

ΔVT δVS

VTmax

K. Itoh, Hitachi

22

Double-Gate FD-SOI•Small ΔVT & negligible δVT

(ultra-thin & lightly-doped channel)•Adjustable VT → multi-VT

•Large VT change(wide-range well-bias control)

•Reduced SER & small ipn

•Dynamic VT MOST(e.g., G-well connection)

M. Yamaoka et al., Symp. VLSI Circuits 2004, R. Tsuchiya et al., IEDM2004 Dig. pp. 631-634

Back-gate voltage Vwell (V)

0.2

0.1

0.0

-0.1Thre

shol

d vo

ltag

e V

t(V

)

-1.0 -0.5 0.0 0.5 1.0

nMOSTVt @VDS =1.0 VtSOI =20nm

tBOX = 100 nm

10 nm

B

A

σint90 nm bulk

65 nm bulk

45 nm bulk32 nm bulk

65 nm FD-SOI45 nm FD-SOI

32 nm FD-SOI


σ(VT)σext

σintσext σ(VT)

σint

G

S D

p+(VBN )

G

S D

n+(VBP )

p+

S DG

S DG

n+

n-well

p-sub

NMOST

SOI( ≤ 20nm)

BOX (≤ 10nm)

PMOST

p-sub

K. Itoh, Hitachi

23

M. Yamaoka et al., SOI Conf. Dig. pp. 109-111, Oct. 2004

SRAM Cells with Dynamic-VT MOSTs

M. Yamaoka et al., A-SSCC Dig. pp. 109-112, Nov. 2005

M1: decreased VT M2: increased VT

M3: increased VT M4: decreased VT

DL DL

VDD0VDD

VDD

M1 M2

M3 M40

Write margin improved withdecreased VT for driver/transferMOSTs & increased VT for load MOSTs.

W

0

DL DL

VDD

0 R1.0 V

RW 1.0 V

M1 M2

M3 M4M5 M6

to widen the voltage margin

K. Itoh, Hitachi

24



•Reduce cell size


e-RAM

RAM cellarray

DRAMSRAM

periph.DL

SRAMDRAM

WL VDD

0

"1"

"0"

DLWL

0 VDD

DL

Cs

Peripheral Circuits•Reduce leakage-Increased ISTB & IACT


K. Itoh, Hitachi

25

Gate tunneling current (iG)• Insensitive to VG & temp. • Sensitive to tox

1/10 iG -reduction with tox -increment of only 2-3 Å for SiO2, whilethe same reduction with VG -decrement of as much as 0.5 V.Such a large VG control in low-VDD region is risky.

Device designers are responsible for the reduction. (High-k)

Subthreshold current (iL)• Insensitive to device structures• Sensitive to VG ,VT & temp thatcan be controlled by circuits.

1/10 iL-reduction with VT -increment, orVG -decrement of only 100 mV.

Circuit designers are responsible forthe reduction.

Leakage Currents of Periphery

iL ∝ W 10(VG-VT )/S

S ~ 100mV/dec.@100ºC 1/10 with ΔVT = 100mV

or ΔVG = -100mV

VG

iLW

K. Itoh, Hitachi

26

Subthreshold Current (iL) of Periphery

K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001Y. Nakagome et al., IBM J. R&D, Vol.47, No.5/6, Sep./Nov. 2003

1. Input-Predictable LogicDesigners can preparethe schemes in advance.

2. Slow Cycle (tRC =25, 60 ns)Each circuit is active for onlya short period within “long”cycle, enabling additional time for iL-control.

3. Iterative-Circuit BlocksMajor iL sources. All circuits in each block areinactive, except selected one.

4. Robust CircuitsiL-immune NAND dec. (w/o iL-sensitive NOR dec.)

5. On-Chip Power SuppliesVDH &VBB utilized for dual-static VT.

non

-se

lect

edsele

cted selected WL

sele

cted

YL

Rowdec.

non

-se

lect

ed

WD Memory array

selected

non-selected

non-selected

Col.dec.

φP

axiVDH 0φX

dynamicNAND

ayi

VDD 0

φY

staticNAND

CLK

axi

WL

selected

non-selectedVDH

tRC

ayi

YLVDD

VDH

VDD

Features of RAM Periphery

K. Itoh, Hitachi

27

•At present, VT is still so high that iL is small in active mode, though iL dominates in standby mode.

•In the future, with further reducing VT, iL will dominate evenin active mode. Leakage reduction for active mode is the key.

Cu

rren

t (A

)

Trends in DRAM Peripheral Current

Capacity (bits)16M 64M 256M 1G 4G 16G 64G10-6

10-5

10-4

10-3

10-2

10-1

100

1011.2 A

IAC

IACT

IDC (IL)

Cycle time=180 nsT = 75°C, S = 97 mV/dec.

0.160.24 0.190.53 0.40 0.32 0.13

VDD (V)

Extrapolated VT at 25°C (V)

1.01.21.53.3 2.5 2.0 0.8


iL-Increase in Periphery

IACT = IAC +IDCIAC = ΣCj VDD fIDC = ΣiLk ∞ ΣWk 10-VT/S

VT = aVDDk >> j

chip (active)

Inactive (k)

Active (j)

K. Itoh, Hitachi

28

•Use high-VT MOSTachieved statically or dynamically with VTh =VTl + ΔVT

•For static high-VT

ΔVT by ion impla. orstatic-VBB application.

•For dynamic high-VT

ΔVT by dynamic back-biasing schemesG-S back-bias is best due to large ΔiL/Δδ, applicable even to active mode.

Offset Voltage, δ (V)

Leak

age

Red

uct

ion

(ra

tio) 1

10-1

10-2

10-3

10-4

0 0.2 0.4 0.6 0.8 1.010-5

L = 90 nm, tOX = 2 nmVDD = 1 VS = 100 mV/decadeK = 0.2 V1/2, 2ψ = 0.6 Vλ = 0.05

VDD

0

+δ0

VDD

0

0

-δ

VDD

0

0

-δ

VDD

+δ0

VDD -δ0

0

0(DIBL)

NMOS

∼−ΔVT

k (√δ +2ψ -√2ψ )ΔVT δ∼−

Basic Concept of iL-Reduction

Y. Nakagome et al., IBM J. R&D, Vol.47, No.5/6, Sep./Nov. 2003

K. Itoh, Hitachi

29

Three Practical Reduction CircuitsApplicable even to Active Mode

Switched-Source Imp.(G-S Self-Backbiasing)

Power Switch utilizinginternal power supply(G-S Offset Driving)

Dual-Static VT utilizing internal power supply

(VDD)

IN

(0)

VDD

OUT

SSI

VDD

OUT

(0)(VDD)

IN

SSI

VDD

VDD

low VT–VBB

low-VTcore

–VBB

VDD VDD

VDH

(>VDD)

VDDVDH (>VDD)

low VT0

low-VTcore

δ

VDD - δ

K. Itoh, Hitachi

30

No matter how large i1 is, itis confined to const. current i2’ with self-adjusting δ.

Stacking effects (δ = 0.2 V)• G-S backbias of Q1 (1/100)• Sub-S backbias of Q1 (1/1.5)• DIBL effect of Q2 (1/2)

Applicable even to active mode• Fast iL-control capability with

small δ & CL and self-reduction• Small area penalty if applied

to iterative circuit blocks• Capability of confining to min.

active circuitry

SSI (G-S Self-Backbias)

M. Horiguchi et al., Symp. VLSI Circuits Dig., p. 47, 1993.

for fast iL-control of input predictable logic

i1’ = i2’∴δ = (S/ln10) ln(W1/W2)

Reduction Ratio γ =i1’/i1 =10−δ /S =W2/W1

• Smaller iL (=i2’) & larger δ with smallerW2

• γ = 1 (no reduction) for W2 =W1Other secondary effects reduce iL.(Sub-S backbias & DIBL)

circuits

Q1

0

i0 : current density

i1=i0W110-VT/S

w/o SSI with SSI

Q1

0

Q2

0

const. current

δ

i2’=i0W210-VT /S

i1’ =i0W110- (δ +VT)/S

SSI

W1 W1

W2

K. Itoh, Hitachi

31

Inverter Chain

• For 0-V input, iL flows from an n-MOST in each 0-V input inverter, and accumulatesinto SSI.

• SSI confines to its constantcurrent (=i0 W2 10-VT/S ).

•W2 ≅w1 ≅ ··· ≅wn without speedpenalty because each inverterswitches at different timing.

• Area penalty is negligible with increasing the number ofinverters because W2 « Σwi .

Such is the case for p-MOST SSI.

Small Area Penalty with SSI Sharing

M. Horiguchi et al., IEEE J. Solid-State Circuits, vol. 28, no. 11, pp. 1131-1135, Nov. 1993.

ΦDVDD

VDD

ΦS0

VDD

0VDDIN

0

SSI

SSIVDD -δ

δ

w1

W2

w20

K. Itoh, Hitachi

32

• During non-selected periods iL (= i’ ) flows from each circuit, and accumulates into SSI.

• SSI confines to its constant current (=i0 W2 10-VT/S).

• W2 ≅w without speed penalty because only one MOST is activated with SSI on.

• Area penalty is negligible with n » 1 because W2 « nw.

Small Area Penalty with SSI Sharing

M. Horiguchi et al., IEEE J. Solid-State Circuits, vol. 28, no. 11, pp. 1131-1135, Nov. 1993.

Iterative Circuit Block (non-selected/standby)

= 0Q1

W1 =nw

i1’=ni ’

i ’0wQ

0Q2

SSI

i ’0wQ

W2

n

δ

K. Itoh, Hitachi

33

Confining to Minimum Active CircuitryPartial activation of multi-divided block


1,023i → 134ifor n/m =1024/8

block (selected)

n

(n -1)i

activatedQ 0

i0Q VDD

i0Q VDD

VDD w

i =i0 w 10-VT/S

subblock subblocks(selected) (non-selected)

i2’=i0 W2 10-VT/S ≅ i , W2 ≅ w

n/m

#0 #1 #m -1

(n/m -1)i

i0Q

VDD

SSI

VDD

Q

0

0Q2

δ

• • •

0

δ

0

VDD

≅ (m -1)i

W2 W2

w

i2’ i2’

K. Itoh, Hitachi

34

Low-VT switch (Q) shuts off the supply of low-VT core during standby. A raised VDH needed to cut off Q with G-S backbias.

Problems:1. If VDH generated by charge pump, • Unregulated floating VDH

For well-regulated VDH,C2VDHf < CPVDDfP , C1 »CP , C1 »C2 , level monitor.

• Increased pump powerFor low pump power with keeping the VDH level, CPVDDfP & C2VDHf reduced.-> Smaller C2 & slower f

2. Area penalty by large Q3. Slow recovery of internal power node ( )

Power Switch (G-S Offset Drive)


VDH Gen.C1 C2

φlow VT

fP VDD CP

VDD VDD

VDH (>VDD)

0

ACT STB

Low-VTcore

Q

φ

f

Levelmonitor

K. Itoh, Hitachi

35

Applicable even to active mode, if the switch itself operates fast enough. After evaluating the input, the output level continues to be held by high-VT holder without leakage. Otherwise

•Floating output discharges, causing a large iL at pMOST in the succeedingcircuit, in which the switch is still on.

•Unnecessary discharging prevents the output from quick recovery.

Power Switch with Level Holder

VDD

Level holder

in outVDD

Low-VTcircuit

VDD

Low-VTcircuit

High-VT

off

VDD with

w.o.

0

iL


K. Itoh, Hitachi

36

Dual Static VT


iL reduced to 1/5 for uniform use of VTlwith assumptions: Wtotal (critical path)=10% of Wtotal (chip), VTl = 0.21 V, VTh = 0.31 V, S = 0.1 V/dec.

highVTlowVT

criticalpath Chip

Selective use of a high VT to• Off-MOSTs during standby• Non-critical path, while using

low VT to critical path.-> Low iL & high speed chipThe reduction is not remarkablebecause VT difference must besmall. A large VT difference may cause a racing problem: a pulse-timing imbalance between VTl -& VTh-circuits.

Useful for active & standby modesVTh

VDD

VTl

'L''H''L'(standby)

VDD

VTl

VTh

K. Itoh, Hitachi

37

256-Mb DRAM (Standby)

VDH

(VDH)

VDD

VDH

Memory array

VDH

RX

I/O SA

Sub-word driver

SWLVDH

VBB

MWLVDH

VBB

VDHL

φH

VDDL

(VDH)

(VDH)(0)

(0)

(VDH)

YL(0)DL DL

VBB

φD

(VDH)RX

VDHArray Control

(VDH)

(VDD)SSI2

SSI1

fromrow dec.

Column decoder & driver

Sense amplifier

Main-word driverM. Hasegawa et al., ISSCC Dig. pp. 80-81, 1998.

K. Itoh, Hitachi

38

M. Hasegawa et al., ISSCC Dig. pp. 80-81, 1998.

40 µA with dual VT

Conv.

ProposedPower downself-refresh

1.28 mA

0.21 mA

Dual static VTSSI

T = 75°CS = 109 mV/dec. (PMOST)

89 mV/dec. (NMOST)VT = 0.03 V (PMOST, 0.7 nA/μm)

-0.02 V (NMOST, 0.7 nA/μm )VDD = 2.0 V, VDH = 3.8 V, VBB =-1 V

Peri. Drivers Y-dec Arraycontrol

Standby Current Reduction (256 Mb)

K. Itoh, Hitachi

39

Conv.

1180 mA

Proposed

69

SA

VDH = 1.75 V, VDD = 1 V, tRC = 180 nsVT = -0.12 V (2nA/μm), S = 97 mV/dec., 75°C

AC

75

DC

word drivers695

(subthreshold) 1105

decoder209

others132

drv.

75

116

41

SSI power switch with level holder

1-V 16-Gb DRAM

T. Sakata et al., 1993 Symp. VLSI Circuits.

Active Current Reduction

K. Itoh, Hitachi

40

K. Hardee et. al, ISSCC2004 Dig. p. 200

0.6-V 16-Mb e-DRAM

• Some int. voltages are controlled to compensate for Δ (iL, τ) caused byΔ (VT, T, VDD).• In sleep mode, 0.3-VG-S b.b. reduces SA’s iL.

0.9 V

VNB

VNSB

on-chip converters

VPB

VPSB

3 V

ExternalVDD (0.6 V) VDD I/O (2.5 V)

-0.3 V

ND

0.9

-0.3

0.9

PD

VSPVDD

VPBSSI2PG

VSN

SENVPB

VNB

VDD

VNB SSI1

0

0.6 V-δ

0.6 0

-0.3

δNG

P-switch driver (inverter chain)

0.6

K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp. 339-344, Oct. 2004

Y Circuits 0.6 V

-0.3

VPSB

DL0.3 V

VDD

VPB

VNSB

VNB

DL

40 fF

SA0.2-VVT

ND

PD

DL0

256WLs

0.60.9

DL

P-switch

P-switch

K. Itoh, Hitachi

41

2.5 V 3 V

0.6-V 16-Mb e-DRAM

2.5

SSI2XE1 0

2.5

3

2.5

PRE

ai

dec.

VNB

XE3 0 SSI3

3

level shifter

word driverXE2

0

3

XDE SSI1

VNB

33

WL0

WLn-1

2.5

0

0

2.5

0

3

0

2.5 K. Hardee et. al, ISSCC2004 Dig. p. 200K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp. 339-344, Oct. 2004

X Circuits (Active)

K. Itoh, Hitachi

42

X Circuits (Sleep)

0.6-V 16-Mb e-DRAM

XDE-0.3

32.5

2.5 V 3 V

2.5

SSI2XE1 2.5

2.5

3

2.5

PRE0

ai0

dec.

VNB

XE3 3 SSI3

3

level shifter

word driverXE2

2.5

3

SSI1

δ1

3 -δ3

3

VNB

33

2.5-δ2

WL0

WLn-1

0

0

0

0

K. Hardee et. al, ISSCC2004 Dig. p. 200K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp. 339-344, Oct. 2004

K. Itoh, Hitachi

43

Active Mode4-bank arch. with one-bankactivation confines active circuitry to 1/4, and reduces•AC power of cont. signals•iL in inactive banks if SSI

is applied to WD & cells.SSI1 : Small δ1 & CL → 0.3 nsSSI2 : Drawbacks;

Large δ2 (0.4 V) & CL → 3 nsCell-supply reduced by δ2

Sleep ModePeriphery off withpower switch off → 3ns

Multi-Bank Architecture

M. Yamaoka et. al., ISSCC2004 Dig. p. 494K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp. 339-344, Oct. 2004

1.2-V 1-Mb e-SRAM

VDD

BS0

δ2SSI2

SSI1

0

other periphery(SA, write amp, etc.)

BK0BK1

BK2BK3BS3

BS1

BS2

VDD

BS0

VDD

WL0

0

0

WL1

WLn-1

VDD

0δ2 δ2

WD0

VDD -δ1

K. Itoh, Hitachi

44

Leakage of 1-Mb e-SRAM (Active)

M. Yamaoka et. al., ISSCC2004 Dig. p. 494

VT = 0.4/0.3 V

cells (VT = 0.4 V) word drivers amp.Conv.

(300 MHz)

SSI1(300 MHz)

SSI1 & SSI2P-switch

(100 MHz)

460 μA(1)

350 μA(0.75)

150 μA(0.33)

1.2 V, room temp.

K. Itoh, Hitachi

45



•Reduce cell size


e-RAM

RAM cellarray

DRAMSRAM

periph.DL

SRAMDRAM

WL VDD

0

"1"

"0"

DLWL

0 VDD

DL

Cs



K. Itoh, Hitachi

46

Ever-increasing ΔVT,and rapidly-lowering gate-over drive with device scaling.They enhance speed variation of peripheryΔτ/τ ∝ ΔVT/(VDD –VT)Solutions

•For inter-die Δτ,Compensation with VBB generator. e.g., Speed improvement by 63%

•For intra-die Δτ, FD-SOI

Speed Variation90 nm bulk

65 nm bulk

45 nm bulk

32 nm bulk

65 nm FD-SOI

45 nm FD-SOI

32 nm FD-SOI


σ(VT)σintσext

σintσextσ(VT)

Process Technology (nm)

4

3

2

1

0 600 32250 130 65LP SOC

MPUITRS 2001

Gat

e O

ver

Dri

ve ,

VD

D –

VT

(V)

M. Yamaoka et al., Symp. VLSI Circuits 2004

K. Itoh, Hitachi

47

IDS (M1) is a good indicator of iL& speed. VGS (M1) = VDD/2 ≅ VT.VD is compared to VDD/2 + Δ andVDD/2 – Δ to determine if VNBshould be increased or decreased.

e.g.,For low VT (fast process or high Tj)VD < VDD/2 – Δ. The lower OP activates PUMP, so VNB starts to decrease and VTis increased to compensate. For high VT (slow process or low Tj)VD > VDD/2 + Δ. The upper OP discharges M2-gate for driving the body, allowing VTto be reduced and compensated for.Such is the case for VDD.

VBB Generator for NMOS Body

K. Hardee et. al, ISSCC2004 Dig. p. 200Temp (°C )

-25 0 25 50 75 100 125Fast Process

Slow Process0.6 V (VDD)

0.7 V

0.8 V

0.6 V

0.7 V0.8 V

0.4

0.2

0.0

-0.2

-0.4

-0.6

VN

B(V

)

0.7 V(VDD )

M12.5 V

M2

VD

VDD /2

VDD/2– Δ

2.5 V

VDD

VDD/2+ Δ

2.5 V

PUMP

VNBLIMIT

2.5 V

Max.=1/2VDD

Min.=-2/3VDD

φ

φ

K. Itoh, Hitachi

48

Intra-Die Speed VariationLow-Power CMOS LSIs

0.9 0.8 0.7 0.6

0

1

2

3

4

90 65 45 32

τ(V

T0 +

ΔVT)

/τ

(VT0

)

bulk SOIΔVT (+)

ΔVT (–)

1 1.29 1.89 2.51– 0.23 0.38 0.50

VDD(V)F (nm)

σ(VT) bulk (ratio)σ(VT) SOI (ratio)

L/W = 1F/6FVT0 = 0.3 V, ΔVT = 3σ(VT)τ (VT) ∝ VDD/(VDD –VT)1.25

0.530.861.19

3.76

0.861.19

(ITRS’03)

+–

K. Itoh, Hitachi

49



•Reduce cell size


e-RAM

RAM cellarray

DRAMSRAM

periph.DL

SRAMDRAM

WL VDD

0

"1"

"0"

DLWL

0 VDD

DL

Cs



K. Itoh, Hitachi

50

RAM Cells (DRAM)Short DL allows a small CS & simple CS-structure with small CD.Planar-CS cell might replace e-SRAM cells. vsig ≅ CS/CD ⋅VDD/2.In addition, short DL enables low-VDD fast operation.

proposed (ISSCC2005) conventional

Cells/DL 32 128CS 5 fF (Ta2O5; MIM) ≥ 15 fF (MIS)

Additional wire No local wire (M0)Thermal budget no impact on logic intolerable impactCell RC delay W storage cont. Non-metalized cell

Co-salicided S/DCell contact R 10 Ω 10 kΩ

M. Iida et al., ISSCC2005 Dig. p. 460, M. Shirahata et al., ISSCC2005 Dig. p. 462

M3

M2

DL (M1)

Logic DRAM

M1

DL(M0)

M3

M2

M1 DL

Logic DRAM

K. Itoh, Hitachi

51

Stacked TFT SRAM Cells

S.-M. Jung, et al., Symp. VLSI Tech. June 2004, Y.H.Suh et al., ISSCC2005 Dig. p. 476.

Cell Size Reduction (6-T SRAM Cell)

• Single-crystal TFTThe highest density cell(25F 2) comparable to DRAM cells.1.8-V 61.1-mm2 144-MHz256-Mb SRAM.

• Drawbacks as e-SRAMsSophisticated process, High-VDD operation due to TFT PMOST ofS =140 mV/dec.,IDS = 2/3 of the bulk.

Load p-TFTs & transfer n-TFTsdouble-stacked over bulk driver n-MOSTs in different levels of layers.

K. Itoh, Hitachi

52

Cell-Size Comparisons

Cel

l siz

e (r

atio

)20

01-T 1-T 4-T 6-T

15

5

(Sta

nd-

alon

e 8

F 2

)

1

20.5

3-T 3-T

3.65.6

6.7

SAC for stand-alone DRAMNo SAC for others

1.8

10

3 polySAC 3 poly

3

L.I.

3D

3D

14

3

K. Itoh, Hitachi

53

6-T SRAM Cell: Due to high necessary VT & large ΔVT•Not suitable for sub-1-V VDD,•Continue to be used for a high VDD (≥ 1 V).Challenge; Small-ΔVT MOSTs. TFT cells for stand-alone SRAMs.

1-T DRAM Cell: •Suitable even for sub-1-V VDD. Challenges; Planar capacitors, Small-ΔVT MOSTs.

Peripheral Circuits:•Subthreshold-currents will be reduced sufficiently with existing techniques even for active mode.

•Speed variations will continue to be serious.Challenges; VBB control, Small-ΔVT MOSTs.

Two Approaches:High-VDD bulk-CMOS for low-cost RAMs,Low-VDD FD-SOI for high-speed low-power RAMs.

Future Prospects for RAMs

K. Itoh, Hitachi

54

1. I discussed challenges and trends in LV RAMs.2. I reviewed state-of-the-art LV RAM circuits.3. I gave prospects of RAMs with emphasis on

further needs for•Ultra-low voltage RAM cells, •Advanced devices & circuits to reduce speed

variations.

Conclusion

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