IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011 479
An Accurate Two-Port De-Embedding Techniquefor RF/Millimeter-Wave Noise Characterization and
Modeling of Deep Submicrometer TransistorsXi Sung Loo, Kiat Seng Yeo, Senior Member, IEEE, Kok Wai J. Chew, Member, IEEE, Lye Hock Kelvin Chan,
Shih Ni Ong, Manh Anh Do, Senior Member, IEEE, and Chirn Chye Boon
Abstract—An accurate and simple noise de-embedding tech-nique is proposed for high-frequency noise characterization oftransistors. It is demonstrated on 0.13- m CMOS devices forup to 80 GHz. The proposed technique adopts a generalizedtwo-port fixture model in conjunction with a set of shielded basedstructures, which enable simple de-embedding of fixture parasiticfor up to the Metal 1 level. Unlike other methods, it is capable ofsimultaneously accounting for the parasitic effects of probe to padcontact impedances and metal finger parasitic while using onlythree dummy test structures. Also, it is designed to accommodatenonsymmetry between bond pad parasitic elements at two-portwithout consuming additional silicon area. This corresponds toa reduction in noise de-embedding error, which increases alongthe frequency domain (6% of NFmin at 80 GHz). Meanwhile,underestimation of metal finger parasitic by conventional tech-niques has lead to degradation in noise performance (NFmin)of 0.13- m CMOS transistors by more than 3.5 dB at 80 GHz.Further validation results from extracted gate capacitance andtransistor gain performance provide solid support to the proposedde-embedding technique.
Index Terms—Layout, MOSFETs, scattering parameters, semi-conductor device noise.
I. INTRODUCTION
R APID advancement in wireless technology over the pastfew decades has pushed transistor devices to operate in
the vicinity of 100-GHz frequency. As a consequence, high-fre-quency noise has emerged as a dominant issue in RF integratedcirciut (RFIC) design, which is further worsened by scaling ofpower supply and increase in complexity of RF circuits. Thisdrives the need for precise transistor noise model, which re-lies greatly on accurate high-frequency noise characterizationof the transistor device. A robust noise de-embedding techniqueis therefore essential to correctly extract the intrinsic noise pa-rameters of the transistor device by completely removing sur-rounding parasitic noise effects of the test fixture. However, thedominance of fixture parasitic effects as a result of drastic re-
Manuscript received June 26, 2010; revised September 24, 2010; acceptedNovember 03, 2010. Date of publication January 10, 2011; date of current ver-sion February 16, 2011.
X. S. Loo, K. W. J. Chew, and S. N. Ong are with VIRTUS, Integrated Cir-cuit (IC) Design Centre of Excellence, School of Electrical and Electronic En-gineering, Nanyang Technological University, Singapore 639798, and also withGLOBALFOUNDRIES Singapore Pte Ltd., Singapore 738406.
K. S. Yeo, L. H. K. Chan, M. A. Do, and C. C. Boon are with VIRTUS,Integrated Circuit (IC) Design Centre of Excellence, School of Electrical andElectronic Engineering, Nanyang Technological University, Singapore 639798.
Digital Object Identifier 10.1109/TMTT.2010.2097770
duction in NFmin of CMOS device along the scaling trend [1],[2] has imposed great challenges to noise de-embedding.
Several publications on noise de-embedding techniques,which are based on the series-parallel equivalent-circuit model[3]–[5] and generalized network model of test fixture [6]–[10],have been reported. The latter type of technique is wellknown for its high generality and ability to account for thetransmission line effects of interconnects at high frequency.However, the forward coupling mechanisms that exist on thelossy substrate of the test fixture is not addressed in cascadetwo-port-based techniques [6]–[8]. Meanwhile, high generalityof a four-port-based noise de-embedding technique [9], [10]is compromised by ideality assumptions made on the intrinsicstandards of test structures. This results in accuracy degradationof the de-embedding method at high frequency. On the otherhand, the complexity level of equivalent-circuit-model-basedtechniques increases from [3]–[5] as accuracy at higher fre-quency of characterization becomes critical. The more recenttechnique [5] is superior to other methods, as it is able to re-move parasitic effects of the test fixture for up to metal fingers(Fig. 3). Therefore, it is increasingly important for transistorcharacterization as the de-embedding reference plane is shiftedcloser to the desired boundary of device. However, it ignoresthe parasitic effects of probe to pad contact impedance andcould only de-embed for up to the Metal 2 level of the testfixture. It is also associated with expensive implementationcost and high de-embedding complexity, as it requires the samenumber of test structures as [9] for the same purpose.
In this paper, a simple and accurate noise de-embeddingmethodology is presented for noise characterization and mod-eling of two-port transistor devices. It provides more accurateprediction of the bond pad parasitic than other methods andcould de-embed test fixture parasitic for up to the Metal 1 levelwhile consuming 40% less silicon area than [5]. In the proposedde-embedding technique, the test fixture parasitic is modeled bygeneralized two-port networks to achieve high de-embeddingaccuracy and alleviate the complexity of de-embedding due toparasitic extraction. In particular, the proposed noise de-em-bedding technique would be demonstrated on CMOS devices.Such a noise de-embedding technique would be explained inlength in Section II. In Section III, the noise de-embeddingresult is compared with other methods.
II. NOISE DE-EMBEDDING METHODOLOGY
In the proposed noise de-embedding technique, two port net-works (Fig. 1), and are used, respectively, to model
480 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 1. Test fixture model of transistor test structure (DUT), which encom-passes cascade parasitic networks �� �� �, parallel coupling network�� �, and series parasitic network �� �. Note that DUT is the acronym for“device-under-test.”
Fig. 2. Schematic layout of ground shielded based transistor test structure(DUT) in ground–signal–ground (G–S–G) configuration.
Fig. 3. De-embedding techniques that are proposed in [3], [4], and [6]–[10]are designed to remove test fixture parasitics up to interconnect boundaries (Å )only. The proposed technique, which is based on mix series-parallel configura-tions of the parasitic, is able to establish de-embedding reference plane at theMetal 1 level of metal fingers (B).
both series and parallel parasitic of interconnects plus metal fin-gers. Both and are not necessary to be reciprocal andare valid regardless of circuit configuration of parasitic compo-nents. The complicated steps in extraction of fixture parasiticcomponents are avoided as only two-port network parametersof and are needed to be known. Both cascading net-works, and , represent the bond pad parasitics thatappear at Port 1 and Port 2, respectively. Instead of modeling it
Fig. 4. Types of dummy test structures that are adopted in proposed noisede-embedding techniques: OPEN, SHORT, PAD SHORT-OPEN, and PADOPEN-SHORT.
Fig. 5. Network/circuit models of dummy test structures that used for extrac-tion of fixture parasitic. The circuit model of the PAD SHORT-OPEN structureis identical to [4], with the exception that the bond pad parasitic components arenot assumed to be the same, which results in higher generality and accuracy.
with a single admittance element [6]–[8], it is described by twomajor components, probe to pad contact impedance ,and pad to ground impedance . The proposed noisede-embedding technique differs from [4] in that the bond padparasitic elements of and are not necessary to beidentical. As a result, it could be applied to more general cir-cumstances.
A. Test Structure
Fig. 2 illustrates the schematic layout of the ground shieldedbased [12] transistor test structure that is used for characteri-zation purposes. It consists of eight metal layers and is fabri-cated on GLOBALFOUNDRIES’ 0.13- m CMOS technology.The intrinsic nMOS device lies in the fixture gap of the Metal 1ground shield and is surrounded by P guard rings. The wideMetal 1 ground shield is set as the ground reference plane andhas a negligible resistance value [12]. The enlarged view of annMOS device is shown in Fig. 3.
LOO et al.: ACCURATE TWO-PORT DE-EMBEDDING TECHNIQUE 481
Fig. 6. Comparisons between measured (DUT) and de-embedded power gain ��� �� of transistor devices [(a) Width � � � � �m, Length � ���� �m and(b) and (c) Width � �� � �m, Length � ��� �m]at various dc-biasing conditions [(a) and (b) � � � � �� V and (c) � � � V, � � ��� V] forfrequency range from 4 to 80 GHz.
In order to minimize the parasitic effects of narrow intercon-nects, broad signal pads are designed to allow probes movingcloser to the intrinsic nMOS device. Meanwhile, the width ofthe signal pad is optimized to minimize the coupling betweenpads. Edges on the interconnects and bond pads are chamferedto minimize parasitic effects that are induced by step disconti-nuities [13].
Four types of dummy test structures (Fig. 4) are required forcharacterization of fixture parasitic, namely, OPEN, SHORT,PAD SHORT-OPEN, and PAD OPEN-SHORT. However, onlythree dummy test structures are required for fabrication asPAD OPEN-SHORT could be realized by simply rotatingPAD SHORT-OPEN 180 during on-wafer measurement. Thisdirectly saves the cost of implementation while fulfilling therequirement of proposed noise de-embedding technique. TheOPEN test structure is simply a fixture frame (without device)that encompasses lead fingers at both the Metal 1 and Metal 2level. The SHORT test structure is a similar version of OPENtest structure with no fixture gap. The lead fingers are directlyconnected to a highly conductive Metal1 ground shield throughVia1 without introducing additional connection parasitic, ascompared to [5]. Also, the forward coupling effects on theproposed SHORT structure can be neglected as there is nofixture gap. With these layout configurations, the parasiticeffects of lead fingers can be effectively de-embedded up to theMetal 1 level. Both the OPEN and SHORT structures that arepresented in [3] and [4] differs from the proposed techniquethat the metal fingers are not included. On the other hand, bothPAD SHORT-OPEN and PAD OPEN-SHORT structure consistof only bond pads, which are shorted by wide interconnects atonly one port than the other.
B. Characterization of Fixture Parasitic
The equivalent two-port network/circuit models of test struc-tures are shown in Fig. 5. The model of the OPEN structure issimilar to the DUT test fixture model, but without the intrinsictwo-port device due to its layout configuration. On the other
hand, the parasitic effects of the Mp in SHORT structure is ig-nored as there is negligible forward coupling effect, whereas thecouplings to ground at device boundaries are shunted by SHORTinterconnections. Bond pad parasitic elements that appear atPort 1 and Port 2 of test fixture are extracted from one-port -pa-rameter measurements on both the PAD SHORT-OPEN struc-ture and PAD OPEN-SHORT structure. The procedure for ex-traction of the fixture parasitic is summarized as follows.Step 1) Extract parasitic components of bond pad from mea-
sured one-port -parameters of PAD SHORT-OPENstructure and PAD OPEN-SHORTstructure
(1)
(2)
where is the system characteristic impedance.Step 2) Determine two-port network parameters of series
parasitic network from measuredparameters of SHORT structure . The obtainedresult, , is converted into the -matrix
(3)
where and are converted from theirequivalent -matrices
(4)Step 3) Extract two-port network parameters of parallel par-
asitic network from measured param-eters of the OPEN structure
(5)
(6)
482 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 7. Comparisons between measured (DUT) and de-embedded noise parameters (NFmin, Rn, and Topt) of transistor devices [(a) and (b) Width � �� � �m,Length � ���� �m and (c) Width � �� �� �m, Length � ���� �m] at various dc-biasing conditions [(a)–(d) � � � � ��� V) for frequency range from4 to 26 GHz. Note that the de-embedded noise parameters by proposed technique and other compared techniques [3]–[5] are almost identical in (c) and (d).
C. Procedure for -Parameter De-Embedding
The procedure for -parameter de-embedding is as follows:Step 1) De-embed parasitic effects of and from
raw measured parameters of transistorstructure . Convert the de-embedded result
to the -matrix
(7)
Step 2) De-embed parasitic effects of
(8)
Step 3) De-embed parasitic effects of and convert thede-embedded result, to the matrix,
(9)
D. Procedure for Noise De-Embedding
The procedure for noise de-embedding is as follows.Step 1) Convert measured noise parameters ( ,
, and ) to the noise correlationmatrix (in chain representation) by method[14]. Calculate , , , andfrom , , , and by applying method[15].
Step 2) Convert , to , andde-embed parasitic noise effects of cascade compo-nents
where ,
, and superscript denotes the
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Fig. 7. (Continued.) Comparisons between measured (DUT) and de-embedded noise parameters (NFmin, Rn, and Topt) of transistor devices [(e) and (f) Width �
� � �� �m, Length � ���� �m] at various dc-biasing conditions [(e) and (f) � � � V, � � ��� V] for frequency range from 4 to 26 GHz. Note that thede-embedded noise parameters by proposed technique and other compared techniques [3]–[5] are almost identical in (e) and (f).
Hermitian complex conjugate transpose
(10)
Step 3) De-embed parasitic noise effects of series network.Convert to
where
(11)
Step 4) De-embed parasitic noise effects of the parallel net-work. Convert to
where
(12)
Step 5) Lastly, convert to and calculate thenoise parameters of the intrinsic transistor device( , and ) by applying themethod [14]
where (13)
III. DE-EMBEDDING VERIFICATION AND RESULTS
Noise measurements of 0.13- m nMOS devices are per-formed by the ATN NP5B measurement system in conjunctionwith HP8510C VNA for a frequency range from 4 to 26 GHz.Measurements at frequency below 4 GHz are avoided as themeasured NFmin of the transistor approaches an uncertaintylimit of instrument [1], [2]. Meanwhile, device characterization
at millimeter-wave frequencies ( 30 GHz) is performed byan Agilent E8361A PNA (with a frequency extension module)through -parameter measurements. Additional OPEN andSHORT structures of [3] and [4] (without metal fingers) are fab-ricated for verification purposes. All test structures of [3]–[5]are based on the same shielded pad frame as the proposedstructures for fair comparison of de-embedding techniques.
A. Impact of Fixture Parasitic on Transistor Power Gain
In this section, the performance of de-embedding techniquesat millimeter-wave frequencies is investigated on transistorpower gain . Fig. 6(a) shows the measured and de-em-bedded power gain of the nMOS device (Width m,Length m) by various techniques at a dc bias ofand V. The difference between performance ofthe proposed technique with and without considering parasiticeffects of probe to pad contact resistance is small (0.5 dB at80 GHz) for frequencies below 80 GHz. This implies thatthe large discrepancy between performance of the proposedtechnique and [3] and [4] at high frequencies is mainly due toparasitic effects of metal fingers (3 dB at 80 GHz).
On the other hand, de-embedding performance of the pro-posed technique is identical to [5] when the probe to pad con-tact resistance is neglected . In contrast, aslight improvement of transistor power gain over frequency isobserved (0.5 dB at 80 GHz) when the effect of probe to padcontact resistance is taken into account by the proposed tech-nique. This clearly demonstrates that the proposed technique ismore accurate than [5] at millimeter-wave frequencies.
In order to substantiate the verification results discussedabove, the de-embedded power gain of large width nMOSdevices at different dc-bias modes is also demonstrated.Fig. 6(b) and (c) shows the measured and de-embeddedpower gain of an nMOS device (Width m,Length m) by various techniques at both triode
484 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 8. Results from reciprocity tests �� � � � confirm that both transistor devices [(a) Width � ��� �m, Length � ���� �m and (b) Width � ��� �m,Length � ��� �m] are passive at � � ��� � � V. Comparisons between measured and de-embedded NFmin of transistor devices [(c) Width � �� � �m,Length � ���� �m and (d) Width � �� � �m, Length � ��� �m] for frequency range from 4 to 80 GHz at cutoff mode.
( V, V) and saturation regions (and V). The comparison results of de-embeddingtechniques are consistent with those observed in Fig. 6(a)for the device with a smaller width. However, the impact ofde-embedding is smaller for larger gain device due to domi-nance of intrinsic transistor performance over the surroundingtest fixture parasitic. For example, the transistor power gainperformance shows improvement of only 3.2 dB at 80 GHzafter de-embedding by the proposed technique as compared to11 dB for the device with a smaller width at the same dc-biasingcondition ( and V). Both de-embedded powergain performance by the proposed technique and [5] are almostidentical ( 0.2-dB difference at 80 GHz) as the impact of con-tact resistance becomes smaller for the transistor device with alarge size. Nevertheless, the results presented in Fig. 6(a)–(f)confirms that the proposed de-embedding technique remainsvalid regardless of transistor geometries.
B. Comparison of Noise De-Embedding Results
The impact of de-embedding techniques on noise per-formance of the nMOS device with different geometry isalso investigated. Fig. 7(a) and (b) shows the measuredand de-embedded noise parameters of transistor device
(Width m, Length m) for a frequencyrange from 4 to 26 GHz at the saturation mode ( and
V). As evidenced from the results presented in theprevious section, clear separation between the predicted NFminby the proposed technique and [3] and [4] beyond 15 GHz ismainly contributed by parasitic effects of metal fingers. On theother hand, de-embedded noise parameters by the proposedtechnique are in good agreement with [5] for even a lessernumber of dummy test structures used. However, the distinc-tion between de-embedded noise performance of the large sizetransistor by the proposed technique and [3] and [4] remainsnegligible for frequencies below 26 GHz at both saturation [seeFig. 7(c) and (d)] and triode regions [see Fig. 7(e) and (f)].Further, de-embedding by both the proposed technique andcompared techniques only resulted in a slight improvement ofthe transistor NFmin by less than 1 dB at 26 GHz. These resultssupport the claim by [17] that nMOS devices with smallerwidth or size are more vulnerable to de-embedding errors asthe transistor test structure (DUT) is increasingly dominated byfixture components.
Direct noise measurement at millimeter-wave frequencies isimpossible due to the limitation of the existing noise measure-ment system. Instead, the noise parameters of a transistor can
LOO et al.: ACCURATE TWO-PORT DE-EMBEDDING TECHNIQUE 485
Fig. 9. (a) Comparisons between extracted gate capacitance of 0.13-�m nMOS devices by different de-embedding techniques at � � ��� � � V. Com-parisons between bond pad parasitic elements at two-port �� �� ) and �� � � � [magnitude (b) and phase (c)] for frequency range from 4 to 80 GHz.(d) Residual error (expressed in percentage of device NFmin) in de-embedded NFmin of the nMOS device as a result of failure to account for the discrepancybetween bond pad parasitic elements at two ports. NF50 of input and output bond pad parasitic networks �� �� � are also shown for same frequency rangefrom 4 to 80 GHz.
be calculated directly from its two-port network parameters [15]once it operates as a passive device. The equality betweenand (both magnitude and phase) in Fig. 8(a) and (b) con-firms that both of the transistor devices mentioned above are re-ciprocal and passive at the cutoff mode ( and V).Fig. 8(c) and (d) illustrates the comparisons between the ex-tracted and de-embedded NFmin of the nMOS devices by var-ious techniques for frequency from 4 to 80 GHz at zero gateand drain bias. Both results presented in Fig. 8(c) and (d) showthat the difference between the de-embedded NFmin by the pro-posed technique and [3] and [4] increases consistently along thefrequency axis as the impact of metal finger parasitic becomessignificant at millimeter-wave frequencies. It exhibits the largestimpact on the transistor with smaller size (Width m,Length m), as clearly shown by the 4-dB margin inbetween the de-embedded NFmin by the proposed techniqueand [3] and [4] at 80 GHz. Similar to the results presented inFig. 6(a)–(f), noise de-embedding performance of both the pro-posed technique and [5] are highly correlated with each other forthe same OPEN and SHORT structures used. The performanceof the five-step de-embedding technique would be worse than
predicted if it is based on the original proposed structures in [5](nonshielded based), which can de-embed t he fixture parasiticfor up to the Metal 2 level only.
C. Validation of Metal Finger Parasitic Effects
In order to verify the accuracy of the de-embedding tech-niques, the total zero bias V gate ca-pacitance of the 0.13- m nMOS device is extracted ata sufficiently low frequency (2 GHz) such that it could be ap-proximated by [18]. Note that the intrinsic com-ponents of the nMOS device are negligible since it is turned off[18]. The extracted gate capacitance after de-embedding is thencompared with the reference value that is calculated based onprocess parameters of the 0.13- m CMOS technology. The re-sults in Fig. 9(a) clearly show that the extracted gate capaci-tance using the proposed technique and [5] are closely matchedwith the reference value. It varies proportionally with the devicesize as indicated ( of Device #1 of Device#2). This confirms that the proposed technique could correctlyde-embed the test fixture parasitic up to the metal fingers. Mean-while, extracted gate capacitance of Device #1 by [3] and [4] is
486 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
about five times higher than actual value as the parasitic capac-itance between metal fingers is included in the result.
D. Variability of Bond Pad Parasitic Elements
Variability between bond pad parasitic elements of andis also investigated and its impact on the noise de-em-
bedding result is discussed. In order to produce stable and con-sistent results, the skating distances of probes are maintainedaround 50 to 60 m [16]. Fig. 9(b) and (c) shows the extractedbond pad parasitic components of the test fixture, which includeprobe to pad contact impedances and pad to groundadmittances ). Note that the impedance value ofhas a magnitude of approximately 40% higher than on av-erage for frequency range from 4 to 80 GHz. This is mainly dueto the discrepancy in surface profiles of probes, which resultedin a different contact area between the probe and bond pad [11].In contrast, the difference between pad to ground admittances
is negligible even at 80 GHz. Variations betweenbond parasitic elements at the input and output ports resultedin increasing separation between NF50 of bond pad parasiticnetworks, and along the frequency domain [seeFig. 9(d)]. Failure to account for such variation by [4] would in-duce 3.9% to 6% error (at 80 GHz) in the de-embedded NFminof the transistor devices highlighted in Fig. 9(d). In other words,more accurate prediction of the bond pad parasitic by the pro-posed technique has led to better noise de-embedding perfor-mance than other reported work [3]–[8].
IV. CONCLUSION
In this paper, an accurate and simple noise de-embeddingmethodology has been proposed for high-frequency noise char-acterization of transistor devices. It is developed based on ageneralized two-port fixture model in conjunction with a setof shielded-based test structures, which enable accurate de-em-bedding of the test fixture parasitic for up to metal fingers. Theproposed noise de-embedding technique has been validated on0.13- m technology based CMOS transistors for up to 80 GHz.It shows superior performance to techniques [3] and [4] at highfrequencies as the parasitic effects of metal fingers dominate.Compared to technique [5], which has similar de-embedding ca-pability (for up to metal fingers), the proposed technique con-sumes less silicon area, is simpler, and has been proven to bemore accurate in high-frequency characterization of the activeCMOS device. Further, better prediction of the bond pad par-asitic gives additional boost to the noise de-embedding perfor-mance of the proposed technique as compared to other reportedwork [3]–[8]. These advantages confirmed that the proposedde-embedding technique is suitable for noise characterization ofCMOS devices at millimeter-wave frequencies. Moreover, theproposed technique can also be applied to other types of activedevices, which include III–V compound transistors.
ACKNOWLEDGMENT
The authors are grateful to GLOBALFOUNDRIES Singa-pore Pte Ltd., Singapore, for fabricating the test structures.
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Xi Sung Loo was born in Kuala Lumpur, Malaysia,in 1982. He received the B.E. (Hons.) degree in elec-trical and electronic engineering from Nanyang Tech-nological University, Singapore, in 2007, and is cur-rently working toward the Ph.D. degree at NanyangTechnological University.
His research interests mainly focus on design,layout optimization, and high-frequency noisecharacterization of RF CMOS devices for modelingpurposes.
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Kiat Seng Yeo (SM’09) received the B.E. (Hons.)degree in electronics and Ph.D. degree in electricalengineering from Nanyang Technological University,Singapore, in 1993 and 1996, respectively.
In 1996, he joined the School of Electrical andElectronic Engineering, Nanyang TechnologicalUniversity, as a Lecturer, and became an Asso-ciate Professor and Professor in 2002 and 2009,respectively. He became Sub-Dean (Student Affairs)in 2001, Head of the Department of Circuits andSystems in 2005, and Interim Director, VIRTUS,
Integrated Circuit (IC) Design Centre of Excellence in 2009. He providesconsultancy services to statutory boards and multinational corporations in theareas of semiconductor devices and electronic circuit design. He has beenextensively involved in the modeling and fabrication of small MOS/bipolarintegrated technologies for the last 17 years. His current research interestsinclude the design of new circuits and systems (based on scaled technologies)for low-voltage low-power applications, RFIC design, integrated circuit designof BiCMOS/CMOS multiple-valued logic circuits, domino logic and memories,and device characterization of deep-submicrometer MOSFETs.
Kok Wai J. Chew (M’02) received the B.E.(Hons.) degree in electrical engineering and M.Eng.and Ph.D. degrees in electrical engineering fromNanyang Technological University, Singapore, in1996, 1999, and 2007, respectively.
In 1998, he joined Chartered SemiconductorManufacturing, Singapore, as an Engineer with theMixed-Signal/RF CMOS Technology DevelopmentGroup, where he was involved in mixed-signalprocess characterization and integration, RF CMOSdevice layout, and characterization. In 2002, he
became a Senior Engineer and joined the SPICE Modeling Group, where he iscurrently responsible for RF CMOS and SiGe BiCMOS actives and passivestest-chip design, characterization, modeling, and customer support across alltechnologies. He is a Member of Technical Staff and Group Leader for RFCMOS characterization and modeling. He has authored or coauthored over15 papers in leading technical journals and conferences worldwide. He holds18 U.S. patents. His research interests include characterization and modelingof RF MOS/bipolar transistors, RF passives, and noise characterization andmodeling of MOS transistors.
Lye Hock Kelvin Chan was born in Penang,Malaysia, in 1983. He received the B.E. (Hons.)degree in electrical and electronic engineering fromNanyang Technological University, Singapore, in2007, and is currently working toward the Ph.D.degree at Nanyang Technological University.
His research interests mainly focus on design andhigh-frequency noise modeling of RF CMOS devicefor low-power applications.
Shih Ni Ong was born in Johor, Malaysia, in 1983.She received the B.E. (Hons.) degree in electrical andelectronic engineering from Nanyang TechnologicalUniversity, Singapore, in 2007, and is currentlyworking toward the Ph.D. degree at Nanyang Tech-nological University.
Her research interests mainly focus on high-fre-quency noise characterization and modeling of RFCMOS device for IC design purposes.
Manh Anh Do (SM’05) received the B.Sc degreein physics from the University of Saigon, Saigon,Vietnam, in 1969, and the B.E. (Hons.) degree inelectronics and Ph.D. degree in electrical enigneeringfrom the University of Canterbury, Canterbury, NewZealand, in 1973 and 1977, respectively.
From 1977 to 1989, he held various positions in-cluding: Design Engineer, Production Manager, andResearch Scientist in New Zealand, and Senior Lec-turer with National University of Singapore. In 1989,he joined the School of Electrical and Electronic En-
gineering, Nanyang Technological University (NTU), Singapore, initially as aSenior Lecturer, then an Associate Professor in 1996, and then Professor in2001. He has been a consultant for many projects in the electronic industry, andwas a key consultant for the implementation of the $200 million Electronic RoadPricing (ERP) Project in Singapore from 1990 to 2001. From 1995 to 2005, hewas Head of the Division of Circuits and Systems, NTU. He is currently the Di-rector of the Centre for Integrated Circuits and Systems, NTU. He has authoredor coauthored over 100 papers in leading journals and 135 papers internationalconferences in the areas of electronic circuits and systems. His current researchis focused on mobile communications, RF IC design, mixed-signal circuits andintelligent transport systems. Prior to that, he specialized in sonar designing andbiomedical signal processing.
Dr. Do is a Fellow of the Institution of Engineering and Technology (IET),U.K. He is a Chartered Engineer. He was a council member of the IET (from2001 to 2004). He was an associate editor for the IEEE TRANSACTIONS ON
MICROWAVE THEORY AND TECHNIQUES (2005, 2006).
Chirn Chye Boon received the B.E. degree (Hons.)in electronics and Ph.D. degree in electrical engi-neering from Nanyang Technological University(NTU), Singapore, in 2000 and 2004, respectively.
In 2005, he joined NTU, as a Research Fellow andbecame an Assistant Professor that same year. Priorto that, he was with Advanced RFIC, where he was aSenior Engineer. He specializes in direct conversionRF transceiver front-end design, phase-locked-loopfrequency synthesizers, clock and data recovery cir-cuits, and frequency dividers.
Dr. Boon is a reviewer for the IEEE TRANSACTIONS OF CIRCUITS AND
SYSTEMS—PART I: REGULAR PAPERS, the IEEE MICROWAVE AND WIRELESS
COMPONENTS LETTERS, and the IEEE TRANSACTIONS ON MICROWAVE THEORY
