IGBT Open-Circuit Fault Diagnosis in a Quasi-Z-Source...

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Abstract—In this paper, a fast and practical method is proposed for open-circuit (OC) fault diagnosis (FD) in a three-phase quasi-Z-source inverter (q-ZSI). Compared to the existing fast OC FD techniques in three-phase voltage-source inverters (VSIs), this method is more cost-effective since no ultra-fast processor or high-speed measurement is required. Additionally, the method is independent of the load condition. The proposed method is only applicable to Z-source family inverters and is based on observing the effect of shoot-through (SH) intervals on the system variables during switching periods. The proposed algorithm includes two consecutive stages: OC detection and fault location identification. When both stages of the OC FD algorithm are done, a redundant leg is activated and utilized instead of the failed leg. The accuracy of the proposed method is confirmed by the experimental results from a low-voltage q-ZSI prototype.

Index Terms— Quasi-Z-Source Inverter, Open-Circuit

Fault, Fault Diagnosis Algorithm.

I. INTRODUCTION

O ensure service continuity and increase the reliability of a

distributed generation (DG) power system, fault-tolerant

(FT) structures have been considered widely in recent literature

[1]-[4]. A DG power system includes many parts such as the

storage device, the processor unit, the sensors, the input source

and the power electronics converter. A failure could occur in

any of these parts. According to the study in [5], semiconductor

and soldering faults cause approximately 34% of power device

failures. However, it is estimated that at least 80% of faults in

the converter part are due to semiconductor failures [6].

Power switch faults which are typically caused by high

thermal or electrical stress are categorized into two main

groups: short-circuit (SC) and open-circuit (OC) faults [7]-[8].

An OC fault (OCF) in a power converter could occur through a

switch failure or a driver breakdown. Gate driver breakdown is

the main cause of converter failure (53% of the converter faults)

and results in permanent IGBT OC [7].

Unlike an SC fault, which usually triggers the SC protection

of the system, an OCF can remain undetected for a long time,

degrading the power quality in the power system. Problems

such as abnormal stress on circuit elements can occur after

OCF, causing further damage to the system [7]. As OC faults

are prevalent in power device failures, OC FD is a basic step for

increasing the reliability of a power system. In non-FT systems,

using OC FD techniques prevents extra system damages. In FT

systems, it also results in continuous operation after an OC

fault. Speed, cost, reliability, and independence of the load

condition are the main factors for evaluating an OC FD method. The approaches for OC FD are either current-based or voltage-

based [9]-[10] and each type has different strategies. Current-

based methods have been considered widely in the literature

[11]-[16]. In [10], a thorough review of these methods is

presented. In most of these methods, the measured three-phase

currents are mathematically analyzed to recognize OCF.

Usually, no extra hardware is required in current-based

methods, making them cost-effective. Low speed, high

complexity, limitation for multiple faults detection and

malfunction in small loads are the drawbacks of these

approaches [17]. In Table I, some common OC FD methods are

compared. Park’s vector approach presented in [18] (with

specification as shown in Table I), is a well-known FD method.

The main drawback is that the detection algorithm is too

complex to fit in a processor designed for power electronics

application. The normalized DC current method in [19] is based

on Park’s vector approach which is not load-dependent (unlike

Park’s vector method). This method is not efficient when

closed-loop control is implemented. In the modified normalized

DC current method, this problem is nearly solved [19]. The

slope calculated from 𝑖𝑑 and 𝑖𝑞 samples (the current

components of Park’s vector), is used for FD in the slope

method [20], in which FD is load-dependent and rather slow. In

the AC current instantaneous frequency method, OCF is

detected from the calculation of the current space vector

frequency [20]. The location of the OCF is not recognized by

this FD procedure. In [21] another cost-effective and relatively

fast current-based alternative is proposed which is also robust

to load variation. In this method, the difference between the

reference and the output current is calculated. But this approach

cannot be used in a system with an open-loop control. A similar

technique, using the system mathematical model is proposed in

[22] for motor drive application. However, its implementation

is rather complex and demands high mathematical calculations.

In addition, extra measurement (phase voltage sensing) is

needed for the FD procedure. Another model-based method is

presented in [23]. Although it is cost-effective as no extra

hardware is required, the accuracy of the FD is strongly

dependent on the pre-assumed values for the system

parameters. In practice, the method is inefficient.

IGBT Open-Circuit Fault Diagnosis in a Quasi-Z-Source Inverter

Mokhtar Yaghoubi, Javad S.Moghani, Negar Noroozi, Student Member, IEEE, Mohammad Reza Zolghadri, Senior Member, IEEE

T

Manuscript received Dec 13, 2017; revised Jan 25, 2018 and Apr 02,

2018; accepted May 29, 2018. Mokhtar Yaghoubi and Javad S.Moghani are with the Department of

Electrical Engineering of Amirkabir University of Technology, Tehran, Iran (e-mail: [email protected], [email protected]).

Negar Noroozi and Mohammad Reza Zolghadri are with the Department of Electrical engineering of Sharif University of Technology, Tehran, Iran (e-mail: [email protected], [email protected]).


In Table I, the specification of some voltage-based FD

methods are also depicted. In “actual and reference quantity

comparison” the fault is recognized by comparing the reference

and the measured phase voltage values [24]. The method is

much faster than current-based methods, but it has a costly

implementation. Sensing the lower switch voltage is another

fast voltage-based FD strategy [8]. It uses op-amp/flip-flop

auxiliary circuits for FD, increasing the complexity of the

system. In [7], an OC FD is proposed based on three-phase

current, phase voltage, and DC link voltage measurements. The

method is fast but the many variables involved in FD could

make the method sensitive to noise. An ultra-fast FPGA-based

approach is proposed in [25]. It is not possible to implement this

technique in a usual DSP/microcontroller processor used in

power electronics applications. The need for high-bandwidth

voltage measurement is another drawback of this method,

leading to a cost increase. In addition, the assumption on delays

in the response time of the circuit elements is required. This

may affect the accuracy of the FD in practice. In [26] another

voltage-based method is proposed. It is based on the

comparison of the lower switch voltage and the added

photocoupler output. This approach is low-cost and fast, but it

is dependent on the characteristics of the devices which can

change by thermal conditions or by aging.

In summary, in comparison to current-based FD methods,

voltage-based methods are much faster and have higher

immunity to false alarms. However, voltage-based methods

usually require additional measurement and extra hardware

leading to higher cost and complexity [24]-[26].

The three-phase q-ZSI shown in Fig. 1, is a beneficial

structure for DG especially in photovoltaic (PV) applications

[27]-[29]. In addition to the single-stage buck-boost

characteristic, q-ZSI can absorb constant power from the input

source. Compared to the traditional Z-source inverter (ZSI) the

voltage on capacitor 𝐶2 (Fig. 1) is much less than that on 𝐶1

[30], leading to reduced passive component rating and lower

manufacturing cost. In [31], modeling and controller design of

q-ZSI is discussed. In [31]-[33], q-ZSI with battery storage for

hybrid PV application is presented.

To have a reliable PV power system, applying FT strategies

to q-ZSI has some advantages compared to the traditional

double-stage PV converters. As mentioned, a significant

portion of semiconductor failures is due to switch OC faults [7].

To cover OC faults at both AC and DC sides of a double-stage

PV converter, two separate FT strategies (for AC and DC

stages) are required. FT topologies for DC/DC stage in PV

systems are presented in [34]-[35]. Due to a single-stage

structure and fewer semiconductor elements in q-ZSI,

implementing FT strategies in q-ZSI has lower cost and higher

reliability.

FD is the main step in FT systems. In this paper, a novel

voltage-based OC FD technique is proposed for three-phase q-

ZSI. The proposed method is much faster than most of the

approaches shown in Table I. This method is able to recognize

OC faults in just a few switching cycles. Despite the fast FD

method in [25], no high-speed processor or ultra-fast

measurement is required. In comparison to the existing

techniques, the proposed method has a simpler implementation.

In addition, the CPU of the processor is not involved in the FD

procedure during normal work conditions. To implement the

proposed method, only a low-cost auxiliary circuit (including a

comparator and a resistive divider) is added to the system.

Therefore, the cost of the system does not change significantly

(unlike most voltage-based approaches [8], [24]-[26]). In

addition, this method is independent of the load condition since

C2

load

L2

C1

cba

SaH

SaL

SbH

SbL

ScH

ScL

DL1

+

_

+_

+

_

VC1

VC2

iL1 iL2

vleg

+

_

Lf Lf Lf

ia ib ic

Z Z Z

Vin

Fig. 1. Three-phase q-ZSI main topology.

TABLE I THE COMPARISON OF OC FD METHODS IN THREE-PHASE INVERTERS.

Method FD Time

(msec)

Load

Dependency

Implementation

complexity Required variables

Extra

Cost

Park’s Vector Method [18] 20 High Medium 3-phase currents No

Normalized DC Current Method [19] 18.4 High Low 3-phase currents No

Modified Normalized DC Current Method [19] 18.4 Low Low 3-phase currents No

Slope Method [20] 38.3 High Low 3-phase currents No

AC Current Instantaneous Frequency Method [20] 20 Medium Low 3-phase currents No

The Reference Current Errors Method [21] 13 Low Low 3-phase currents No

Observer-Based Method [22] 19 Low Medium 3-phase currents/voltages Medium

Actual and Reference Quantity Comparison [24] 5 Low High phase, neutral and pole voltages High

Lower Switches Voltage Observation [8] 2.7 Low Medium lower switches voltage High

Instant Voltage Error [7] 2.5 Low Medium 3-phase currents /voltages Low

Real-Time FPGA-Based [25] 0.01 Low High pole voltages/device delays High

Switching Function Model-Based [26] 0.01-10 Low Medium lower switches voltage Medium


it is voltage-based. The FD procedure is based on observing the

SH intervals effect on the voltage across the legs (𝑣𝑙𝑒𝑔 in Fig.

1). Therefore, it is not applicable in the traditional VSIs. In the

proposed FD algorithm, the detection of OCF and identifying

the failed leg are implemented in two consecutive stages. In the

first stage, the algorithm confirms an OCF. Then the algorithm

starts to save the data from the system for a few switching

cycles. Finally, by analyzing the data, the failed leg is

recognized. In [35], using “redundant leg” is described as an

optimized and cost-effective solution for three-phase FT

inverters. After identifying the failed leg by the proposed

algorithm, a redundant leg is replaced with the failed leg.

In section II of this paper, the main structure of the three-

phase q-ZSI is reviewed. In section III, OC fault effect on q-ZSI

is analyzed. The OC FD algorithm is presented in section IV.

To verify the proper operation of the proposed algorithm, the

experimental results for a low-voltage prototype are presented

in section V. Finally, the conclusion of this paper is presented

in section VI.

II. AN INTRODUCTION TO QUASI-Z-SOURCE INVERTER

q-ZSI shown in Fig.1 has two operating modes [36]:

1) Inverter Mode: In this mode, q-ZSI operates similarly to a

classic voltage source inverter (VSI). In this mode, the

continuous input current flows through the input side diode (𝐷

in Fig. 1).

2) Shoot-through Mode: During this mode, the inverter

becomes short-circuit intentionally through any phase legs. The

network diode is turned off via the reverse-bias voltage.

𝑣𝑙𝑒𝑔 (depicted in Fig. 1), denotes the voltage across the leg

terminals. In Fig. 2, the typical waveform of 𝑣𝑙𝑒𝑔 is shown.

During SH mode, 𝑣𝑙𝑒𝑔 is zero, while during non-SH mode, 𝑣𝑙𝑒𝑔

is equal to the sum of the voltages across the input capacitors:

𝑣𝑙𝑒𝑔 = {0 𝑆𝐻 𝑚𝑜𝑑𝑒𝑣𝐶1 + 𝑣𝐶2 𝑛𝑜𝑛 𝑆𝐻 𝑚𝑜𝑑𝑒

(1)

𝑣𝐶1 and 𝑣𝐶2 are the voltages across 𝐶1 and 𝐶2 shown in Fig. 1.

As a control strategy in q-ZSI, the peak value of the leg

terminals voltage (𝑣𝑐1 + 𝑣𝑐2 ) is regulated through SH duration

adjustment, where:

𝑣𝐶1 + 𝑣𝐶2 ≈ VB = 𝑉𝑖𝑛 × 𝐵 (2)

𝐵 =1

1−2𝐷𝑠ℎ (3)

B in (2)-(3) denotes the “boost factor” of the q-ZSI and 𝐷𝑠ℎ is

the relative SH state duration in a switching period. 𝑉𝐵 denotes

the peak value of the 𝑣𝑙𝑒𝑔. When the source voltage is dropped,

𝐷𝑠ℎ is increased and the leg terminals peak voltage is kept

nearly constant [36].

For the scalar implementation of SVM vectors in a q-ZSI, SH

duration is divided into six separate intervals which are located

between the main SVM vectors [37]. In Fig. 3, the arrangement

of SH and the main SVM states are shown for 𝐴1 sector. In Fig.

4, SVM sectors in αβ plane are depicted [37]. 𝑇𝑎 and 𝑇𝑏 in Fig.

3 are the durations of the first and the second active vectors of

SVM method respectively. 𝑇𝑠ℎ is SH state length; 𝑇0 and 𝑇7

denote the duration of zero state in which the three lower and

the three upper switches are turned on. The calculation of the

compare signals values in q-ZSI (shown by 𝑇𝑚𝑖𝑛±, 𝑇𝑚𝑎𝑥± and

𝑇𝑚𝑖𝑑± in Fig. 3) is presented in [37]. The filled rectangles in Fig.

3 represent SH states; where 𝑆𝐻𝑖 (𝑖 = 𝑎, 𝑏, 𝑐) identifies the

short-circuit leg in each SH state. As it is seen, during each SH

state only one leg becomes short-circuit. For example, the first

SH in Fig. 3 is through leg “a”. The switching states are

symmetric to the center of the switching period.

III. OPEN-CIRCUIT ANALYSIS IN QUASI-Z-SOURCE

INVERTER

In the most probable OC fault case [7], IGBT is only affected

and its antiparallel diode is sound. This fault is also called

“open-gate fault”. In this case, only one polarity of the output

current is conducted by the freewheeling diode or the sound

switch of the leg. In Fig. 5(a), the output currents of the inverter

are shown when the upper switch of leg “a” (𝑆𝑎𝐻 in Fig. 1) is

OC.

SH interval

VB

non-SH

interval

non-SH

interval

vleg

SH interval

t

Fig. 2. The typical waveform across the leg terminals voltage.

Timer counter/PRD

SaLSaH

SbLSbH

ScLScH

0.5Tsw

0.5Tmax+

0.5Tmid-0.5Tmid+

0.5Tmin-0.5Tmin+

0.5Tmax-

T0/2 Ta/2 Tb/2 Tb/2 Ta/2 T0/2T7

000 100 110 111 100 000110

t

vleg / VB

1

TSW

SHa SHb SHc SHc SHb SHa

TSH /6 TSH /6 TSH /6 TSH /6 TSH /6 TSH /6

t

t

states:

Fig. 3. Scalar implementation of SVM method in q-ZSI [37].

A1

A2

A3

A4

A5

A6

V1 (100)

V2 (110)V3 (010)

V4 (011)

V5 (001) V6 (101)

θ=ωm t

Fig. 4. SVM vectors and phase regions [37].


It is also possible that the total leg becomes OC. This fault

may happen by the intervention of the protection system [6]. In

Fig. 5(b), the output currents are shown for the case that both

switches of leg “a” are OC.

After an OCF in a switch, low-frequency harmonics appear

in the harmonic content of the qZSI state variables (𝑣𝐶1, 𝑣C2,

𝑖𝐿1, and 𝑖𝐿2) as well as the output power. The leg voltage peak

value is dropped as the SH state is not implemented by the

faulty leg (the boost factor is decreased in practice). For the

simulated q-ZSI, the normalized value of “𝑣𝐶1 + 𝑣𝐶2” is shown

in Fig. 6(a)-(b) in the case of OC in a switch and a leg

respectively. In both cases, the peak value of the leg terminals

is dropped. 𝑣𝑙𝑒𝑔 during OCF in a switch is shown in Fig. 7. As

shown in Fig. 3 and Fig. 7, in normal work condition, six SH

intervals are visible on 𝑣𝑙𝑒𝑔 during each switching period.

During OCF (in both leg and switch cases), the number of SH

intervals recognizable from 𝑣𝑙𝑒𝑔 is decreased to four.

IV. OPEN-CIRCUIT FAULT DIAGNOSIS IN QUASI-Z-SOURCE

INVERTER

As it is mentioned, all SH states appear as zero-value

intervals on 𝑣𝑙𝑒𝑔. In this paper, “NFE” is defined as the number

of falling edges (FE) in 𝑣𝑙𝑒𝑔 waveform during half of the

switching period. It can be said that when all SH states are

implemented properly, NFE is three. During OCF, NFE is

reduced to two since the SH state is not implemented by one

leg.

Assuming normal work condition in an ideal q-ZSI, 𝑡𝐹𝐸𝑖 (𝑖 =1,2,3) is defined as the falling edge (FE) time at the beginning

of its SH state in a switching cycle (shown in Fig. 8). 𝑡𝐹𝐸𝑖 values

are calculated as:

{

𝑡𝐹𝐸1 = 0.25(𝑇𝑆𝑤 − 𝑇𝑎 − 𝑇𝑏 − 𝑇𝑠ℎ)𝑡𝐹𝐸2 = 𝑡𝐹𝐸1 + 𝑇𝑠ℎ/6 + 0.5𝑇𝑎 𝑡𝐹𝐸3 = 0.5𝑇𝑠𝑤 − 𝑡𝐹𝐸1 − 𝑇𝑠ℎ/6

(4)

{

𝑇𝑎/𝑇𝑠𝑤 = 𝑀𝑐 sin (𝑛

𝜋

3− 𝜃)

𝑇𝑏/𝑇𝑠𝑤 = 𝑀𝑐sin (𝜃 − (𝑛 − 1)𝜋

3)

𝑀𝑐 = √3𝑉𝑟𝑒𝑓/𝑉𝐵

(5)

In (5), 𝑉𝑟𝑒𝑓 and 𝜃 are the reference vector amplitude and angle

in 𝛼𝛽 plane; “𝑛” is the sector number.

Each FE in Fig. 8 (FE1, FE2, and FE3) is implemented

through a separate leg. Table II shows the short-circuit leg for

each FE moment along SVM sectors. For example, the second

FE (FE2) during the third sector (𝐴3) is implemented through

leg “c”.

In practice, FE moments in 𝑣𝑙𝑒𝑔 occur with a little delay

comparing to 𝑡𝐹𝐸𝑖 values in (4), mainly because of the IGBTs

turning-off delay.

(a)

(b)

Fig. 5. The output currents during OCF in three-phase q-ZSI. (a)

open-gate fault in 𝑆𝑎𝐻; (b) OC in both switches of leg “a” (𝑆𝑎𝐻 and 𝑆𝑎𝐿).

0.1 0.15-15

-10

-5

0

5

10

15

t (sec)

i a, i b

, i

c (A

)

ia

0.1 0.15-15

-10

-5

0

5

10

15

t(sec)

i a, i b

, i c (

A)

ia

(a)

(b)

Fig. 6. The leg voltage peak value (normalized by 𝑉𝐵) (a) open-gate fault in 𝑆𝑎𝐻; (b) OC in both switches of leg “a” (𝑆𝑎𝐻 and 𝑆𝑎𝐿).

0.08 0.1 0.12 0.14 0.16 0.18 0.20.8

0.9

1

1.1

1.2

t (sec)

(vC

1+

vC

2 )

/ V

B OCF

0.08 0.1 0.12 0.14 0.16 0.18 0.20.8

0.9

1

1.1

1.2

t (sec)

(vC

1+

vC

2 )

/ V

B OCF

Fig. 7. The leg voltage (normalized by 𝑉𝐵) during open-gate fault in 𝑆𝑎𝐻.


A. Falling edges Detection

Most of the microcontrollers and DSPs designed for power

electronics applications have a “capture” unit used for motor

speed or duty cycle measurement. For example,

TMS320x28xxx family from Texas Instrument processors and

even lower speed processors like dsPIC30F4011 from

Microchip contain this unit. The capture unit includes a high-

bandwidth rising/falling-edge detector. When the edge detector

is triggered, the DSP timer value can be saved to a capture

register. Multiple edges timing could also be retrieved from

capture registers. TMS320F2808 used in this paper includes

four capture registers (CAP1... CAP4). By each trigger, the

timer register can be saved sequentially in these registers.

To detect FE moments, 𝑣𝑙𝑒𝑔 should be digitized first. A

simple circuitry shown in Fig. 9 (a) is proposed for this purpose.

The leg voltage is scaled down by a resistive divider and is

compared to a constant voltage (𝑉𝑐) by a digital comparator. The

gain of the resistor divider is designed as:

𝐾𝑟𝑑 =3

𝑉𝐵 (6)

Considering (6), the peak value of 𝑣𝑙𝑒𝑔 (≈ 𝑉𝐵) is scaled down

to 3𝑉 at the comparator input. 𝑉𝑐 is set at 1.5𝑉, covering nearly

half of the IGBT delay during digitalizing 𝑣𝑙𝑒𝑔 . The digital

output from the comparator (𝑣𝑐𝑎𝑝) is transferred to the capture

unit. The detected FE moments, 𝑡𝑐𝑎𝑝𝑗 (𝑗 = 1,2,3 in normal

condition and 𝑗 = 1,2 during OCF) are saved to the capture

registers (CAPj) as shown in Fig. 10. As mentioned, in practice,

the detected FE moments (𝑡𝑐𝑎𝑝𝑗) are not exactly equal to the

calculated times (𝑡𝐹𝐸𝑖) because of system delays. A delay

margin (𝑡𝑑) is considered for each 𝑡𝑐𝑎𝑝𝑗 value to be considered

as a correct FE detection. 𝑡𝑑 is selected due to the IGBTs typical

turning-off time (𝑡𝑜𝑓𝑓). In this paper, 𝑡𝑑 is considered 2𝜇𝑠𝑒𝑐

which is 2.5 times larger than 𝑡𝑜𝑓𝑓 in the used IGBTs. If the

difference between 𝑡𝑐𝑎𝑝𝑗 and 𝑡𝐹𝐸𝑖 is less than 2𝜇𝑠𝑒𝑐, 𝐹𝐸𝑖

detection is confirmed. In Fig. 10, the filled rectangles shows

the permitted delay margin.

B. Open-Circuit Fault Diagnosis Algorithm

The OC FD algorithm proposed in this paper is based on

examining 𝑣𝑙𝑒𝑔 and its zero-value intervals; the missed zero–

value interval in 𝑣𝑙𝑒𝑔 identifies the OC leg. Comparing to OC

VbVaV0 / V7states: t

vleg / VB

tFE1 tFE2 tFE3 0.5 Tsw

FE1 FE2 FE3

t

V7 / V0

0

SH SH SH

Fig. 8. FE times (𝑡𝐹𝐸𝑖) in 𝑣𝑙𝑒𝑔; there are three falling edge moments

during normal work condition.

TABLE II THE SHORT-CIRCUIT LEGS IN DIFFERENT SECTORS DURING HALF PERIOD.

𝑨𝟏 𝑨𝟐 𝑨𝟑 𝑨𝟒 𝑨𝟓 𝑨𝟔

FE1 a c b a c b

FE2 b a c b a c

FE3 c b a c b a

+

_

+_Vc

capture unit

DSP boardresistive divider

Comparator

vleg

vcap

0v

5vkrd .vleg CAP1CAP2CAP3

Fig. 9. The capture unit interface, including the resistive divider and the comparator.

tCAP3

t

DSP timer

vcap

tCAP1

t

vleg

CAP2CAP3

td td td

tCAP2tCAP1

tFE3tFE1 tFE2

Fig. 10. The timer values sent to capture registers (through to

detection of falling edges in 𝑣𝑙𝑒𝑔).

Set PF. NFE, tFEi and tCAPj are

saved for the next 5 cycles.

Start

NFE is saved

NFE is less than 3

for three sequential

cycles ?

no

Set DF (OCF is announced)

tei,j values are calculated

End

More than two

cycles confirm OC? no

yes

yes

first stage

(OCF detection)

The missed FE is identified.

The failed leg is identified

using Table II.

second stage

(identifying the failed leg)

Fig. 11. The proposed OC FD algorithm.


FD algorithms in traditional VSIs, this method has the

advantages of being both fast and cost-effective. With this

method, it is possible to detect OCF in a few switching cycles

without the need to use an ultra-fast processor or high-speed

measurement. In addition, the OC FD is independent of the load

condition.

In the proposed OC FD algorithm, OCF detection and the

failed leg identification are implemented in two consecutive

stages. In the first stage, the algorithm confirms an OCF. Then,

the CPU starts handling the saved data to identify the failed leg.

The NFE is checked for each switching cycle and if it is less

than three for a few cycles, an OCF status is announced by the

algorithm. To avoid the effect of noise and disturbance, two

binary variables are defined for the first stage of the algorithm

showing the status of “probable fault” and “definite fault” (PF

and DF respectively). By repeating fault detection in three

sequential cycles, PF is set. Then, the NFE is checked for the

next five cycles and 𝑡𝐶𝐴𝑃𝑗 and 𝑡𝐹𝐸𝑖 values are saved separately.

If the OCF condition is confirmed again (at least in three of the

five cycles), DF is set. In fact, the OCF status is announced by

setting DF. Then the second stage of the algorithm is started. In

Fig. 11 the proposed OC FD algorithm is depicted. The number

of cycles for setting DF and PF is selected based on the required

speed for FD and the reliability of the algorithm. Increasing the

number of investigated cycles results in decreasing the

misdetections and also the speed.

As mentioned, 𝑡𝐹𝐸1, 𝑡𝐹𝐸2, and 𝑡𝐹𝐸3 are calculated due to (4)-

(5). During OCF only 𝑡𝐶𝐴𝑃1 and 𝑡𝐶𝐴𝑃2 are retrieved from CAP1

and CAP2 registers. In the second stage of OC FD algorithm,

the difference between 𝑡𝐹𝐸𝑖 and 𝑡𝐶𝐴𝑃𝑗 is calculated as:

{

𝑡𝑒1,1 = |𝑡𝐶𝐴𝑃1− 𝑡𝐹𝐸1|

𝑡𝑒2,1 = |𝑡𝐶𝐴𝑃1 − 𝑡𝐹𝐸2|



(7)

Using Table III and 𝑡𝑒𝑖𝑗 values, the missed FE is identified and

using Table II, the failed leg is recognized.

After FD, the failed leg is disabled and a redundant leg is

added to the inverter circuit through a TRIAC switch as shown

in Fig. 12. The proposed algorithm can detect the failed leg

(which could have one or two failed switches), but it is not able

to determine the exact location of the failed switch. Meaning

that by this algorithm it is not possible to recognize that the

upper, lower or both switches of the leg are failed. Since

replacing the total leg (instead of the failed switch) is introduced

as an optimized FT strategy for three-phase inverters [35], this

strategy is used in this paper. Therefore, the determination of

the failed switch location is not necessary when the total leg is

replaced with another one.

V. THE EXPERIMENTAL RESULTS

A low-voltage q-ZSI prototype shown in Fig. 13 is

implemented. The switching and line frequencies are 20𝑘𝐻𝑧

and 50𝐻𝑧 respectively. The output voltage is 110𝑉 and 𝑉𝐵 is

380𝑉. The maximum value of 𝐷𝑠ℎ and the minimum value of

the input voltage in the prototype are 0.24 and 200V

respectively. A 600V/15A power module (FSBS15CH60) is

used in this prototype. Through adjusting SH state duration, the

leg voltage peak value (𝑣𝐶1 + 𝑣𝑐2) is kept nearly constant (≈𝑉𝐵 = 380𝑉) when the input voltage varies. The PV input source

is modeled with a DC supply voltage. The prototype provides

1.2𝑘𝑊 on the AC side. The digital signal processor,

TMS320F2808, provides PWM and the protection commands.

The capture unit interface includes a resistive divider, a zener

diode (as a voltage limiter) and an inexpensive comparator

(LM311). Three TRIAC switches are connected to the middle

of the main legs and the redundant leg similar to Fig. 12.

As it is mentioned, 𝑣𝑙𝑒𝑔 has a pulsating form and its peak

value is equal to the sum of the voltages across 𝐶1 and 𝐶2. In

Fig. 14, 𝑣𝑙𝑒𝑔 is shown. During SH states, 𝑣𝑙𝑒𝑔 is nearly equal to

Vin

L1 L2

C1

ab

c

filter

&

load

C2

redundant leg

D

Fig. 12. The three-phase FT q-ZSI structure with a redundant leg.

Fig. 13. The designed three-phase q-ZSI prototype.

Fig. 14. The voltage across the leg terminals (𝑣𝑙𝑒𝑔); the SH states are

detectable by zero-value intervals; the peak value is nearly 380v.

TABLE III THE MISSED FE DETECTION FROM THE CALCULATED ERROR

condition the missed FE 𝑡𝑒1,1 > 𝑡𝑑 FE1

𝑡𝑒2,1 > 𝑡𝑑 & 𝑡𝑒2,2 > 𝑡𝑑 FE2

𝑡𝑒3,2 > 𝑡𝑑 FE3


zero.

In Fig. 15(a)-(c), the output currents of the q-ZSI in normal

conditions and during OCF in a switch/leg are shown. In Fig.

15 (a), the RMS value of the output current is equal to 3.5A per

phase. In Fig 15(b), the leg “a” only conducts the current with

negative polarity due to the OCF in 𝑆𝑎𝐻 . The output currents

during OC in both switches of a leg are shown in Fig. 15(c). 𝑆𝑎𝐻

and 𝑆𝑎𝐿 become OC simultaneously. After the fault, the current

of phase “a” is zero.

𝑣𝑙𝑒𝑔 and 𝑣𝑐𝑎𝑝 (the input of the capture unit) are measured and

shown in Fig. 16(a)-(c) for normal conditions and during OCF

in a switch/leg. Comparing Fig. 16(a) to Fig. 16(b)-(c) shows

that the number of SH states are reduced during OCF. The

disturbance originated from the OCF is visible on 𝑣𝑙𝑒𝑔 in Fig.

16(b)-(c). The peak value of 𝑣𝑐𝑎𝑝 is constant and equals 5𝑉. In

Fig. 17(a)-(b), 𝑣𝑙𝑒𝑔 peak value (𝑣𝑐1 + 𝑣𝑐2) is depicted during

OCF in a switch/leg. The voltage drop across the capacitors

during OCF is due to the reduction of the real SH duration. The

line-frequency harmonics are also seen after the OCF in Fig.

17(a)-(b).

In Fig. 18(a)-(b), DF and PF signals before and after OC fault

are depicted. The OC instant is highlighted with a dashed line

in Fig. 18(a)-(b). After three cycles from the OC instant, PF is

set. A few cycles later, DF is also set. Indeed, setting DF is the

declaration of definite OC fault by the algorithm. At this point

the algorithm enters the second stage. As an example, the data

(a)

(b)

(c)

Fig. 15. The output currents of implemented q-ZSI; (a) during normal

condition; (b) during OC in 𝑆𝑎𝐻; (c) during OC in 𝑆𝑎𝐻 and 𝑆𝑎𝐿.

(a)

(b)

(c)

Fig. 16. 𝑣𝑐𝑎𝑝 comparing to 𝑣𝑙𝑒𝑔 in the implemented q-ZSI; (a) during

normal condition; (b) during OC in 𝑆𝑎𝐻; (c) during OC in 𝑆𝑎𝐻 and 𝑆𝑎𝐿.

TABLE IV THE MISSED FE DETECTION FROM THE CALCULATED ERROR

CAP1 CAP2 [𝑡𝑒𝑖𝑗](usec) Sector

Cycle 1 2076 2781 [16.50, 0.85, 6.78, 0.97] 1

Cycle 2 2046 2786 [16.29, 0.85, 7.06, 0.96] 1

Cycle 3 2016 2793 [16.08, 0.84, 7.38, 0.98] 1

Cycle 4 1989 2780 [15.90, 0.87, 7.52, 0.84] 1

Cycle 5 1957 2795 [15.66, 0.85, 7.89, 0.92] 1


used at the second stage of FD algorithm in the OCF case in Fig. 18(a) are shown in Table IV. 𝑡𝑐𝑎𝑝𝑗 values are calculated

(a) (b) Fig. 17. The input capacitors voltage (𝑣𝐶1 + 𝑣𝐶2); (a) OCF in 𝑆𝑎𝐻 (b) OCF in both 𝑆𝑎𝐻 and 𝑆𝑎𝐿.

(a) (b)

Fig. 18. PF and DF signals after the OCF (a) OCF in 𝑆𝑎𝐻 (b) OCF in both 𝑆𝑎𝐻 and 𝑆𝑎𝐿.

(a) (b)

(c) (d)

Fig. 19. The output currents in FT q-ZSI; (a) OCF in 𝑆𝑎𝐻 and replacing the leg “a” in the nominal load; (b) OCF in 𝑆𝑎𝐻 and 𝑆𝑎𝐿 and replacing the

leg “a” in the nominal load; (c) OCF in 𝑆𝑎𝐻 and replacing the leg “a” in 30% of the nominal load; (d) OCF in 𝑆𝑎𝐻 and 𝑆𝑎𝐿 and replacing the leg “a” in 30% of the nominal load.


from 𝐶𝐴𝑃𝑗 registers as:

𝑡𝑐𝑎𝑝𝑗 =𝐶𝐴𝑃𝑗

2×𝑃𝑅𝐷𝑇𝑠𝑤 (8)

In (8), PRD is the period of the DSP timer. In Table IV, the

difference between the detected FE times and the calculated

values in (4) are approximately 1𝜇𝑠𝑒𝑐. Using Table IV and

Table III, it is concluded FE1 is not detected. Considering the

sector number and Table II, one or both of switches of the leg

“a” are failed.

After completing OC FD, the commands of the failed leg are

disabled. Then, the redundant leg is activated and added to the

inverter circuit through a TRIAC in the FT q-ZSI. In Fig. 19(a)-

(d), it is shown how OC is covered by the fault tolerant

operation (FTO). The moments of OCF and FTO (activating the

redundant leg in the inverter circuit) are determined by the

dashed lines in Fig. 19(a)-(d). In Fig. 19(a)-(b), the switch and

leg OC occur in the nominal load condition. In Fig 19(c)-(d) the

switch/leg OC occur in a light load where the output power is

reduced to 30% of the nominal value. In both cases, the OCF is

successfully recognized and the redundant leg is used instead of

the failed leg.

CONCLUSION

In this paper, a novel, fast and cost-effective OC FD

algorithm is presented for FT q-ZSI. The proposed method is

independent of the load condition and is based on observing the

SH state effect on the leg terminal voltage. No fast

measurement or high-speed processor is required and only a

low-cost comparator circuit is added to the system. The

proposed FD algorithm is only applicable to voltage fed ZSIs.

For higher reliability in a PV system, FT q-ZSI is considered

as a beneficial structure. FT q-ZSI has fewer semiconductor

elements and a lower probability of facing OCF compared to

FT double-stage PV converters. In addition, while in FT

double-stage PV converters, two separate FT strategies are

needed for each stage (DC/DC and inverter), the FT q-ZSI input

side has no switch component. This makes FT q-ZSI more

reliable and cost-effective. In this paper, the proposed FD

algorithm is applied to an FT q-ZSI with one redundant leg. In

less than ten switching cycles, the failed leg is recognized and

disabled. The redundant leg is utilized instead of the failed leg.

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Mokhtar Yaghoubi was born in Kermanshah, Iran, in 1985. He received his B.S. and M.S. degrees from Sharif University of Technology, Tehran, Iran, in 2008 and 2011, respectively. He is currently working toward the Ph.D. degree in Department of Electrical Engineering at Amirkabir University of Technology. His research interests include renewable energy and design and control of power electronic converters.

Javad S. Moghani was born in Tabriz, Iran, in 1956. He received the B.Sc. degree from South Bank Polytechnic, London, U.K., in 1982; the M.Sc. degree from the Loughborough University of Technology, Loughborough, U.K., in 1984; and the Ph.D. degree from the University of Bath, Bath, U.K., in 1995; all in electrical engineering.From 1984 to 1991, he was with the Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran, where he is

currently an Associated Professor. His research interests include electromagnetic modeling and design using the finite-element method, power electronics, and electric drives.

Negar Noroozi (S’17) was born in Tabriz, Iran, in 1985. She received the B.S. degree in electrical engineering from University of Tehran, Iran, in 2007, and the M.S. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2010. She is currently a Ph.D. candidate at the Department of Electrical and electronics engineering of Sharif University of Technology, Tehran, Iran. Her research interests are renewable energy,

AC/DC and DC/AC converters.

Mohammad Reza Zolghadri (SM’13) is an associate professor and head of power system group at the department of Electrical Engineering, Sharif University of Technology, Tehran, IRAN. He received his B.S. and M.S. degrees from Sharif University of Technology, in 1989 and 1992, respectively, and the Ph.D. degree from Institute National Polytechnique de Grenoble (INPG), Grenoble, France, in 1997, all in electrical engineering. In 1997 he joined the department of Electrical Engineering of Sharif University of

Technology. From 2000 to 2003, he was a Senior Researcher in the Electronics Laboratory of SAM Electronics Company, Tehran. From 2003 to 2005, he was a Visiting Professor in North Carolina A&T State University, USA. He is the founder and head of Electric Drives and Power Electronics Lab (EDPEL) at Sharif University of Technology. He is a member of founding board of Power Electronics Society of Iran (PESI). He is the author of more than 100 publications in power electronics and variable speed drives. His fields of interest are application of power electronics in energy systems, modeling and control of power electronic converters and variable speed drives.

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