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An Overv i ewofDig i t a l Ci rc u i t Test ing andDesign for Test ab i l i t y

Santosh Biswas

Dept. of EE , IIT Kharagpur

Advanced VLSI Design Laboratory(Testing)

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Faul t Sim ula t ion

Problem and motivation

Fault simulationalgorithms Serial

Parallel

Deductive

Concurrent

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Prob lem and Mot ivat ionFault simulation Problem: Given

A circuit

A sequence of test vectors

A fault model

Determine

Fault coverage - fraction (or percentage) of modeledfaults detected by test vectors

Set of undetected faults

Motivation

Determine test quality and in turn product quality Find undetected fault targets to improve tests

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Faul t s im ula t or in a VLSIDesign Proc ess

Ver i f ied des ignnet l i s t

Ver i f i ca t ioninpu t s t imu l i

Faul t s im ula t or Test vec t ors

Modeledfau l t l i s t

Testgenera to r

Testc o m p a c t o r

Faul tcoverage

?

Removet est ed fau l t s

Delete vec to rs

Add vec t o rs Low

Adequate

Stop

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Faul t Sim ula t ion Sc enar ioCircuit model: mixed-level

Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals

High-level models (memory, etc.) with pin faults

Signal states: logic Two (0, 1) or three (0, 1, X) states for purely

Boolean logic circuits

Timing: Zero-delay for combinational and synchronous

circuits

Mostly unit-delay for circuits with feedback

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Faul t Sim ula t ion Sc enar io

(cont inued)Faults:

Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay

faults; analog circuit fault simulators are not yet incommon use

Equivalence fault collapsing of single stuck-at faults

Fault-dropping -- a fault once detected is droppedfrom consideration as more vectors are simulated;fault-dropping may be suppressed for diagnosis

Fault sampling -- a random sample of faults issimulated when the circuit is large

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Faul t Sim ula t ionA lgor i thms

Serial

Parallel

Deductive

Concurrent

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Ser ia l A lgor i t hmAlgorithm: Simulate fault-free circuit and saveresponses. Repeat following steps for each faultin the fault list:

Modify netlist by injecting one fault

Simulate modified netlist, vector by vector, comparing

responses with saved responses If response differs, report fault detection and suspend

simulation of remaining vectors

Advantages: Easy to implement; needs only a true-value simulator, less

memory

Most faults, including analog faults, can be simulated

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Ser ia l A lgor i t hm (Cont .)Disadvantage: Much repeated computation; CPUtime prohibitive for VLSI circuits

Alternative: Simulate many faults together

Test vec to rs Faul t -f ree c i rc u i t

Ci rcu i t w i th faul t f 1

Ci rcu i t w i th faul t f 2

Ci rcu i t w i th fau lt f n

Com parat or f1 det ec t ed?

Com parat or f2 det ec t ed?

Com parat or fn det ec t ed?

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Para l le l Faul t Sim ulat ionCompiled-code method; best with two-states

(0,1)Exploits inherent bit-parallelism of logicoperations on computer words

Storage: one word per line for two-statesimulation

Multi-pass simulation: Each pass simulates w-

1 new faults, where wis the machine wordlength

Speed up over serial method ~ w-1

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Paral le l Faul t Sim . Ex am ple

ab c

d

e

f

g

1 1 1

1 1 1 1 0 11 0 1

0 0 01 0 1

s-a-1

s-a-0

0 0 1

c s-a-0 det ec t ed

Bi t 0 : fau l t -f ree c i rc u i t

B it 1 : c i r cu i t w i t h c s-a-0

B it 2 : c i r cu i t w i t h f s-a-1

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Deduc t ive Faul t Sim .Example

ab c

d

e

fg

1

1 1

0

1

{a0}

{b0 , c0}

{b0}

{b0 , d0}

Le = La U Lc U {e0}

= {a0 , b0 , c0 , e0}

Lg

= (Le

Lf

) U {g0

}

= {a0 , c0 , e0 , g0}

U

{b0 , d0 , f1}

Nota t ion : Lk i s fau l t l i s t fo r l ine k

kn is s-a-n fa ul t on l i ne k

Fau l ts de tec t ed byt he input vec t o r

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Conc . Faul t Sim . Ex am ple

ab c

d

e

fg

1

1

1

0

1

1

11

1

01

1 0

0

1

01

0

01

00

1

1

0

1

00

1

11

1

11

0

00

0

11

0

00

0

00

0 1 0 1 1 1

a0 b0c0 e0

a0 b0

b0

c0 e0

d0d0 g0 f1

f1

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Test ab i l i t y Measures

Controllability andobservability

SCOAP measures Combinational circuit example

Sequential circuit example

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PurposeNeed approximate measure of: Difficulty of setting internal circuit lines to 0 or 1

by setting primary circuit inputs Difficulty of observing internal circuit lines by

observing primary outputs

Uses: Analysis of difficulty of testing internal circuit

parts redesign or add special test hardware

Guidance for algorithms computing test patterns

avoid using hard-to-control lines Estimation of fault coverage

Estimation of test vector length

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OriginsOrig insControl theoryRutman 1972 -- First definition of controllability

Goldstein 1979 -- SCOAP First definition of observability

First elegant formulation

First efficient algorithm to compute controllability andobservability

Parker & McCluskey 1975 Definition of Probabilistic Controllability

Brglez 1984 -- COP 1st probabilistic measures

Seth, Pan & Agrawal 1985 PREDICT 1st exact probabilistic measures

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Test ab i l i t y Ana lys is

Invo lves Ci rc u i t Topolog ic a l ana lysis , but not es t vec t ors and no searc h a lgori t hm St a t ic analysis

L inear com put a t ional com p lex i ty Ot herw ise, i s po int less m ight as w e l l useautom at ic t es t -pa t t e rn generat ion andca lcu la te : Ex ac t faul t c overage Ex ac t t est vec t o rs

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Types of Measures SCOAP Sandia Cont ro l lab i l i t y and Observabi l i t y

Analys is Program Com binat iona l measures: CC0 Di f f i cu l t y of se t t ing c i rcu i t l i ne t o logic 0 CC1 Di f f i cu l t y of se t t ing c i rcu i t l i ne t o logic 1 CO Di f f i cu l t y of observ ing a c i rcu i t l ine

Sequent ia l measures analogous: SC0 SC1 SO

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Range of SCOAP Measures

Controllabilities 1 (easiest) to infinity(hardest)

Observabilities 0 (easiest) to infinity (hardest)

Combinational measures: Roughly proportional to # circuit lines that must be

set to control or observe given line

Sequential measures: Roughly proportional to # times a flip-flop must be

clocked to control or observe given line

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Golds t eins SCOAP MeasuresGolds t eins SCOAP Measures AND gate O/P 0 controllability:

output_controllability = min (input_controllabilities)+ 1

AND gate O/P 1 controllability:

output_controllability = (input_controllabilities)+ 1

XOR gate O/P controllability

output_controllability = min (controllabilities of

each input set) + 1

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Contro l lab i l i ty

Examples

Cont ro l lab i l i ty

Examples

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More Observabi l i tyExamples

More Observabi l i tyExamples

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Cont ro l lab i l i t y Through Leve l 0

Circ led num bers g ive l evel num ber. (CC0, CC1)

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Cont ro l lab i l i t y Throughnex t Level

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Combinat iona l

Observabi l i t y for Level 1Num ber in square box is leve l f rom pr imary ou tpu t s (POs).(CC0, CC1) CO

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Combinat iona lObservabi l i t ies for Level 2

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Final Com binat ional

Observabi l i t ies

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Sequent ia l Measure

Di f ferences Combinat iona l

Inc rement CC0, CC1, CO w henever you passt hrough a gat e , e i ther fo rw ards or back w ards Sequent ia l

Inc rement SC0, SC1, SO only w hen you passt hrough a f l ip -f lop, e i t her forw ards orbac k w ards, t o Q, Q, D, C, SET , or RESET

Both Must i t e ra te on feedbac k loops unt i l

c ont rol labi l i t i es s tabi l i ze

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D Fl ip-Flop Equat ions Assum e a sync hronous RESET l ine. CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0

(RESET ) SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0(RESET ) + 1 CC0 (Q) = m in [CC1 (RESET ) + CC1 (C) + CC0 (C),

CC0 (D) + CC1 (C) + CC0 (C)] SC0 (Q) is analogous CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0

(RESET ) SO (D) is analogous

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Sequent ia l Ex am ple

In i t ia l i za t ion

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Aft e r 1 I t e ra t ion

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Aft e r 2 I t e ra t ions

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St able Sequent ia l Measures

Fi l S t i l

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Final Sequen t ia l

Observabi l i t ies

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Com binat ional Au t om at icTest -Pat t ern Generat ion

(ATPG) Bas ic s

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Orig ins of St uc k -Faul t s

Eldred (1959) First use of structuraltesting for the Honeywell Datamatic 1000computer

Galey, Norby, Roth (1961) First

publication of stuck-at-0 and stuck-at-1faults

Seshu & Freeman (1962) Use of stuck-

faults for parallel fault simulationPoage (1963) Theoretical analysis ofstuck-at faults

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S

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Funct iona l vs . St ruc tura lFunct iona l vs . St ruc tura l

Functional ATPG generate complete set oftests for circuit input-output combinations 129 inputs, 65 outputs:

2129 = 680,564,733,841,876,926,926,749,

214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years

Structural test: No redundant adder hardware, 64 bit slices

Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests)

Takes 0.000001728 s on 1 GHz ATE

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R d P t t G t iRandom Pat t ern Genera t ion

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Random -Pat t ern Genera t ionRandom -Pat t ern Genera t ion

Flow chart formethod

Use to gettests for 60-80% of faults,then switch toD-algorithmor other

ATPG for rest

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Circ u i t and BinaryDec is ion Tree

Ci rc u i t and B inaryDec is ion Tree

Bi D i i DiBinar Dec is ion Diagram

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Binary Dec is ion DiagramBinary Dec is ion Diagram

BDD Follow path from source to sink node product of literals along path gives Booleanvalue at sink

Rightmost path: A B C= 1

Problem: Size varies greatly

with variable order

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Algor i t hm Com ple t eness

Definition: Algorithm is completeif it

ultimately can search entire binarydecision tree, as needed, to generate atest

Untestable fault no test for it even afterentire tree searched

Combinational circuits only untestable

faults are redundant, showing thepresence of unnecessary hardware

Algebras : Rot hs 5-Va luedAlgebras : Rot hs 5-Va lued

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Algebras : Rot h s 5 Va lued

and Mut hs 9-Valued

Algebras : Rot h s 5 Va lued

and Mut hs 9-Valued

SymbolDD0

1X

G0G1F0F1

Meaning1/00/10/0

1/1X/X0/X1/XX/0X/1

Fai l ing

Mach ine010

1XXX01

Good

Mach ine100

1X0

1XX

RothsAlgebra

Muth sAdd i t ions

R h d M h Hi h

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Rot h s and Mut h s Higher-Order Algebras

Rot h s and Mut h s Higher-

Order Algebras

Represent two machines, which are simulated

simultaneously by a computer program: Good circuit machine (1st value)

Bad circuit machine (2nd value)

Better to represent both in the algebra: Need only 1 pass of ATPG to solve both

Good machine values that preclude bad machinevalues become obvious sooner & vice versa

Needed for complete ATPG: Combinational: Multi-path sensitization, Roth

Algebra

Sequential: Muth Algebra -- good and bad machinesmay have different initial values due to fault

Pat h Sens i t iza t ion Met hodPat h Sens i t iza t ion Met hod

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Pat h Sens i t iza t ion Met hod

Ci rc u i t Ex am ple

Pat h Sens i t iza t ion Met hod

Ci rc u i t Ex am ple1 Fault Sensitization

2 Fault Propagation3 Line Justification

Pat h Sens i t iza t ion Met hodPat h Sens i t iza t ion Met hod

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Pat h Sens i t iza t ion Met hod

Ci rc u i t Ex am ple

Pat h Sens i t iza t ion Met hod

Ci rc u i t Ex am ple Try path f h k L blocked atj, since

there is no way to justify the 1 on i

1 0D

D

1

1DD

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Redundanc y Rem ovalUsing ATPG

Redundancyidentification

Redundancy removal

Redundant Hardw are andRedundant Hardw are and

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Redundant Hardw are and

Simpl i f i ca t ionSimpl i f i ca t ion

Redundant Faul t q sa1

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Redundant Faul t q sa1Redundant Faul t q sa1

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Mult ip le Fau l t Mask ingMult ip le Fau l t Mask ingfsa0 tested when fault qsa1 not there

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In t ent iona l RedundantImp l i can t BCEliminates hazards in circuit output

Major Com binat iona l

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Major Com binat iona l

Aut om at ic Tes t -Pa t t e rnGenerat ion A lgor i t hm s

D-Algorithm (Roth) 1966

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Branc h-and-Bound Searc h

Efficiently searches binary search treeBranching At each tree level, selectswhich input variable to set to what value

Bounding Avoids exploring large treeportions by artificially restricting searchdecision choices Complete exploration is impractical

Uses heuristics

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Ex am ple Faul t A sa0Ex am ple Faul t A sa0

Step 1 D-Drive Set A = 1

D1 D

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St ep 2 -- Ex am pleSt ep 2 -- Ex am ple

D10D

Step 2 D-Drive Set f =0

D

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St ep 3 -- Ex am pleSt ep 3 -- Ex am ple

D10D

Step 3 D-Drive Set k =1

D

1D

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St ep 6 -- Ex am pleSt ep 6 -- Ex am ple

D10D

Step 6 Consistency Set c =0, Set e= 0

D

1D

1

00

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ExampleExample

D10

X

D

Step 7 Consistency Set B =0

D

1D

1

000

Ex am ple Faul t s sa1

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Primitive D-cube of Failure

1

Dsa1

Ex am ple St ep 2 s sa1

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Propagation D-cube for v

1

D0

sa1 DD

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Ex am ple Faul t u sa1

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Primitive D-cube of Failure

1

D

0

sa1

Ex am p le St ep 2 u sa1

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Propagation D-cube for v

1

D

0

sa1D

0

Ex am p le St ep 2 u sa1

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Forward and backward implications

1

D

0

sa1D

00 1

0

1

0

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Incons is ten t

d= 0 and m= 1 cannot justify r= 1

(equivalence) Backtrack

Remove B= 0 assignment

Ex am ple Bac k t rac k

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Need alternate propagation D-cube for v

1

sa1 D

0

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Ex am ple St ep 4 u sa1

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Propagation D-cube for Zand implications

D

1

sa1D

0

D

1

1

00

0

1 1

Sequent ia l Ci rc u i t ATPG

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qTim e-Fram e Ex pansion

Problem of sequential circuitATPG

Time-frame expansion Nine-valued logic

ATPG implementation and drivability

Complexity of ATPG

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Ex am ple: A Ser ia l Adder

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FF

An Bn

CnCn+1

Sn

s-a-0

11

1

1

1

X

X

X

D

D

Com binat iona l log ic

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Conc ept o f T im e-Fram es

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If the test sequence for a single stuck-at faultcontains nvectors,

Replicate combinational logic block ntimes Place fault in each block

Generate a test for the multiple stuck-at fault usingcombinational ATPG with 9-valued logic

Comb.b lock

Faul t

Time-

f rame0

T ime-

f rame-1

T ime-

f rame-n+1

Unknownor g iven

In i t . s ta t e

Vec to r 0Vec t or -1Vec to r -n+1

PO 0PO -1PO -n+1

Sta te

var iab les

Nex t

s ta te

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Five-Valued Log ic (Rot h)

0 1 D D X

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0,1, D, D, XA

B

X

X

X

0

s-a-1

D

A

B

X X

X

0

s-a-1

D

FF1 FF1

FF2 FF2D D

Tim e-fram e -1 Tim e-f ram e 0

Nine-Valued Logic (Mut h)0 1 1/0 0/1 1/X 0/X X/0 X/1 X

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0,1, 1/0, 0/1, 1/ X, 0/X, X/0, X/1, XA

B

X

X

X

0

s-a-1

0/1

A

B

0/X 0/X

0/1

X

s-a-1

X/1

FF1 FF1

FF2 FF20/1 X/1

Tim e-fram e -1 Tim e-f ram e 0

Im p lem ent a t ion o f ATPG

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Select a PO for fault detection based on drivabilityanalysis.

Place a logic value, 1/0 or 0/1, depending on faulttype and number of inversions.

Justify the output value from PIs, considering allnecessary paths and adding backward time-frames.

If justification is impossible, then use drivability toselect another PO and repeat justification.

If the procedure fails for all reachable POs, then thefault is untestable.

If 1/0 or 0/1 cannot be justified at any PO, but 1/X or0/X can be justified, the the fault is potentiallydetectable.

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Design fo r Test abi l i t y (DFT):

Full-Scan

Def in i t ion

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Def in i t ionDesign for testability(DFT) refers to thosedesign techniques that make test generationand test application cost-effective.

DFT methods for digital circuits: Ad-hoc methods

Structured methods: Scan

Partial Scan

Built-in self-test(BIST)

Boundary scan

DFT method for mixed-signal circuits: Analog test bus

Ad-Hoc DFT Met hods

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Good design practices learnt through experience areused as guidelines:

Avoid asynchronous (unclocked) feedback.

Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates.

Provide test control for difficult-to-control signals.

Avoid gated clocks.

Consider ATE requirements (tristates, etc.)Design reviews conducted by experts or designauditing tools.

Disadvantages of ad-hoc DFT methods:

Experts and tools not always available. Test generation is often manual with no guarantee of high fault

coverage.

Design iterations may be necessary.

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Adding Sc an St ruc t ure

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Adding Sc an St ruc t ure

SFF

SFF

SFF

Combinat iona l

log ic

PI PO

SCANOUT

SCANIN

TC or TCK Not show n: CK or MCK/SCK f eed al l SFFs.

Test ing Sc an Regis t er

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Test ing Sc an Regis t erScan register must be tested prior toapplication of scan test sequences.

Example: 2,000 scan flip-flops, 500comb. vectors, total scan test length ~

106 clocks.Multiple scan registers reduce testlength.

Mul t ip le Sc an Regis t ersS fli fl b di t ib t d

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Mul t ip le Sc an Regis t ersScan flip-flops can be distributed among anynumber of shift registers, each having aseparate scaninand scanoutpin.

Test sequence length is determined by thelongest scan shift register.

Just one test control(TC) pin is essential.

SFF

SFF

SFF

Combinat ionallog ic

PI/SCANIN PO/SCANOUTM

UX

CK

TC

Sc an Overheads

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IO pins:

Area overhead:

Performance overhead:

Multiplexer delay added in combinational path;

approx. two gate-delays. Flip-flop output loading due to one additional

fanout; approx. 5-6%.

Power

Aut om at ed Sc an Des ign

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Behavio r, RTL, and logicDesign and ver i f ic at ion

Gate-levelne t l i s t

Sc an design

ru le aud i ts

Combinat ionalATPG

Scan hardw areinser t ion

Chip layout : Sc an-cha in op t im iza t ion ,t im ing ve r if i ca t ion

Sc an sequenc eand tes t p rogram

generat ion

Design and t estda ta fo r

manufac tur ing

Rulev io la t ions

Scanne t l i s t

Combinat ionalvec to rs

Sc an chain order

Mask da ta Test p rogram

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Mot iva t ion fo r St andard

Bed-of-na i ls pr in t ed c i rc u i t board t es te r gone

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We put c om ponents on bot h s ides o f PCB &rep laced DIPs w i th f la t pac k s to reduceinduc tanceNai ls w ould hi t c omponent s

Reduc ed spac ing bet w een PCB w i resNai ls w ould shor t t he w i res

PCB Tester m ust be replaced w i t h bu i lt -in t es tde l ivery syst em -- J TAG does t ha t Need s tandard Syst em Test Por t and Bus In tegra t e c omponents f rom d i f fe rent vendors

Test bus ident ic a l fo r var ious c omponentsOne ch ip has tes t hardw are fo r o ther c h ips

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Inst ruc t ion Reg is t e r

Loading w i t h J TAG

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Loading w i t h J TAG

Ser ia l Board / MCM Sc an

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Ser ia l Board / MCM Sc an

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The Slides have been collected form

the work of Vishwani D. Agrawal

Thanks !!!!