Journal ofComputational and Theoretical Nanoscience
Vol. 5, 1072–1088, 2008
Impact of High-� Gate Stacks on Transport andVariability in Nano-CMOS Devices
J. R. Watling1, A. R. Brown1, G. Ferrari2, J. R. Barker1, G. Bersuker3, P. Zeitzoff4, and A. Asenov1�∗1Device Modelling Group, Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow G12 8LT, UK
2INFM-S and Physics Department, University of Modena and Reggio Emilia, I-41100 Modena, Italy3SEMATECH, 2706 Montopolis Drive, Austin, TX 78741, USA
4Freescale Semiconductor, 255 Fuller Road, Albany, NY 12203, USA
Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters inorder to satisfy the International Technology Roadmap for Semiconductors (ITRS) requirementsfor drive current in high-performance transistors. Amongst the preferred near term solutions aretransport enhanced FETs utilising strained Si (SSi) channels. Additionally, high-� dielectrics areexpected to replace SiO2 around or after the 45 nm node to reduce the associated gate leakagecurrent problem, facilitating further scaling. However, in spite of significant recent technologicalachievements, in particular, in reducing charge trapping and crystallization of the dielectric, mobilitydegradation in the devices with the high-� gate stacks caused, in part, by the strong soft opticalphonon scattering leaves room for further performance improvement. In this work we study theimpact of soft optical phonon scattering on the mobility and device performance for conventionaland strained Si n-MOSFETs with high-� dielectrics using a self-consistent Poisson Ensemble MonteCarlo device simulator, with effective gate lengths of 67 and 35 nm.
Keywords: High-�, Intrinsic Fluctuations, Mobility, Monte Carlo Simulation.
8.1. The Impact of SixHf1−xO2 Alloy . . . . . . . . . . . . . . . . 10828.2. The Role of the Interfacial Layer . . . . . . . . . . . . . . . 1083
9. MOSFET Simulations with and without High-� Dielectrics . . 10849.1. Simulation of Si and SSi MOSFETs with SiO2 . . . . . . 10859.2. Simulation of Si and SSi MOSFETs with
∗Author to whom correspondence should be addressed.
1. INTRODUCTION
The scaling of MOSFETs as dictated by the InternationalTechnology Road Map for Semiconductors (ITRS) hascontinued unabated for many years and enabled the world-wide semiconductor market to grow at a phenomenal rate.However, the ITRS scaling is reaching hard limitations.One of the most significant problems is the maintenance ofelectrostatic integrity, which demands the use of extremelythin gate oxides, below 1 nm,1 to provide the required highgate capacitance, as well as the use of high channel dopingto control short channel effects. These requirements leadto low device performance and high-gate leakage.1 Onepromising solutions to these problems is the introductionof high-� dielectrics to replace the current SiO2 and oxini-trides as gate insulators.2 This allows the use of physicallythicker oxide, and as a consequence a reduction in gateleakage current, while still maintaining the necessary largegate capacitance, to ameliorate the requirement for highdoping a move towards fully-depleted SOI and double-gatedevices as these device architectures are able to provideincreased electrostatic integrity without the need for high-channel doping. In this paper however, we will concentrateon the proposed introduction of high-� dielectrics as theseare to be introduced first.1
Watling et al. Impact of High-� Gate Stacks on Transport and Variability in Nano-CMOS Devices
Jeremy R. Watling was born in Norwich, England in 1973, receiving his Bachelors Degree(B.Sc) along with the physics prize for his undergraduate studies at the University of EastAnglia in 1995, and his Ph.D. on carrier transport in quantum well structures in 1998from the same University. He then moved to the Department of Electronics and Electri-cal Engineering at the University of Glasgow to work on the simulation of Si/SiGe MOSstructures. In January 2002, he was appointed to the position of lecturer within the Depart-ment of Electronics and Electrical Engineering, at the University of Glasgow. His researchinterests include Monte Carlo and Drift Diffusion device simulation, especially the useof quantum corrections in both simulation techniques. In September 2004 was awarded aprestigious EPSRC Advanced Research Fellowship., to study the performance impact ofInterface Roughness and Self-Heating in Nano-scale devices. He has authored/co-authoredover 30 papers in the area of semiconductor simulations and was awarded best paper at the1998 SPIE conference.
Andrew Brown received the B.Eng. (Hons) degree in Electronics and Electrical Engi-neering from the University of Glasgow, Glasgow, UK in 1992. Since this time he hasbeen employed as a researcher in the Department of Electronics and Electrical Engineeringat the University of Glasgow working on the development of parallel 3D simulators forsemiconductor devices. He is lead developer of the Glasgow 3D ‘atomistic’ device simu-lator, designed to investigate intrinsic parameter fluctuations in nanometre scale MOSFETsdue to discrete random doping, line edge roughness, oxide thickness variation and gate-stack non-uniformity. Previous work includes the simulation of insulated gate bipolar tran-sistors. His interests include high performance parallel computing, device modelling andvisualisation.
Giulio Ferrari was born in Modena, Italy, in 1976. He received the laurea and Ph.D.degrees in Physics from Modena and Reggio Emilia University, Modena, Italy, in 2001and 2005, respectively. In 2005, he joined the Device Modelling Group of the Universityof Glasgow, Glasgow, United Kingdom. In 2006 he moved to S3 CNR-INFM NationalResearch Center, Modena, Italy. In his research experience he has worked on quantumsimulations of coherent and dissipative transport in electronic devices, development of MonteCarlo simulators and their application to the modelling of silicon nano-devices with high-�gate staks and on theoretical studies of the light-condensed matter interaction with particularinterest in dichroism and magnetic materials.
John R. Barker has been Professor of Electronics at the University of Glasgow, Glasgow,Scotland UK since 1985 where he was a co-founder of the Nanoelectronics Research Centrewith responsibility for the Theory and Modelling activities. He is a graduate of the Uni-versity of Edinburgh and the University of Durham. He obtained his Ph.D. in TheoreticalSolid State Physics from the University of Warwick in 1969 where he held a PersonalSRC Fellowship. From 1970 to 1985 he was a lecturer then senior lecturer in TheoreticalPhysics at the University of Warwick, Coventry, UK. He has been a visiting Professor atColorado State University, North Texas State University, and visiting scientist at The IBMT. J. Watson Laboratories. He is a Fellow of the Royal Society of Edinburgh and a Fellowof the Royal Astronomical Society. He has a broad range of research interests that cur-rently include Green function modelling of nano-devices, silicon germanium hetero-MOS,
interface roughness modelling, smart dust and highly parallel computer architectures. He has over 300 publicationsin semiconductor physics, hot electron theory, quantum transport theory, Monte Carlo simulation, device physics andmodelling, quantum theory of atomistic effects in ultrasmall devices, parallel computing, olfactory sensors, molecularelectronics.
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Gennadi Bersuker received the M.S. degree in Physics from Leningrad State University,Saint Petersburg, Russia, and the Ph.D. degree in physics from Kishinev State Univer-sity, Chisinau, Moldova. After graduation, he joined the Moldavian Academy of Sciences,Chisinau. Then, he was with Leiden University, Leiden, The Netherlands, and the Universityof Texas at Austin. Since 1994, he has been with SEMATECH Inc., Austin, as a SEMA-TECH Fellow, working on process-induced charging damage, electrical characterization ofCu/low-k interconnect, high-k gate stacks, and advanced CMOS process development. Hehas more than 200 publications on electronic properties of dielectrics and semiconductorprocessing and reliability.
Peter M. Zeitzoff received the B.S.E. and Ph.D. degrees in electrical engineering fromPrinceton University, Princeton, NJ, in June 1967 and June 1976, respectively. In 1975, hewas with Eastman Kodak Company, where he worked on the design and fabrication of large-scale CCD image sensors as well as on bipolar IC technology. In 1985, he was with AT&TBell Laboratories, where he worked in a number of areas, including assessment of IC tech-nology development options, BiCMOS technology development, and the development andapplication of internal TCAD process and device simulation tools for AT&T’s IC technolo-gies. From 1995 to 2006, he was with SEMATECH, where he was appointed to the SeniorFellow position in 2001. Since October 2006, he has been with the CMOS Research Depart-ment, Freescale Semiconductor, Austin, TX, where he is working on advanced MOSFETdevices and technology. His main areas of interest at SEMATECH were MOSFET devices
and device physics, including MOSFET electrical characterization, the impact of front-end process on MOSFET devicecharacteristics, and nonplanar MOSFET devices. Dr. Zeitzoff has been active in the International Technology Roadmapfor Semiconductors (ITRS) since 1997 and has chaired the ITRS’s US Regional Working Group on Process Integration,Devices and Structures since 2001. Also, he worked closely with the Emerging Research Devices group and helped guidethis new chapter in the ITRS.
Asen Asenov (M’96) received his M.Sc degree in solid state physics from Sofia University,Bulgaria in 1979 and the Ph.D. degree in physics from The Bulgarian Academy of Science in1989. He had ten-years industrial experience as a head of the Process and Device ModellingGroup in Institute of Microelectronics, Sofia, developing one of the first integrated processand device CMOS simulators IMPEDANCE. In 1989–1991 he was a Visiting Professorat the Physics Department of Technical University of Munich, Germany. He joined theDepartment of Electronics and Electrical Engineering at the University of Glasgow in 1991,and served as a Head of Department in 1999–2003. As a professor of Device Modelling,Leader of the Glasgow Device Modelling Group and Academic Director of the GlasgowProcess and Device Simulation Centre he coordinates the development of 2D and 3D quan-tum mechanical, Monte Carlo and classical device simulators and their application in the
design of advanced and novel CMOS devices. He has pioneered the simulations and the study of various sources ofintrinsic parameter fluctuations in decanano- and nano-CMOS devices including random dopants, interface roughnessand line edge roughness. He has over 350 publications in process and device modelling and simulation, semiconductordevice physics, atomistic effects in ultra-small devices and impact of variations on circuits and systems including in thelast 5 years more than 15 papers in IEEE Transactions journals.
However, there are many technological issues3 associ-ated with the use of high-� dielectrics in the MOSFETgate stack still be fully resolved such as trapped charge,partial crystallization of the dielectric and random grainorientations, as shown in Figure 1, leading to mobilitydegradation and instabilities. Some of these factors willalso introduce intrinsic parameter fluctuations in the cor-responding MOSFETs through the non-uniformity of thedielectric properties of the high-� material associated withrandom grain orientation and phase-separation.4 Suchvariations in the film structure are illustrated in Figure 2,
which shows a plan-view TEM image of a HfSiO film,with phase separation between HfO2 crystalline regions,with different grain orientations, and the amorphous SiO2
matrix.5 The resulting fluctuations in the gate stack struc-ture will vary from one device to another, resulting influctuation of important device parameters, similar to thefluctuations introduced by random discrete dopants andoxide thickness variations,6 currently limiting the perfor-mance and the reliability of bulk-like MOSFETs. How-ever, mobility degradation due to soft optical (SO) phononscattering7–10 might present a more fundamental drawback
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Watling et al. Impact of High-� Gate Stacks on Transport and Variability in Nano-CMOS Devices
–
+
Source
Channel
Drain
κ4: κ for amorphous regionκ1:κ for crystallised grain
Nfix: fixed charge density
thigh-κ: thickness of high-κ
tint: thickness of interfacial layer
Nit: trap density
Interfacial Layer
Metal Gate
Surfaceroughness
Interface trap
Interfacial dipoles
Phase-separationcrystallisation
κ1, κ2, κ3: different κ for
Different grain orientations
Random grain orientation
Remote phonon
Remote surface roughnessFixed charge
Λ: correlation length∆
∆: amplitude of roughness
e–
tint
thigh-κ
––
Fig. 1. Schematic showing the current technological issues associated with the introduction of high-� gate stacks, which will have an impact ondevice performance and reliability.
Fig. 2. Plan-view TEM image of a HfSiO film illustrating phase sepa-ration of the Hf and Si oxides.
limiting the performance of MOSFETs with high-�dielectrics. In this paper we will address each of the impor-tant issues raised above in turn. We will first address thefluctuations issue of random grain orientation and phase-separation and then finally the fundamental issue of mobil-ity degradation due to soft optical (SO) phonon scattering.
2. RANDOM GRAIN ORIENTATIONS
2.1. Simulation Methodology
The simulations were carried out within the Glasgow3D Drift-Diffusion/Density Gradient statistical devicesimulator,11 which is able to incorporate a polycrystalline
high-� gate stack with variations in dielectric constant fordifferent grains.12 In order to introduce a realistic grainstructure a large AFM image of polycrystalline grains13
has been used as a template, and scaled to give grainsizes typical for high-� material. The simulator imports arandom (in both location and orientation) section of thegrain template, which corresponds to the dimensions ofthe device. A recursive search algorithm has been imple-mented to identify all the mesh nodes within a particular“grain.” Then each individual grain is assigned a differentdielectric constant, chosen randomly from within a givenrange, which is then assigned to all the mesh nodes con-tained within that grain. An example of this is shown inFigure 3 for a 30× 30 nm channel MOSFET. Although,the MOSFET has a physical gate length of 40 nm, with
0 10 20x [nm]
y [n
m]
Die
lect
ric
cons
tant
300
5
10
15
20
25
30
10
12
14
16
18
20
22
Fig. 3. An example grain pattern for a 30× 30 nm channel MOSFETchosen randomly from the template image. The dielectric constantassigned to each grain is illustrated.
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High-κ
SiO2
Si
Fig. 4. Vertical assignment of dielectric constants for the bulk MOSFETshowing, on the top, a layer of high-� dielectric with lateral varia-tion determined by the pattern randomly extracted from the template.A 0.5 nm interfacial layer of SiO2 is included above the interface withsilicon.
5 nm sub-diffusion either side to provide the 30 nm chan-nel length. As the typical grain size (∼2–10 nm) is on thesame scale as, or larger than, the oxide thickness consid-ered for the MOSFETs we are interested in, we assumethe dielectric consists of a single layer of grains, and theboundaries between grains are considered to be vertical.This is illustrated in Figure 4, which depicts the verticalstructure (resulted from the full 3D simulations) consist-ing of a top high-� layer with random orientation of thedielectric grains, deposited on 0.5 nm interfacial layer ofSiO2. The usual value of 3.9 for the relative dielectricconstant of SiO2 is assumed, although in reality the inter-facial layer maybe silicon-rich and therefore could havea slightly larger dielectric constant. Underneath, the bulksilicon of the planar MOSFET is considered.
2.2. Results for Random-Grain OrientationFluctuations
The fluctuations in surface potential resulting from thedielectric structure presented in Figure 3 are shown inFigure 5. It can be seen that in the regions of the channelunder grains with a high dielectric constant the potentialbarrier is lowered, whereas in the presence of grains witha low dielectric constant the barrier increases. This varia-tion in surface potential will be different for each devicedue to different dielectric patterns, leading to variation inimportant device characteristics, such as threshold voltage,between devices.
Figure 6 shows the fluctuations in threshold voltage,�VT, for a series of bulk-planar MOSFETs scaled from50 nm to 15 nm. The dielectric structure is as described inthe previous section where the gate stack for each deviceconsists of a 0.5 nm interfacial SiO2 layer and a poly-crystalline high-� on top of it with a random dielectric
Length [nm] Wid
th [n
m]
50403020100
30
20
10
60
Pot
entia
l [V
]
0.06
0.04
0.02
–0.02
–0.04
–0.06
0
Fig. 5. Surface potential in a 30×30 nm MOSFET demonstrating thefluctuations induced by variations in dielectric constant.
pattern. One would expect that as the device dimen-sions are reduced the magnitude of the fluctuations wouldincrease, and this is the trend initially. However, this istempered by the scenario chosen for the scaling of theoxide thickness with reduction in channel length, in accor-dance with the ITRS.1 The scaling reduces the capacitivecontribution of the high-� relative to the contribution of thefixed-thickness interfacial layer, limiting the effect of thehigh-� dielectric fluctuations at small device dimensions.
For the 30 nm device the standard deviation in thresholdvoltage is approximately 10 mV, at this channel length,the dominant source of intrinsic parameter fluctuations israndom discrete dopants as we have shown previously,14
which typically produces a �VT on the order of 40 mV, andwhich increases significantly at shorter channel lengths.15
Therefore, while variation in the gate-dielectric due to ran-dom grain orientation will undoubtedly contribute to theoverall fluctuation in device characteristics, it will not bethe dominant factor. This situation however, may changewith the transition to low-doped channel UTB MOSFETsand multiple gate MOSFETs.
10 20 30 40 50
Channel length [nm]
8
9
10
11
12
σVT [
Vm
]
Fig. 6. �VT for bulk MOSFETs scaled from 50 nm to 15 nm. Simula-tions of 200 devices with unique grain pattern and associated dielectricconstants were performed for each channel length.
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κ2 κSiO2κSiO2
κ1κ1
α
α
H(x)
x
Fig. 7. Method used for allocating dielectric properties based on thegeneration of a random surface.
3. PHASE-SEPARATION
3.1. Simulation Methodology
To carry out these simulations the 3D Glasgow ‘atomistic’device simulator11 has been modified to include spatialvariations in the gate dielectric associated with structuralnon-uniformity of the high-� gate stack. To illustrate thiseffect we have carried out simulations in the case of crys-talline phase separation, where grains of a high-� mate-rial (e.g., HfO2) with different crystal orientation interfaceeach other, or are embedded within a SiO2 matrix.
The TEM image of Figure 2, illustrates typical phaseseparation of HfSiO into HfO2 poly-crystal regions anda SiOx matrix resulting from high temperature annealing.There is a definite characteristic length to the spacing andsize of the HfO2 crystals, with the crystal size being ona scale of approximately 5 nm. This suggests that a sta-tistical approach for generating the structure of the high-�dielectric should be adopted. Our approach for describingthe high-� structure is based on the 2D Fourier synthesistechnique, which has been previously utilised for the gen-eration of random surface roughness patterns.6 A randomsurface is generated with given statistical parameters, rmsamplitude, �, and correlation length, �. First a complex
(a) (b) (c) (d)
Fig. 8. Dielectric patterns produced by the model with different parameters: (a) �=�, �= 5 nm, (b) �= 075�, �= 5 nm, (c) �= 05�, �= 5 nm,(d) �= 075�, �= 25 nm.
array with N ×N elements is constructed, whose ampli-tude is determined by the power spectrum obtained froma Gaussian autocorrelation function with the specified val-ues of � and �. The phases of the elements are selectedrandomly, ensuring that each surface is unique. Severalconditions16 must be satisfied to ensure that the corre-sponding 2-D surface in real space, obtained by inverseFourier transformation, represents a real function, H�x y�.
Figure 7 illustrates how this random surface, H , can beused to assign the dielectric constants to the different mate-rials in the gate oxide. A single parameter �, chosen tobe a particular fraction of �, controls the phase separationwith SiO2 assigned for −�<H <�, and high-� dielectricassigned in the rest of the material. This provides a struc-ture similar to that evident from the TEM image (Fig. 2)consisting of isolated grains of high-� material surroundedby SiO2. Figure 8 shows the effect of varying the param-eters � and � on the generated patterns. Reducing thevalue of � reduces the separation between regions of dif-ferent high-� dielectric, and reducing � to zero removesthe phase separation. Changing � alters the overall scaleof the random pattern and is adjusted to give grain sizesof approximately 5 nm.
3.2. Results for Random Phase-SeparationFluctuations
The potential drop between gate and channel in the regionsof high-� will naturally be less than across regions ofSiO2. This will lead to spatial fluctuations in the sur-face potential which will inevitably lead to variations indevice characteristics from one device to the next. Figure 9shows the electrostatic potential within a MOSFET, clearlydemonstrating the fluctuations in surface potential due tostructural variations in the gate oxide. The random dielec-tric pattern is shown in the plane above the device withthe regions of high-� dielectric producing higher surfacepotentials than in those parts of the channel below an SiO2
region. ID–VG characteristics for ten 50×50 nm MOSFETswith random high-� patterns are shown in Figure 10clearly demonstrating the spread in threshold voltages.
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Fig. 9. Electrostatic potential in a 50× 50 nm MOSFET showing thefluctuations in surface potential due to the spatial variations in gatedielectric. The dielectric pattern is shown in the plane above.
The parameters used in the phase separation model forthese simulations are � = 07� and � = 3 nm as theseparameters produce patterns on the same scale as the fea-tures in the TEM image of Figure 2. Here a single value ofdielectric constant (�= 20�0) is used in the high-� regions.Also shown are the curves for a pure SiO2 gate oxide andpure high-� (above an interfacial layer). These two con-ditions are the limiting cases for the fluctuations and thecurves from devices with random phase separation patternswill lie between these two curves. In all cases the gateoxide is 4 nm thick, and the expected degradation in sub-threshold slope due to the reduced gate oxide capacitancewhen SiO2 is used, is evident.
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VG [V]
I D [
A/µ
m]
10–10
10–9
10–8
10–7
10–6
10–5
10–4
10–3
Pure SiO2
Pure High-κHigh-κ w/ interfacial layer
Fig. 10. ID–VG characteristics for 10 devices with random dielectricpattern, and the limiting cases.
10 20 30 40 50
Channel length [nm]
10
15
20
25
30
35
40
σVT [
mV
]
Fig. 11. Dependence of �VT on channel length for samples of 200devices with random gate dielectric patterns.
In Figure 11 the standard deviation in threshold volt-age, �VT, for a sample of 200 devices, each with a differ-ent gate dielectric pattern, is shown for different channellengths. This increases as the channel length is reducedbelow 50 nm, however it saturates at shorter channellengths to a value of approximately 33 mV. This saturationbehaviour is characteristic of intrinsic parameter fluctua-tions, which are caused by stochastic structural variations,which can be modelled using this Fourier synthesis tech-nique. As the device feature size approaches the correla-tion length of the fluctuations the boundaries imposed bythe limiting cases discussed above restrict the magnitudeof the fluctuations. This behaviour has also been observedin the cases of oxide thickness variation.6
Figure 12 shows the dependence of the fluctuations inon-current, �Ion, on the channel length. This demonstratesthat for the channel lengths and device structure consid-ered here there is very little change in the fluctuations withchannel length, with �Ion being approximately 12–13%in each case. However in such conditions, in additionto the fluctuations due to variations in the electrostatics
10 20 30 40 50
Channel length [nm]
11
12
13
14
σ Ion
[%
]
Fig. 12. Dependence of �Ion on channel length for samples of200 devices with random gate dielectric patterns.
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within the device, which are fully captured by the drift-diffusion simulator, there will be increased scattering fromthe potential fluctuations within the channel, which willlead to variations in the transport from device to device.
4. HIGH-� MOBILITY DEGRADATION
High-� materials allow the use of a thicker gate dielectricas compared to SiO2 and oxynitride, whilst maintaining thegate capacitance and thus reducing gate leakage. However,it is not all good news from the point of view of manu-facturing the next generation of silicon-based MOSFETs.Apart from the problems due to morphology discussedabove, all known high-�’s demonstrate some degree ofmobility degradation, which may be associated, amongother factors, with the coupling of carriers to the sur-face soft-optical (SO) phonons. We note here that thesephonons are not a new phenomenon and are present, evenfor the traditional Si/SiO2 interface. Fortunately, nature hasbeen kind to us here with relatively large phonon ener-gies, minimizing the phonon population and weak cou-pling, resulting in less than 5% degradation in this case.However, severe mobility degradation in the presence ofhigh-� becomes evident when comparing the vertical fielddependence of mobility for a wide range of high-� mate-rials against the SiO2 data (even when the effect of fasttransient charge trapping on mobility17 is excluded). AsHf-containing oxides are the leading high-� contenders,we have performed a detailed analysis of the mobility inHf-based gate stacks, considering a number of structuresand compositions. We have also studied the impact of aSiO2 interfacial layer between the channel and the HfO2
which reduces the detrimental effect of the SO phononscattering on the mobility, but increases the equivalentoxide thickness (EOT) of the gate dielectric. We have alsostudied the impact of Hafnium Silicate (SixHf1−xO2), apossible material of choice for the first commercial intro-duction of high-� gate stacks being thermally stable andoffering a good compromise between small EOT and largeelectron mobility.
5. THEORY AND SIMULATIONMETHODOLOGY
5.1. The Monte Carlo Simulator
The scattering mechanisms that play an important rolein the presence of high-� dielectrics are complementaryto the standard scattering mechanisms that control mobil-ity in silicon. The Monte Carlo (MC) methodology allowsthe modelling of the scattering mechanisms, band struc-ture and charge propagation in the presence of exter-nal fields in a self-consistent environment.18 The electronband-structure model employed within our MC simulatoris based on the commonly used Si band structure consist-ing of a set of six non-parabolic, ellipsoidal �-valleys, and
is sufficient for accurately modelling the electron trans-port in Si up to moderately high fields and energies.19
The six conduction band valleys are grouped in threepairs: one valley pair pointing in the �100� direction, onein the �010� direction and one in the �001� direction.The ellipsoidal nature of the conduction band valleys isincluded explicitly through the use of different longitudinaland transverse masses, making use of the Herring-Vogttransformation.20 The simulator considers all the rele-vant scattering mechanisms including: inelastic acousticphonon scattering; ionised impurity scattering with degen-erate screening (which is especially important in heavilydoped channels with a high concentration of mobile car-riers contributing to the screening);21 interface roughnessscattering (see Section 6); and optical inter-valley phononscattering which is modelled using 3 f -type and 3 g-typephonons.21 Our bandstructure model for Si also treats theL- and � -valleys in the same non-parabolic ellipsoidalframework. However, these valleys play a negligible rolein determining the carrier transport in modern devices dueto their large energy separation from the �-valleys.
5.2. Soft Optical Phonons
The introduction of high-� gate dielectrics typicallyreduces the gate leakage current by several orders ofmagnitude.3 However, it also introduces strong soft-optical(SO) phonon scattering, which degrades the mobility.7 Thescattering results from the strong ionic polarizability ofthe high-� material, which is fundamentally related to itslarge dielectric constant. It therefore seems unlikely thatmaterials with high-� and weak SO phonon scattering canbe found. Electrons scatter from the SO phonons via aFröhlich interaction which has an unscreened scatteringfield amplitude at the dielectric interface given by:
��SO ={��SO
2Q
[1
��Si +�iox
− 1��Si +�0
ox
]} 12
(1)
for when mode 1 responds (the SO phonon mode associ-ated with TO1, an expression for which is given below).A similar equation exists for when mode 2 responds, with�i
ox replaced by ��ox and with �0ox replaced by �i
ox. In theabove equation we have neglected the response of plas-mons in the gate and the channel. ��ox, �0
ox, �iox and ��Si
are the optical, static and intermediate permittivities forthe oxide and Si respectively and �SO is the frequencyof the soft-optical (SO) phonon, calculated from the twodominant transverse-optical (TO) phonon modes in thedielectric via the Lyddane-Sachs-Teller relationship. TheSO phonon frequencies �SO are approximated by:
�SOi =[��Si +�0
ox
��Si +�iox
] 12
�TO1 (2)
for SO mode 1, and similarly for mode 2.22
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The scattering amplitude matrix element ��SO decreasesaway from the dielectric interface as e−Qt , where Q rep-resents the in-plane momentum transfer and t—the dis-tance from the interface. The scattering rate for soft-opticalphonon scattering from a initial state k to a final state k′,is proportional to the square of the matrix element, whichin turn is given by:
S�k k′�=(e2
4�
)�
�
[Nq
Nq +1
]e−2QtD�k′� (3)
where Nq denotes the phonon populations, (Nq + 1 foremission and Nq for absorption), given the Bose-Einsteindistribution function:
Nq =1
exp(��SOkBT
)−1(4)
and D(k′) denotes the density of states associated with thefinal state k′. Here, this is given by the two-dimensionaldensity of states, because the electrons within the substratedo not have translational invariance in the direction per-pendicular to the oxide, and accordingly we assume an ide-alised wave-function for the electrons in the semiconductorat a distance d from the interface of the form !�z−d�eikr/�2��2.23 We note that the matrix element decreases withenergy due to the (1/Q) term and thus the total scatter-ing rate for soft-optical phonon scattering will decreasewith increasing energy as is typical of a Fröhlich typeinteraction.24 The scattering rate decreases with increas-ing energy and drops exponentially as a function of thedistance from the Si/HfO2 interface. The state of scatter-ing for the k-vectors parallel to the interface is determinedby conservation of momentum and energy, while k-vectorin the z-direction is conserved, as is consistent with thetwo-dimensional density of states employed.
6. SURFACE ROUGHNESS SCATTERING
6.1. The Model
In a semiclassical regime, scattering from roughness atthe interface may be considered as a boundary condi-tion on the electron distribution function.25 26 In such ascheme, the scattering from the interface is treated asbeing a mixture of diffuse scattering and specular reflec-tion. The fraction of reflected and diffused carriers istypically considered to be constant, independent of theenergy (k-vector) of the carrier, and the type of inter-face, and isotropic with respect to the outgoing directionafter the scattering (see e.g., the original model and suc-cessive applications25 27 28). However, this approach doesnot exhibit the important reduction in the mobility thatis observed at low inversion fields given this and thelack of physical basis for the specular, diffuse approach.In this paper, the problem of interface roughness scat-tering is addressed in a more complete way, following anon-perturbative approach29 30 that allows us to take into
account the carrier energy, the roughness characteristics,and the dependence of the scattering probability on theincoming and outgoing k-vectors.
The model is based on the fact that, when the scatteringevent is an elastic (hard) scattering from a rough surface,it is possible to incorporate its effect as a boundary con-dition for the carrier distribution,31 32 the theory of whichis based on Kirchoff’s diffraction theory.33 The incidentcarrier is described as a plane wave and the spatial proba-bility distribution of the diffused carrier is determined withthe emergent flux, based on geometrical scattering froma surface. The emergent flux depends on the correlationlength, &, and on the root mean square (RMS), �, of theroughness distribution. The method has been developed inthe limit & � �, that conditionally is generally satisfiedfor the semiconductor/oxide interfaces under investigation.It employs the far-field approximation,33 which is satisfiedwhen the observation position, r , is sufficiently far fromthe interface. In the present case, the condition r > �2�dB
has to be fulfilled33 where �dB is the de-Broglie wave-length of the carrier and � is the RMS height of the inter-face. For a thermal electron in the conduction band, theestimated wavelength in equilibrium is �dB ≈ 8 nm at atemperature of 300 K and �dB ≈ 2–3 nm under large biasconditions. Considering the mean free path between col-lisions as a good evaluation of r for a Si MOSFET withSiO2 gate dielectric, the smallest mean free path values≈8–9 nm obtained are within the high energy region inthe middle of the channel in saturation.
An isotropic and exponential autocorrelation functionfor the roughness at the Si/SiO2 interface is assumed, achoice well supported in the literature.34 However, themodel is easily adaptable to different autocorrelation func-tions, such as a Gaussian one. The model is used to cal-culate the probability for a carrier hitting the interface tosuffer a specular scattering:
PSpecular = e−4�2k2 cos2 )in (5)
where k is the wave-vector of the incoming carrier and)in is the incident angle with respect to the normal tothe interface. If the carrier undergoes a specular reflec-tion, its new wave-vector is calculated accordingly. Ifthe specular scattering is rejected the carrier undergoes adiffuse scattering. The angular probability distribution isthen calculated from:
PDiffuse�)in )out�∝�cos)in + cos)out�
2
1+&2k2�sin )in + sin )out�2/2
(6)
where )out is the emergent angle with respect to the normalof the interface. Equation (6) may be found from a solutionof the Lippmann-Schwinger equation, for a wave packetelastically scattering of a rough interface as a bound-ary condition, in the far-field approximation employedhere and then normalizing the average flux density tounity.29 Further details maybe found in the following tworeferences.32 35
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The probability distribution depends explicitly on thephysical parameters & and � of the interface, on the carrierenergy through the k-vector, on the incoming and out-going direction of the carrier. If the surface is smoother(�→ 0 and &→�), the probability of specular reflectionincreases and the angular probability for diffuse scatteringforms a lobe around the specular angle. On the other hand,the angular probability for diffuse scattering spreads outand tends to be more isotropic when &→ 0.
In the Monte Carlo procedure, the implementation ofthe surface roughness model proceeds as follows: duringthe Monte Carlo simulation, when a particle impacts theinterface, the probability of specular reflection is evalu-ated according to Eq. (5) and compared to a random num-ber uniformly distributed between 0 and 1 to determinewhether specular or diffuse scattering is selected; if a dif-fuse scattering event occurs then the outgoing direction isdecided according to Eq. (6).
6.2. Calibration for SiO2
Firstly, the model parameters determining interface rough-ness scattering are calibrated against the universal mobilitycurves for the Si/SiO2 interface published by Takagi.36
The mobility simulations are performed in a MOS capac-itor structure, representative of the inversion layer in theactive channel region of a long-channel MOSFET. Thestudy of the mobility dependence on the vertical field givesa good indication of the impact of SO phonons. Such astudy also provides a good indication for the possible per-formance of decananometre devices. Recent studies37 38
have shown that scattering within the channel continuesto affect the ION current in nano-scale MOSFETs, wherethe fully ballistic regime is never reached. The simula-tions were carried out for substrate acceptor concentra-tions 2× 1016 cm−3, 72× 1016 cm−3 and 3× 1017 cm−3
0 200 400 600 800 1000 1200
Effective field (kV/cm)
0
100
200
300
400
500
600
700
800
Mob
ility
µef
f (cm
2 /Vs)
3.0×1017 cm–3
7.2×1016 cm–3
2.0×1016 cm–3
Fig. 13. Electron mobility versus effective field Eeff . The results areshown for three values of substrate doping concentration, as given in thelegend. The solid lines are the experimental results from Ref. [35], andthe dashed lines are the results obtained via the MC simulator.
0 200 400 600 800 1000 1200
Effective field (kV/cm)
0
100
200
300
400
500
600
700
800
Mob
ility
µef
f (cm
2 /Vs)
7.2×1016 cm–3
Without ionised-impurityscattering
Fig. 14. Electron mobility in the inversion layer at 300 K versus effec-tive field Eeff . The substrate doping concentration is 72×1016 cm−3. Thedashed red curve with the circle symbol is the same as shown in theprevious figure, Figure 14; the solid blue curve with the square symbolis obtained excluding the ionised-impurity scattering.
respectively, for which experimental data is available. Thevalues of the energies of the f and g phonons responsiblefor intervalley scattering used in the simulations are thosegiven in Ref. [39], along with corresponding values ofthe deformation potentials used. Additionally the simula-tor also includes the effect of intravalley inelastic-acousticelectron–phonon scattering, distinguishing between longi-tudinal and transverse modes, along with ionized impu-rity scattering. The best fit was obtained for a correlationlength, & = 13 nm and an RMS amplitude, � = 04 nm,assuming an exponential autocorrelation function, whichis shown to provide a better fit to the experimental datafor the Si/SiO2 interface compared to the Gaussian auto-correlation function.34 These values are in good agreementwith the experimental data (&= 13 nm and �= 048 nm)of Goodnick.34 The values of & and � are kept the samefor all the doping concentrations. Comparison between thesimulated and measured dependence of the mobility onthe electric field normal to the interface is illustrated inFigure 13.
The mobility decrease at low perpendicular fields is dueto the unscreened substrate ionised impurity scattering.40
In order to illustrate this, we have conducted simula-tions for a single value of the substrate doping con-centration (72 × 1016 cm−3) excluding the scattering ofelectrons from ionised impurities. In this case, illustratedin Figure 14, the mobility decreases monotonically withan increasing effective electric field, thus confirming theabove argument.
7. INVERSION LAYER MOBILITY FORHIGH-� OXIDES
A number of possible high-� dielectrics have been pro-posed in the literature (see e.g., Refs. [2 7]). Table I
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Table I. Parameters used in simulations. Values for SiO2, AlN, Al2O3
and HfO2 are from Ref. [7] and references therein; the values for Lu2O3
are from Ref. [41], LaAlO3 from Refs. [42, 43], La2O3 from Refs.[43, 44].
summarises the parameters for the high-� dielectrics stud-ied in our simulations, including SiO2.
Replacing the SiO2 dielectric in MOSFET gate stacksby a high-� dielectric increases the SO phonon scatteringsignificantly, due to a decrease in the SO phonon energies,�SO1 and increased difference between the static �0
ox andhigh-frequency ��ox dielectric constants. We note that whileSO phonon scattering is present for SiO2, it is very small,due to relatively large SO phonon energy and reduced cou-pling, due to the small difference between the static andhigh-frequency dielectric constants. It therefore has a neg-ligible effect on the mobility. The reduction in the channelmobility as a result of the introduction of different high-�gate dielectrics is shown in Figure 15. Due to the lackof available data, the SiO2 interface roughness parametersare used in all these simulations. The results presentedmay therefore be considered to represent the best possiblescenario, it being unlikely that the quality of the high-�dielectric/silicon interface will exceed that of SiO2 giventhe infancy of the high-� dielectric fabrication processesrelative to SiO2 and the natural affinity that silicon dioxidehas for silicon.
0 200 400 600 800 1000
Effective field (kV/cm)
0
100
200
300
400
500
600
Mob
ility
µef
f (cm
2 /Vs)
SiO2AlNLu2O3Al2O3HfO2LaAlO3La2O3
Fig. 15. Electron mobility versus effective field Eeff . The resultsreported are for different high-� materials and SiO2, as shown in thelegend.
It is clear that the replacement of SiO2 with high-�materials leads to a significant degradation of the electronmobility in the inversion layer. This effect is expected, andhas already been analysed in detail.7 Both the dielectricconstant and the phonon energies of the different materi-als play a role in the determination of the total electronmobility, giving as a result a general trend of decreasingmobility while increasing �0
ox, with some deviations due tothe alternating energies of the SO phonon modes involvedin the calculations, as reported in Table I. For example,the higher SO phonon energy explains why LaAlO3 has ahigher simulated mobility compared to HfO2 despite hav-ing a higher dielectric constant. A similar argument holdsfor Al2O3 as compared to Lu2O3, and explains why themobilities of AlN and SiO2 are similar. One should notealso that the measured mobility values can be stronglyinfluenced by multiple factors including the density offixed charges in the dielectric near its interface with thesubstrate and interface state density, which can be affectedby the specifics of the device fabrication process.
8. ALTERNATIVE SOLUTIONS
8.1. The Impact of SixHf1−xO2 Alloy
Hafnium Silicate SixHf1−xO2 is a strong high-� gatedielectric candidate for near future introduction,45 due toimproved thermal stability, homogeneity and uniformityof electrical properties compared to HfO2.46 In order tostudy the impact of its composition, we have simulated thevertical field dependence of the mobility for different stoi-chiometries of the SixHf1−xO2 alloy. The EOT in the simu-lations was fixed at 15 nm, therefore the physical HafniumSilicate thickness changes with x. The interface roughnessparameters were kept the same as those determined fromthe SiO2 calibration. When considering a composite layerit is important to use an accurate estimate for composition(x value) dependence of the dielectric constants and theTO phonon energies in order to determine the SO phononscattering rates. In the SixHf1−xO2 case, we estimate thedielectric constants using an interpolation scheme basedon the Clausius-Mossotti relationship:47
�SixHf1−xO2−1
�SixHf1−xO2+2
= x�SiO2
−1
�SiO2+2
+ �1−x��HfO2
−1
�HfO2+2
The other physical quantities involved in the simulationshave been estimated using Vegard’s law.48
The dielectric constants, both static �0ox and high-fre-
quency ��ox, calculated using the Clausius-Mossotti inter-polation are plotted in Figure 16. Moving away from SiO2
by increasing the fraction of Hf towards HfO2, a sub-stantial increase in the difference between the static andhigh-frequency dielectric constants is observed. This alongwith the decrease in the SO phonon energies leads to anincrease in the amount of SO scattering accounting for theobserved decrease in mobility with increasing Hf content.
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0 0.2 0.4 0.6 0.8 1
Fraction x of Si in SixHf1–xO2
0
5
10
15
20
25D
iele
ctri
c co
nsta
nt, κ
StaticHigh-Freq.
Fig. 16. Dielectric constants in the SixHf1−xO2 oxide, calculated usingthe Clausius-Mossotti relationship.
Simulation results for the impact of SixHf1−xO2 alloycomposition on the mobility are presented in Figure 17,with the increase in the amount of Hf, the mobilitydecreases due to the increased role of remote SO phononscattering, caused by a lowering of the phonon ener-gies and stronger coupling. The downturn in the mobilityobserved at low effective fields, due to the decrease inscreening for ionised impurity scattering is not observedfor high Hf concentrations due to the dominance ofSO phonon scattering, but gradually reappears as the Hfcontent decreases.
8.2. The Role of the Interfacial Layer
HfO2 is the leading high-� candidate for initial introduc-tion into real MOS devices.1 For this reason, we havefocused our study of the impact of the interfacial layeron HfO2 gate stack based materials, although the results
0 200 400 600 800 1000
Effective field (kV/cm)
0
100
200
300
400
500
600
Mob
ility
µef
f (c
m2 /V
s)
SiO2Si75% Hf25%O2Si25% Hf75%O2 HfO2
Fig. 17. Electron mobility versus effective field Eeff for an alloy ofSixHf1−xO2 as given in the legend.
obtained are still qualitatively valid for the other high-�materials.
In a realistic HfO2 based gate stack, the presence ofan interfacial SiOx layer between the Si channel and thehigh-� dielectric has to be taken into account.49 Here wepresent an initial attempt to simulate the impact of such aninterfacial layer on the channel mobility. A SiO2 interfaciallayer is assumed, although the true stoichiometry of thislayer is not exactly known.
This assumption is justified by a number of studies50–52
showing that the interfacial layer between Si and Hf oxidehas a SiOx stoichiometry, and any diffusion of Hf into theinterfacial layer is minor and occurs only at the very edgeof the HfO2/SiOx interface. Very little is known about theprecise stoichiometry (x value) of the SiOx layer. However,in many gate stacks studied,53–55 an interfacial layer ofSiO2 is intentionally grown in order to control the surfaceroughness characteristics and to reduce the interface statedensity and the interaction between electrons and the SOphonons associated with the high-� dielectric.
In order to accurately model the SO phonon scatter-ing in the presence of an interfacial layer, we must mod-ify slightly Eqs. (1)–(3), above as they are only valid fora single-layer oxide.7 Here we employ the approxima-tions and results and equations discussed and presentedin the appendix of Ref. [7], decoupling the high-� andSiO2 phonon modes. This is valid since ����TO represent-ing the TO mode for the high-� oxide is much less thanthe corresponding TO mode for the SiO2, thus ����TO ���SiO2�TO, neglecting the impact of plasmons from thesource and the channel as in Ref. [7]. We make one fur-ther simplification assuming that QtSiO2 is small which isreasonable since tSiO2 is likely to be small, along with Q∼05–1× 106 cm−1, since we are concerned with low-fieldmobility here. This enables us to simplify the problemconsiderably and make the model suitable for device sim-ulation, by neglecting the Q dispersion of the SO phononmodes. Results from simulations of the mobility depen-dence on the perpendicular field at different thicknesses ofthe interfacial layer are presented in Figures 18 and 19.The limiting cases of the SiO2 mobility and HfO2 mobilityfor zero thickness of the interfacial layer are also included.The experimental data published in Ref. [56] are shownfor comparison, marked with circle and square symbols.
The experimental results confirm the simulation trends.The presence of the interfacial layer reduces the HfO2
related mobility degradation. With the increasing thicknessof the SiO2 interfacial layer, the mobility approaches theSiO2 mobility. Therefore the interfacial layer is benefi-cial in increasing the inversion layer mobility, althoughof course it does limit the minimum EOT that can beachieved. The increase in mobility is due to the decouplingbetween the motion of the electrons in the inversion layerand those phonons in the HfO2.
There is also interest in the implementation of high-�materials with a dielectric constant higher than that of
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Inter layer thickness (nm)
0
0.5
1
1.5
Eeff (kV/cm)
200
400
600
800
1000M
obili
ty (
cm2 /
Vs)
100
200
300
400
500
0
2
HfO2 with SiO2 interlayer SiO2
IMEC, poly-Si gate IMEC, metal gate
Fig. 18. Electron mobility for HfO2 versus effective field Eeff and theSiO2 interfacial layer thickness. The mobility for pure SiO2 and theexperimental results55 are also reported.
HfO2. One of the most promising materials is La2O3, whichhas a very high dielectric constant while the simulatedmobility is comparable to the HfO2 mobility (see Table Iand Fig. 15). New studies are focusing on this material forthe next generation CMOS technology.57 58 For these rea-sons, we have extended the simulations of the impact of theSiO2 interfacial layer to the case of La2O3. These resultsare shown in Figure 20. The methodology is the same as
00.511.520
100
200
300
400
Mob
ility
(cm
2 /Vs)
IMEC, poly-Si gate
Interlayer thickness (nm)
IMEC, metal gate
HfO2 with SiO2 interlayer, eeff = 1000 kV/cmHfO2 with SiO2 interlayer, eeff = 1000 kV/cm
Fig. 19. Comparison between the simulated mobility and the experi-mental measures from Ref. [55] as a function of the interfacial layerthickness. The results are the same as for the upper panel, but only thehighest and the lowest simulated mobility are plotted, to show the agree-ment with the experimental results.
Interlayer thickness (nm)0
0.51
1.52
Eeff (kV/cm)
0200
400600
8001000
Mob
ility
(cm
2 /V
s)
100
200
300
400
500
La2 O3 with SiO2 interfacial layer SiO2
Fig. 20. Electron mobility for La2O3 versus effective field Eeff and theSiO2 interfacial layer thickness. The mobility for pure SiO2 is also shown.
that employed in the case of the HfO2 simulations and theresults show a similar trend. However, the gain in mobilitydue to the increased thickness of the SiO2 layer is quickerfor La2O3 compared to HfO2. The reason for this can betraced to the higher energy of the dominant �SO1 phononmode for La2O3 compared to HfO2. This leads on averageto a larger momentum transfer Q resulting in a faster decayof the scattering amplitude S(k k′) with the increasing dis-tance away from the interface (see Eq. (3)).
9. MOSFET SIMULATIONS WITH ANDWITHOUT HIGH-� DIELECTRICS
Strained Si (SSi) channel and high-� gate dielectrics haveboth been considered as performance boosters for CMOStechnology beyond the 90 nm technology node.1 Theperformance enhancement of sub-100 nm SSi MOSFETdevices comes from the strain induced mobility enhance-ment and reduced interface roughness (IR) scattering,59
and has successfully been demonstrated by a numberof players.60–64 Although the introduction of high-� gatedielectrics allows further EOT scaling that leads to signif-icant boost in transistor performance, additional gains canbe obtained by channel engineering, in particular, due tothe strain induced performance enhancement.
In this work we have studied, using Ensemble MonteCarlo (EMC) simulations, the impact of SO-phonon scat-tering on the performance of sub-100 nm conventionalSi and SSi n-MOSFETs arising from the use of HfO2
as a gate dielectric. This is a leading contender as areplacement oxide,7 being thermodynamically stable on Si
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and having conduction and valence band offsets65 66 suf-ficient to prevent significant over the barrier injection ofhot-carriers.
9.1. Simulation of Si and SSi MOSFETs with SiO2
The benchmark devices for our simulations are 80 nmgate length (67 nm effective channel length) conventionalSi and SSi n-MOSFETs with 2.2 nm SiO2 published byIBM67 and a 35 nm gate length n-MOSFET with 1.2 nmSiON published by Toshiba.68 The test devices were care-fully analysed using the commercial device simulatorsMEDICI and TAURUS69 to deduce the device structuresfrom published data. The reverse-engineered devices werethen simulated using our Poisson-EMC simulator. Apartfrom the conventional phonon and ionized impurity scat-tering models, the rough interface is treated using the non-perturbative model for interface roughness, as describedpreviously. Using the roughness parameters given above toreproduce the universal mobility curve in our EMC simu-lations we were able to reproduce the experimental charac-teristics of the IBM devices (see Fig. 21), confirming thata smoother SSi/SiO2 interface contributes to the observedperformance enhancement of SSi MOSFETs.
We have also simulated a 35 nm MOSFET publishedby Toshiba.68 This structure is likely to exhibit a degreeof process-induced strain. We have found that a strainequivalent to SSi (employing the IR parameters for Si)on a 5% Ge content SiGe buffer is necessary to repro-duce the experimental data,68 as shown in Figure 22. Alsoplotted are the simulated device characteristics for 35 nmdevices assuming differing amounts of strain within thechannel. A strained channel MOSFET with an equivalent20% Ge content buffer (employing the IR parameters forSSi) delivers ∼41% drive current enhancement over theoriginal design, in agreement with the recently observed45% drive current enhancement for a 35 nm Si/Si08Ge02
MOSFET.62
Fig. 21. ID–VG characteristics of the 80 nm gate length (67 nm effectivechannel length) Si and strained Si MOSFETs.
VD = 0.1 V, 0.85 V
MC, No strain, RMS/CL = 0.5/1.8
MC, 5% Ge equiv., RMS/CL = 0.5/1.8
MC, 20% Ge equiv., RMS/CL = 0.5/3.0MC, 15% Ge equiv., RMS/CL = 0.5/3.0
MC, 15% Ge equiv., RMS/CL = 0.5/1.8
MC, 10% Ge equiv., RMS/CL = 0.5/1.8
Taurus, with external res.Taurus, without external res.
Lg = 35 nmPermittivity = 4.75
I D (
A/m
icro
n)
VG–VT (V)
Fig. 22. ID–VG characteristics of 35 nm gate length Si and strained SiMOSFETs.
9.2. Simulation of Si and SSi MOSFETs withHigh-� Gate Stacks
The SiO2 used in the original simulations and design ofthe 80 nm and 35 nm devices was replaced by the high-�dielectric HfO2 with the same Equivalent Oxide Thick-ness (EOT) as in the original devices. This leads to thesame gate capacitance and provides almost identical elec-trostatic gate control for the devices with SiO2 and high-�gate stacks. However, in the presence of high-� dielectricsthe carriers within the inversion layer will be subject tosignificant SO phonon scattering, leading to a reductionin the vertical field dependence of the low-field mobil-ity within the channel of a MOSFET, employing a HfO2
gate oxide, as shown in Figure 14. Therefore a reduc-tion in device-drive current is to be expected when high-�dielectrics are introduced into such devices. In the simu-lations we have employed here we have assumed a ‘pure’high-� oxide layer neglecting the formation of an inter-facial layer. At present it appears that experimentally theformation of a thin interfacial layer (usually assumed tobe SiO2 like) is likely, if not unavoidable, during thegrowth/deposition/annealing of high-� dielectrics. The for-mation of the interfacial layer effectively increases theseparation of the high-� dielectric from the substrate, sothat the strong interaction with the low-energy SO phononmodes of the high-� dielectric is reduced, thus the result-ing mobility degradation might be slightly less than pre-dicted here.7
However, the introduction of an interfacial layer with alower-� value than the high-� material changes the totaleffective capacitance of the gate oxide. The minimumachievable equivalent oxide thickness will never be lessthan that of the lower-� interfacial layer. Therefore, theexpected increase in device performance due to the pres-ence of an interfacial layer over a ‘pure’ high-� dielec-tric is compromised by a reduction in the gate capacitanceintroduced by the interfacial layer and as such the presence
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I D (A
/mic
ron)
VG–VT (V)
No So scattering, VD = 0.1 V
So scattering, VD = 1.2 V
SO scattering, VD = 0.1 V
No So scattering, VD = 1.2 V
80 nm Si MOSFET (Leff = 67 nm)
with HfO2 EOT = 2.2 nm
Fig. 23. ID–VG characteristics with and without SO phonon scatteringof 80 nm conventional Si MOSFET with HfO2.
of an interfacial layer represents a significant restriction onthe equivalent oxide thickness that can be achieved.
Figures 23 and 24 show the simulated ID–VG character-istics for 80 nm Si and SSi MOSFETs respectively with a2.2 nm EOT HfO2. A drive current degradation, due to SOphonon scattering from the high-�, of around 40–50% atVD = 01 V and reducing to ∼25% at VD = 12 V at a gateover-drive (VG −VT = 10 V) is observed for both Si andSSi devices together with an increase of the device bal-listity. This may be attributed to the fact that SO phononscattering decreases at high-drain voltages. The carriers,on average, gain energy as they travel down the chan-nel from source to drain due to the potential slope, theamount of energy tending to increase as the drain biasis increased. Thus the carriers in the channel will tendto have higher kinetic energies at high-drain biases thanat low-drain biases, and in-turn will experience less SOphonon scattering, as the Fröhlich interaction decreaseswith increasing carrier energy (Eq. (3)).
80 nm strained Si MOSFET
with HfO2 EOT = 2.2 nm
(Leff = 67 nm)
I D (
A/m
icro
n)
VG–VT (V)
No SO scattering, VD = 0.1 V
No SO scattering, VD = 1.2 V
SO scattering, VD = 1.2 V
SO scattering, VD = 0.1 V
Fig. 24. ID–VG characteristics with and without SO phonon scatteringof 80 nm strained Si MOSFET with HfO2.
Lg = 80 nm, Leff = 67 nmVG–VT = 1.0 V
VD = 1.2 V
Strained Si, No SOStrained Si, SOConventional Si, No SO
Conventional Si, So
X-direction dimension (nm)
Ave
rage
cha
nnel
Vel
ocity
(10
7 cm
/s)
HfO2 EOT = 2.2 nm
Fig. 25. Average channel velocities with and without SO phonon scat-tering in 80 nm Si and SSi MOSFETs with HfO2.
In the high-� gate dielectrics the large static dielec-tric constant arises from the highly polarized ionic bonds,which lead to lower phonon energy and smaller opti-cal permittivity. Conventional SiO2 has the lowest staticdielectric constant, but significantly harder bonds and thushigher phonon energies, which result in the small effectof SO phonon scattering in SiO2 based devices. In thiscase we observe less than a 5% reduction in the drivecurrent when including SO phonon scattering in the sim-ulation of such devices. We also observe that the drivecurrent in the strained Si devices, with SO phonon scatter-ing due to the presence of high-� dielectric, is comparableto the drive current obtain in the conventional Si baseddevices. We can further examine this behaviour by com-paring the channel velocities in these devices. Figure 25compares the average channel velocities with and withoutSO phonon scattering, associated with a HfO2 dielectricat the same gate overdrive (VG −VT = 10 V) for both Siand SSi devices, indicating that the introduction of highmobility strained channels can be used to counteract the
L g = 35 nm, EOT HfO2 = 1 nm
I D (
A/m
icro
n)
VG –VT (V)
20 % Equiv. strain, no SO20% Equiv. strain, with SO15% Equiv. strain, no SO15% Equiv. strain, with SO
VD = 0.85 V
Fig. 26. ID–VG characteristics with and without SO phonon scatteringof 35 nm strained Si MOSFETs with HfO2.
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performance degradation due to SO phonon scattering indevices with high-� gate stacks.
Figure 26 illustrates the ID–VG characteristics for 35 nmSi MOSFETs assuming 15% and 20% Ge content equiv-alent strain with a HfO2 EOT corresponding to a 1.2 nmSiON. The drive current degradation due to SO phononscattering in the 35 nm devices is around 8%. The lessdetrimental impact of SO phonon scattering in this casemay be attributed to a reduction in the SO phonon scat-tering rate with increasing carrier energy as might beexpected in devices with shorter channels and furtherincrease in device ballistity. Therefore while hot carriereffects may be determinable for many reasons, they doreduce the impact of SO phonon scattering.
10. CONCLUSIONS
We have developed a model for the simulation of the struc-tural non-uniformity in high-� gate stacks which resultsboth from phase separation and random-grain orientationsof composite high-� gate dielectrics. We have shown thatthe spatial variation in dielectric constant throughout thegate stack will lead to noticeable parameter fluctuationsbetween devices.
The mobility degradation due to surface-SO phononscattering on channel mobility has been investigated usingMonte Carlo simulations, along with the effect of awide variety of high-� materials, including the leadingHf and La based gate stacks. A non-perturbative semi-classical model for interface roughness scattering has beendescribed and employed. It is clear that low-energy SOphonons considerably degrade the mobility when employ-ing high-� dielectrics. In the case of SixHf1−xO2 gatestacks we have studied the impact of the alloy compositionon mobility. We have also studied the impact on mobil-ity of the interfacial layer technologically present in HfO2
gate stacks. Good agreement with the available experi-mental data has been shown. The simulations clearly indi-cate the importance of an interfacial layer in improvingthe mobility. The quantitative information on the improve-ment in mobility with the increase of the interfacial layerthickness could allow engineers to optimise overall devicedesigns by balancing the associated performance improve-ments against the corresponding increase in equivalentoxide thickness.
For an 80 nm channel length MOSFET we observea significant drive current degradation of around 25% atVG − VT = 10 V and VD = 12 V in conventional andstrained Si devices with an HfO2 gate stack, comparedto SiO2 devices with an equivalent oxide thickness. Ourresults also indicate that the inherent mobility degradationassociated with the high-� gate stack MOSFETs might becompensated by the introduction of strained Si channels.There is also evidence that the increased carrier energyand ballistity in shorter devices may help to reduce the
degradation due to remote SO phonon scattering from thehigh-� gate stack due to the weaker Fröhlich interactionat higher energies. However, the infancy of high-� gatefabrication techniques means that other mobility degrad-ing scattering mechanisms, such as trapped charge andincreased front/back interface roughness will add to thedevice performance degradation.
Acknowledgments: The authors acknowledge the sup-port of EPSRC who supported some of this work throughGrant GR/S80097/01 “Meeting the materials challengesof nano-CMOS electronics,” and the European IntegratedProject PULLNANO. One of the authors (J. R. Watling)also acknowledges the support of EPSRC through anAdvanced Research Fellowship.
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Received: 2 August 2007. Accepted: 6 September 2007.
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