IMPLEMENTING RISC-V FOR IOT APPLICATIONS
Dan GanousisCodasip
Campbell, CA
Vijay SubramaniamMicrosemiAustin, TX
• Extensive experience required
• Significant capital required
• Manufacturing > 9 months
“The average IC design cost for a 28nm device is about $30 million, according to Gartner. In
comparison, the IC design cost for a mid-range 14nm SoC is about $80 million. “Add an extra 60% (to that cost) if embedded software development and mask
costs are included,” Gartner’s Wang said.”
• Consume too much power
• Prohibitively expensive product cost
• Little product differentiation is possible
Product Cost
Cost of
Design
Custom ICs
Systems-on-
Chip (SoCs)
Off-the-Shelf
Components
• Efficient performance/power
• Low cost, rapid manufacturing
• Mainstream tools & experience
IoT ASICs
SILICON IMPLEMENTATION FOR THE IOT
• Protection of your SW investment
• Eliminates IP vendor “lock-in”
• Enables a development community
• Custom extensions to instruction sets
✓ Less risk✓ Lower costs✓ Faster innovation✓ Better products The first Codasip RISC-V processor was
introduced in Nov. 2015
WHY IS RISC-V IMPORTANT FOR IOT?
THE FREE AND OPEN INSTRUCTION SET ARCHITECTURE
Codasip CodAL IP models
• Single description that generates RTL, virtual prototypes, verification, and SDK
• Easy to understand C-like language that models a rich set of processor capabilities
• Modifications and optimizations are automatically reflected in generated SDKs and RTL implementations
/* Multiply and accumulate, semantics dst += src1 * src2 */
element i_mac {
use reg as dst, src1, src2;
assembler { “mac” dst “,” src1 “,” src2 };
binary { OP_MAC:8 dst src1 src2 0:9 };
semantics {
rf[dst] += rf[src1] * rf[src2];
};
};
PROCESSOR IP AT A HIGH LEVEL OF ABSTRACTION
PROCESSOR IP AT A HIGH LEVEL OF ABSTRACTION
Integrated SW
programming and
debug
Application SW
profiling and
optimization
HDK SDKFPGA Dev
Board
CodAL Models
Fast, fully automated creation and
verification of HDKs and SDKs enables
processor IP optimization and design space
exploration
Codasip Studio
•Power
•Reliability
•Security
•Performance
•Time-to-market
•Cost
MICROSEMI: LEADING-EDGE SEMICONDUCTOR SOLUTIONS DIFFERENTIATED BY:
All these criteria can be improved by custom extensions to the RISC-V instruction set
EXISTING AUDIO PROCESSING FOR THE IOT
CHALLENGES IN MOVING INTO THE IOT• Low power requirements
• Low cost (desire to eliminate royalties)
• Creating derivative designs to meet diverse requirements
• Affordability (NRE/mask costs can be prohibitively high)
• Resource requirements can exceed manpower availability
• Time to market must be reduced (9 – 12 months design cycle)
• Performance improvement
• Example: FIR filter currently executes in 10 cycles/tap
• Custom DSP extensions can reduce MIPs and increase code density
which is desirable for IOT applications
PERFORMANCE IMPROVEMENT FOR FIR FILTER VIA DSP EXTENSIONS TO THE RISC-V ISA
CyclesThroughput Improveme
nt
Code size
(Bytes)
Area(Gates)
Area vs. RV32-ISpeedup vs. RV32-
IM
Area vs. RV32-
IM
Speedup vs.RV32-IM-p
Area vs. RV32-IM-
p
Base Config 1,764,256 232 16.0k - - - - -
Base + Serial Multiplier
427,561 4.12 x 148 19.7k 1.24x - - - -
Base + Parallel Multiplier
133,061 13.26 x 148 26.2k 1.64x 3.21x 1.32x - -
Base + DSP Instruction Extensions
31,371 56.24x 64 38.7k 2.43x 13.62x 1.96x 4.24x 1.48x
Fast, simple and accurate design space exploration… in a couple of days, not many months
AUTOMATED IP OPTIMIZATION AND VERIFICATION
Processor ModelingSoftware Analysis
SDK Synthesis HDK Synthesis Verification
IP Microarchitecture
Cycle Accurate
ModelsIP RTL ModelsCA Simulator, Profiler, Debugger
Embedded SW Application Programs
C/C++ Compiler
Assembler
Linker
IA Simulator, Profiler, DebuggerInstruction
Accurate Models
CodAL Models
RISC-V Instruction SetReference Models
UVM Verification
Extensions to the RISC-V instruction set architecture are an efficient method of meeting the needs of the IoT
• Fully automated high-level processor design flow and IP modeling allows for fast and accurate design exploration
• Performance improvement without the need to increase clock frequency or implement in expensive advanced process nodes
• Unique silicon security solutions can be easily implemented
• UVM verification methodology ensures RISC-V compliance
SOLUTION FOR MOVING INTO THE IOT