Improved methodology for modeling the
Parasitic Substrate PNP without access
to the substrate terminal
2006 HICUM Worskshop, Heilbronn, June 12-13, 2006
Franck Pourchon, Didier Céli and Christian Raya
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
limitations (CMRF 2005).
nd experimental results.
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Outline
❐ Introduction and motivation of this work.
❐ Substrate PNP: where is it located?
❐ Why Substrate PNP needs to be modeled?
❐ First proposal for parameters extraction and
❐ Improved method for parameters extraction a
❐ Conclusion.
Outline
ntroduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
irst methoddescription
mproved methoddescription
onclusion
1
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
rk (1/2) time DC+HF measurements.
ures are layouted, compatible
shorten Emitter and Substrateurrent!
(DC+HF structures for eachof measurements (DC+HF
ructures have to be used to
parasitic DC modeling will beme transistor!
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Motivation of this wo❒ Bipolar device modeling requires most of the
❒ For HF measurements dedicated test structwith HF coplanar probes:
❒ Common-Emitter configuration, HF probesterminal, no way to measure the substrate c
❒ To avoid the duplication of test structurestransistor geometries) and duplicationmeasurements), measurements on HF stmodel the parasitic PNP.
❒ In addition, it ensures that HF modeling anddone on measurements coming from the sa
SUB
IN OUT
SUB
DUT
utline
Introduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
irst methoddescription
mproved methoddescription
onclusion
2
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
rk (2/2)parasitic currents description!
extract these parameters.
ParasiticSubstrate PNP
N buried layer
sink
er w
ell
subs
tart
e w
ellemitter N+
IB1+IB2
EI
C1
RE
ITIB1S
QB1B2B2
B1
C2
IC1C2
RCX
IAVL
QTE
QTC
QBE
QBC
QE
QEPIIB1B2
IEX+ISUBQTEX
EXEX
+QEX +IB3
ISUBQTSSF
E C S
P substrate
MEXTRAM
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Motivation of this wo❒ All modern bipolar models include substrate
❒ A model independent method is proposed to
B E SC
buried layerN+
P substrate
sink
er w
ell
subs
trat
e w
ell
RCX
RE
QBE
QBC
RBI/qb
QBCX
IT
IBE
IBC-IGC
RBIP/qb
CI
CX
RBX
BX
ITS
IBEXQBEX
EI
BP
SI
QBCPIBCP
IBEP QBEP
RS
RCI
emitter N+
CBEO
CBCO
BI
QTES
RBX
+XIEX
XQT+XQ
XISUB
I
B
N buried layer
épitaxie N-si
nker
wel
l
subs
trat
e w
ell
RBX
emitter N+
IT
RE
IAVL
QBEI
QBCI
QDE
QDC
IBEI
IBCICRBI
RBIQBEP
QDS
IBEP
IBCX
IBET
CEOX
QBCX”QBCX’
ITS
RCX
RSU
CSU
ISCQCS
E’
B’
C’
B*
S’
EB C S
P substrate
VBIC
HICUM
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Introduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
irst methoddescription
mproved methoddescription
onclusion
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dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
n isolated
S
P+ ring
trate
N- Epi
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Substrate PNP in junctiotechnologies
CEB
PNP
NPN
Buried layer
SIC
P Subs
P+ ring
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ntroduction
Where is locatedthe SubstratePNP?
hy the SPNP needsto be modeled?
irst methoddescription
mproved methoddescription
onclusion
4
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
nch isolated
S
P+
bstrate
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Substrate PNP in deep-tretechnologies
CEB
PNP
NPN
Buried layer
SIC
P Su
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ntroduction
here is located theSubstrate PNP?
Why the SPNPneeds to be mo-deled?
irst methoddescription
mproved methoddescription
onclusion
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dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
to be modeled?ion mode:
-IS
UB [µ
A]
0
5
10
15
20
25
0 0.2 0.4 0.6 0.8 1
10-1110-1010 -910 -810 -710 -610 -510 -410 -310 -210 -110 +010 +110 +2
I C [m
A]
-IS
UB [µ
A]
VCE [V]
Output characteristics:(IC, ISUB) versus VCE
ISUB in log scale
ISUB in lin scale
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Why the Substrate PNP needs❒ The substrate current is triggered by saturat
0
5
10
15
20
25
0 0.2 0.4 0.6 0.8 10
50
100
150
200
250
300
350
I C [m
A]
VCE [V]
IB=40uAIB=80uA
IB=200uAIB=400uA
Output characteristics for low VCE:VB > VC the BC junction is forwarded=> the Substrate PNP is switched on!
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ntroduction
here is located theSubstrate PNP?
Why the S. PNPneeds to be mo-deled?
irst methoddescription
mproved methoddescription
onclusion
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dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
to be modeled?in the IC ramp-up in the output
0.8 1
PNP PNP
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Why the Substrate PNP needs❒ The substrate current impact could be seen
characteristics:
-10
-5
0
5
10
15
20
25
0 0.2 0.4 0.6
I C [m
A]
VCE [V]
with Substratewithout Substrate
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here is located theSubstrate PNP?
Why the S. PNPneeds to be mo-deled?
irst methoddescription
mproved methoddescription
onclusion
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dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Why the Substrate PNP needs❒ Forced gain characteristics:
IB=400µΑ
IC=400µΑ
IE= ??...
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ntroduction
here is located theSubstrate PNP?
Why the S. PNPneeds to be mo-deled?
irst methoddescription
mproved methoddescription
onclusion
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dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
to be modeled?
0
5
10
15
20
25
0 0.2 0.4 0.6 0.8 10
50
100
150
200
250
300
350
-IS
UB [µ
A]
VCE [V]
IB=400uA
IC
ISUB
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Device Modelling
June12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Why the Substrate PNP needs❒ Forced gain characteristics:
I C [m
A]
IB=400µΑ
IC=400µΑ
IE= 800µΑ
IS=280µΑ
IE= 520µΑ
S
IC=400µΑ
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ntroduction
here is located theSubstrate PNP?
Why the S. PNPneeds to be mo-deled?
irst methoddescription
mproved methoddescription
onclusion
9
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
on (1/3)
igh-injection effects.
r model (simple voltage controlledtion effects, series resistances, with a diode:
(1)
S
C
E
BIT
ICS
IBE
ITS
IBC
IBC
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
First method descripti❒ Common Emitter-Collector configuration:
❍ Low current: series resistances neglected, no h
❍ The Substrate PNP is modeled with first ordecurrent source without Early effects, high-injecetc...), the Collector-substrate junction is modeled
and
S C
E
B
E S
B
C
NPNPNP
NPN
ISCIT
IBC
IBE
ITS
IC IT IBC– ISC–= IB ITS IBE+ +=
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ntroduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
First methoddescription
mproved methoddescription
onclusion
0
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
on (2/3)
Substrate are grounded):
VBCVT
-----------
expVCSVT
-----------
exp–
VBE=VBC0
C
IBE
ITSF
IBC
S
C<0V VC=0V
➔ IB = IBC(VBC0)+IBE(VBE)+ITSF(VBC0
➔ IC = -IBC(VBC0)
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
First method descripti
❒ and
❒ Saturation mode VBC=VBC0>0 (Emitter and
IT ISVBEVT
-----------
expVBCVT
-----------
exp–
⋅= ITS ITSS
⋅=
VBE<VBC0VBE>VBC0
ITFIBE ITR
ITSF
IB
IC
VC>0V
VB>0V
V
➔ IB = IBE(VBE)
➔ IC = ITF(VBE)
➔ IB = IBC(VBC0)+ITSF(VBC0)
➔ IC = ITR(VBC0)-IBC(VBC0)-ICS
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ntroduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
First methoddescription
mproved methoddescription
onclusion
1
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
on (3/3)OS isolation ):
ment at VBC0 and VBC=0V:
)/exp(VBC0/VT)
=> ITSS=ITSF(VBC0)/exp(VBC0/VT)
.75 0.8
ITSS = 3.246aA
IBCS = 0.993aA
ITS
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
First method descripti❒ Practical case (0.35µm technology, with LOC
❒ Retrieving model parameters from measure
❍ IC(VBE=VBC0) = -IBC(VBC0) => IBCS = IBC(VBC0
❍ IB(VBE,VBC=0) = IBE(VBE)
❍ IB(VBE=VBC0)=IBC(VBC0)+IBE(VBE)+ITSF(VBC0)
10-10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3
0.4 0.45 0.5 0.55 0.6 0.65 0.7 0
I C, I
B [A
]
VBE [V]
IC
IB
IC=-IBC
VBE from 0.4V to 0.8V
VBC = 0.5V
IBE+
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ntroduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
First methoddescription
mproved methoddescription
onclusion
2
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
tionsis extremely low:
method):
measurement precision!
0.45 0.5 0.55 0.6 0.65 0.7VBE [V]
ICIB
IBE+ITS<0 !
0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8VBE [V]
ICIB
ector leakage!
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
First method limita❒ Measurement inacuracy if substrate current
❒ Measurement issues (independant from the
❒ The calculation of IBC is too sensitive to the
10-10
10 -9
10 -8
10 -7
10 -6
10 -5
0.4 0.45 0.5 0.55 0.6 0.65 0.7
I C, I
B [A
]
VBE [V]
ICIB
10-10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
0.4
I C, I
B [A
]IBE+ITS too small
10-10
10 -9
10 -8
10 -7
10 -6
10 -5
0.4 0.45 0.5 0.55 0.6 0.65 0.7
I C, I
B [A
]
VBE [V]
ICIB
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3
0.4
I C, I
B [A
]
shift in VBE! Coll
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ntroduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
First methoddescription
mproved methoddescription
onclusion
3
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
ption (1/3)
= IBC(VBC0)
(VBC0/VT)
) = ITR(VBC0)-IBC(VBC0)-ISC(VSC0)
VSC0/VT)
) = ITF(VBE)= -ITR(VBC0)
C0) and ITF(VBE=VBC0) are known
d ICS(VSC0=VBC0) are known
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Improved method descri❒ Saturation mode VBC=VBC0>0 and VBE=0V:
❍ IB(VBE=0,VBC=VBC0)
=> IBCS = IBC(VBC0)/exp
❍ IC(VBE=0,VBC=VBC0
=> ISC = ISC(VSC0)/exp(
❍ IC(VBE=VBC0,VBC=0
❒ To sum-up the measurement conditions:
❍ For VBC=0V :
➔ For VBE = VBC , IC and IB are measured: I BE(VBE=VB
❍ For VBC = VBC0 :
➔ For VBE = 0V, IC and IB are measured: I BC(VBC0) an
➔ For VBE = VBC , IB is measured: I TS(VBC0) is known
ITRIBC
ICS
VB=0V
VE=0V
VS=0V
VC<0V
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here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
irst methoddescription
Improved methoddescription
onclusion
4
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
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ption (2/3)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8VBE [V]
VCB=0.5VVCB=0.0V
0.13µm technologyth deep-trench isolation
2aA7aAfA
~IBC(VBC0)
~ITR(VBC0)
~ISC(VSC0)
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Improved method descri❒ Practical case:
10-12
10-11
10-10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3
0I C
, IB [A
]
10-12
10-11
10-10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
I C, I
B [A
]
VBE [V]
VCB=0.5VVCB=0.0V
HS wi
LC & HS 0.13µm technology without deep-trench
ITSS = 0.13aAIBCS = 0.52aAISCS = 1.2fA
ITSS = 0.0IBCS = 0.3ISCS = 0.2
utline
ntroduction
here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
irst methoddescription
Improved methoddescription
onclusion
5
dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
ption (3/3)vices with deep-trench:
0 40 50 60 70 80 90
urried layer Area [um2]
0.5 1 1.5 2 2.5 3 3.5Pactive/Aactive [1/um]
fit
small devices
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Improved method descri❒ Geometry scaling for 0.13µm technology de
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 10 20 3
I SC
S [f
A]
B
fit
0
0.02
0.04
0.06
0.08
0.1
0.12
0 0.5 1 1.5 2 2.5 3 3.5
I BC
S/A
activ
e [a
A/u
m2]
Pactive/Aactive [1/um]
fit
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0
I TS
S/A
activ
e [a
A/u
m2]
LE = from 2 to 15µm
WE = from 0.3 to 1.2µm
WE from 0.3 to 1.2µmLE=15µm and
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here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
irst methoddescription
Improved methoddescription
onclusion
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dm06.39Improved methodology for modeling the Parasitic Substrate PNP without access to the substrate terminal
RRaya
tract parasitic substrate PNPrameters using DC data fromner.
sfully to several technologies, scaling has been studied.
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Device ModellingJune12-13, 2006, Franck Pourchon, Didier Céli and Christian /17FTMCrolles
Conclusion
❒ Two methods have been developed to exmodel parameter and BC and SC diode paHF measurements in a straigth forward man
❒ These methods have been applied succesjunction isolated or deep-trench isolated and
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here is located theSubstrate PNP?
hy the SPNP needsto be modeled?
irst methoddescription
mproved methoddescription
Conclusion
7