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IN5240 Review: Mixers and Oscillators
Sumit Bagga* and Dag T. Wisland**
*Staff IC Design Engineer, Novelda AS**CTO, Novelda AS
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2 May 16, 2008
7.1 Mixers characteristics
Frequency conversion Frequency Conversion
• RF wanted signal is down-converted by a mixer i.e., multiplication with a local oscillator (LO), !"# in time domain
• Multiplication in time domain à convolution in frequency domain (shift of RF signal)
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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Image
Image is the unwanted signal that lies symmetrically to the RF signal of interest with respect to the !"#
[Liscidini, ISSCC, 2015]
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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Hartley Receiver
Spectrum of sine and cosine are asymmetrical à image
[Liscidini, ISSCC, 2015]
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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Noise Mixing
• Receive mixer down converts wanted and the image bands to IF frequency à folding of noise at image frequency on top of wanted band at IF, and is: – Noise at desired and image RF bands down converted à
IF – Added noise from mixer circuit
• If the mixer is noiseless, SSB NF is 3 dB because of the image noise folding
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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SSB and DSB Noise
• SSB NF assumes no signal at the image frequency except source noise• DSB NF assumes image band w/ noise and an image signal equal to
the wanted signal
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
RFThermal Noise
Δf
ωLO
Image
IFThermal Noise
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RF MixersPerformance Metrics
• Noise
• Linearity: P1dB, input inferred intercept points (IIP3, IIP2)
– OP1dB = IP1dB + (+ − 1)– IP1dB + 10.6 dB = IIP3
• Voltage conversion gain/loss
• Port-to-port isolation (LO-RF, RF-LO and LO-IF)
– Leakage from a port to another is undesirable
• Supply voltage
• Power dissipation
IN5240: Design of CMOS RF-Integrated Circuits,
Dag T. Wisland and Sumit Bagga
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Passive and Active Mixers
• Current and voltage mixers à transistors are switches• What is the ideal LO waveform?
– RF signal is multiplied by square wave not sinusoidal
IN5240: Design of CMOS RF-Integrated Circuits,
Dag T. Wisland and Sumit Bagga
EE215C B. Razavi Win. 13 HO #2
56
RF Mixers (I) General Considerations • Performance Parameters - Noise - Linearity: IP3, IP2 - Voltage Conversion Gain - Supply Voltage - Power Dissipation • Passive and active Mixers
• SSB and DSB Noise Figures
[Razavi, EE215C]
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Single and Double Balanced Mixers
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
EE215C B. Razavi Win. 13 HO #2
57
• Port-to-Port Isolation The leakage from each port to the other may degrade the performance: - LO-RF Feedthrough - RF-LO Feedthrough - LO-IF Feedthrough And all other combinations … • Single-Balanced and Double-Balanced Mixers
What is the ideal LO waveform?
[Razavi, EE215C]
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Passive Voltage Mixer
• Active devices (transistors) operate in triode• Large signals at input/output à difficult to completely
turn on/off transistorsIN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Liscidini, ISSCC, 2015]
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Passive Current Mixer
• Active devices (transistors) operate in triode• Low input impedance of transimpedance amplifier
input à small voltage swings at source/drain
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Liscidini, ISSCC, 2015]
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Active Current Mixer
• Transconductor stage à input voltage to current• Switches (transistors) operate in saturation (i.e.,
cascodes coupling/de-coupling RF to IF
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Liscidini, ISSCC, 2015]
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Mixer Comparison
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Liscidini, ISSCC, 2015]
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What is an Oscillator?
• Converts dc power à sinusoidal waveform• High-Q LC tank or a resonator (crystal, cavity, …)
– Lossy LC-tank à amplitude of the oscillator decays
• Oscillation frequency, power, phase noise/jitter, stability, tuning range
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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Oscillator Design
• Amplitude and frequency stability
• Concept of negative resistance
• Oscillator topologies (Colpitts, Hartley, Clapp,
Cross-coupled, …)
• Injection locked oscillators
– Locking range, injection pulling,
IN5240: Design of CMOS RF-Integrated Circuits,
Dag T. Wisland and Sumit Bagga
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Positive Feedback
• Oscillators à feedback systems• Fraction of the output signal is fed back to sustain
oscillations à ‘injected’ energy required to compensate for lossy tank
Feedback Perspective
vo
−vo
n
gmvin : 1
Many oscillators can be viewed as feedback systems.The oscillation is sustained by feeding back a fraction ofthe output signal, using an amplifier to gain the signal,and then injecting the energy back into the tank. Thetransistor “pushes” the LC tank with just about enoughenergy to compensate for the loss.
A.M. Niknejad University of California, Berkeley EECS 142 Lecture 21 p. 6/25 – p. 6/25
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Niknejad, EECS 242]
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Barkhausen’s CriterionLoop Gain ( !" )
• Magnitude of the product of open loop gain and the magnitude of the feedback factor of the amplifier is unity– !" = 1
• System poles are on jω-axis à constant amplitude oscillations– !" < 1à decay– !" > 1à amplitude increases exponential to steady-state
• Phase shift around the loop is 0 or integral multiples of 2)
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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ColpittsColpitts Osc
vx
ix
C1
C2
Connect a test current source as before. PerformingKCL
ix = gmv1 + (vx v1)jωC1
v1jωC ′
2 + (v1 vx)jωC1 + v1gπ + gmv1 = 0
Where C ′
2 = C2 + Cπ. Notice that Cµ can be absorbedinto the tank.
A.M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 6/28 – p. 6/28
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
Colpitts (cont)
Simplifying, we see that
v1
vx=
jωC1
jω(C1 + C ′
2) + gm + gπ
≈C1
C1 + C ′
2
=1
n
The above result follows directly from the capacitordivider. But notice that the assumption only holds whenthe capacitive susceptance dominates over thetransistor transconductance.Using the above result we have
Gx =ixvx
=gm
n+ jω
C1C ′
2
C1 + C ′
2
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 7/28 – p. 7/28
[Niknejad, EECS 142]
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Clapp
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Niknejad, EECS 142]
Clapp Oscillator
vx
ixC1
C2
Applying the same technique, note that
vπ ≈ ixZC1
vx = vπ + (ic + ix)ZC2
vx = ix(ZC1 + ZC2) + gmZC1ZC2ix
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 8/28 – p. 8/28
Clapp (cont)
The input impedance seen by the source is given by
Zx =vx
ix=
1
jωC1
+1
jωC2
+gm
jωC1jωC2
The negative resistance of the Clapp depends onfrequency
Rx = ℜ(Zx) =gm
ω2C1C2
Oscillation will occur if the negative resistancegenerated by the transistor is larger than the series lossin the tank
|Rx| > Rs
gm > Rsω2C1C2
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 9/28 – p. 9/28
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Single-MOS OscillatorsMOS Oscillators
Single transistor MOS oscillator topologies are identicalto the BJT versions shown last lecture. The large-signalproperties of the oscillator, though, differ significantlydue to the different current limiting mechanisms in MOStransistors.
A.M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 10/28 – p
[Niknejad, EECS 142]
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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Cross-Coupled Resistance
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Niknejad, EECS 142]Cross-Coupled Resistancevx
+
ix
M1 M2
id1 id2
Gx =ixvx
=gm
2
The above equivalent circuit can be used to find theimpedance of the cross-coupled pair.At high-frequency the device capacitance and inputresistance should be included in the analysis.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 13/28 – p
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Cross-Coupled Resistance
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Niknejad, EECS 142]
MOS Variations
PMOS devices have less 1/f noise and so a PMOScurrent source will mix less power into the fundamental.Using both PMOS and NMOS differential pairs canlower the current consumption of the oscillator
G′ = Gp + GnA. M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 17/28 – p
DC 1/f noise contributes to the 1/f3 region!
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VCO
Varactor: ‘p’ of the diode is connected to virtual ground
Varactor Tuned Diff Osc (cont)
Vc < Vdd
By reversing the diode con-nection, the “dirty” side ofthe PN junction is con-nected to a virtual ground.But this requires a controlvoltage Vc > Vdd. We canavoid this by using capaci-tors.
The resistors to ground simply provide a DC connectionto the varactor n terminals.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 24/28 – p
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
MOS Varactor (Inversion)
actu
al
VFB VT
Cox
For a quasi-static excitation, thermal generation leads tominority carrier generation. Thus the channel will invertfor VGB > VT and the capacitance will return to Cox.The transition around threshold is very rapid. If aMOSFET MOS-C structure is used (with source/drainjunctions), then minority carriers are injected from thejunctions and the high-frequency capacitance includesthe inversion transition.
A.M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 26/28 – p
[Niknejad, EECS 142]
Voltage-Controlled Osc
In most applications we need to tune the oscillator to aparticular frequency electronically.A voltage controlled oscillator (VCO) has a separate“control” input where the frequency of oscillation is afunction of the control signal Vc
The tuning range of the VCO is given by the range infrequency normalized to the average frequency
TR = 2fmax fmin
fmax + fmin
A typical VCO might have a tuning range of 20% 30%to cover a band of frequencies (over process andtemperature)
A.M. Niknejad University of California, Berkeley EECS 142 Lecture 23 p. 18/28 – p
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ILO
Ali M. Niknejad University of California, Berkeley Slide:
Injection Locking in LC Tanks
• Consider (a) a free-running oscillator consisting of an ideal positive feedback amplifier and an LC tank.
• Now suppose (b) we insert a phase shift in the loop. We know this will cause the oscillation frequency to (c) shift since the loop gain has to have exactly 2π phase shift (or multiples)
7
1416 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
Fig. 2. (a) Conceptual oscillator. (b) Frequency shift due to additional phaseshift. (c) Open-loop characteristics. (d) Frequency shift by injection.
shift), and the ideal inverting buffer follows the tank to create atotal phase shift of 360 around the feedback loop. What hap-pens if an additional phase shift is inserted in the loop, e.g., asdepicted in Fig. 2(b)? The circuit can no longer oscillate atbecause the total phase shift at this frequency deviates from 360by . Thus, as illustrated in Fig. 2(c), the oscillation frequencymust change to a new value such that the tank contributesenough phase shift to cancel the effect of . Note that, if thebuffer and contribute no phase shift, then the drain currentof must remain in phase with under all condi-tions.
Now suppose we attempt to produce by adding a sinu-soidal current to the drain current of [Fig. 2(d)]. If the am-plitude and frequency of are chosen properly, the circuit in-deed oscillates at rather than at and injection lockingoccurs. Under this condition, and must bear a phasedifference [Fig. 3(a)] because: 1) the tank contributes phase at
, rotating with respect to the resultant current,, and 2) still remains in phase with and hence out
of phase with respect to , requiring that form an anglewith . (If and were in phase, then would also bein phase with and thus with ). The angle formed be-tween and is such that becomes aligned with(and ) after experiencing the tank phase shift, , at .
In order to determine the lock range (the range of acrosswhich injection locking holds), we examine the phasor diagramof Fig. 3(a) as departs from . To match the increasinglygreater phase shift introduced by the tank, the angle between
and must also increase, requiring that rotate coun-terclockwise [Fig. 3(b)]. It can be shown that
(1)
(2)
Fig. 3. Phase difference between input and output for different values ofand .
which reaches a maximum of
(3)
if
(4)
Depicted in Fig. 3(c), these conditions translate to a 90 anglebetween the resultant and , implying that the phase differ-ence between the “input,” , and the output, , reaches amaximum of . To compute the value of cor-responding to this case, we first note that the phase shift of thetank in the vicinity of resonance is given by (Section III-A)
(5)
and recognize from Fig. 3(c) that and. It follows that
(6)
(This result is obtained in [3] using a different approach.) Wedenote this maximum difference by , with the understandingthat the overall lock range is in fact around .1
The dependence of the lock range upon the injection level,, is to be expected: if decreases, must form a greater
angle with so as to maintain the phase difference betweenand at [Fig. 3(d)]. Thus, the circuit moves closer to
the edge of the lock range.As a special case, if , then (2) reduces to
(7)
1We call the “one-sided” lock range.
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Source: [Razavi]
GmZT (�0) = gmR = 1
Gmej�0ZT (�1) = 1
Gmej�0 |ZT (�1)|e�j�0 = 1
�ZT (⇥1) = ��0
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
Ali M. Niknejad University of California, Berkeley Slide:
Locking Range
• At the edge of the lock range, the injected current is orthogonal to the tank current.
• The phase angle between the injected current and the oscillator is 90° + Φ0,max
• The lock range can be computed by noting that the tank phase shift is given by
12
�
�0
Iinj
Itank
Iosctan�0 =
2Q
⇥0(⇥0 � ⇥inj)
tan�0 =2Q
⇥0(⇥0 � ⇥inj) =
Iinj
Itank=
Iinj�I2osc � I2
inj
(�0 � �inj) =�0
2Q
Iinj
Iosc
1�1� I2
inj
I2osc
Maximum Locking Range
Ali M. Niknejad University of California, Berkeley Slide:
Phase Noise in Injection Locked Systems
• Under a lock, the phase of the oscillator follows the phase of the injection signal. If a “clean” signal is used to lock a VCO, then the phase noise would improve up to the locking range.
• At the edge of the lock, the injected signal cannot correct for the phase noise since it injects energy at a 90° phase offset, where the signal has a peak amplitude
18
1422 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
As illustrated in Fig. 12(b), if the input frequency deviatesfrom , the resulting phase noise reduction becomes less pro-nounced. In fact, as approaches either edge of the lockrange, drops to zero, raising the impedance seen bythe noise current.
In CMOS technology, it is difficult to rely on the phase noisereduction property of injection locking. Since the lock range istypically quite narrow and since the natural frequency of oscil-lators incurs significant error due to process variations and poormodeling, the locking may occur near the edge of the lock range,thereby lowering the phase noise only slightly. For example, ifthe two-sided lock range is equal to % and the natural fre-quency of the oscillator varies by % with process and tem-perature, then, in the worst case, the injection locking occurs at
. It follows from (37) and the above obser-vations that the impedance seen by the noise falls from infinityto , yielding a 4.4-dB degradation in the phasenoise compared to the case of .
VI. INJECTION PULLING IN PHASE-LOCKED OSCILLATORS
The analysis in Section III deals with pulling in nominallyfree-running oscillators, a rare case of practical interest. Sinceoscillators are usually phase-locked, the analysis must accountfor the correction poduced by the PLL. In this section, we as-sume the oscillator is pulled by a component at while phase-locked so as to operate at . We also assume that the oscillatorcontrol has a gain of and contains a small perturbation,
, around a dc level.Examining the derivations in Section III for a VCO, we ob-
serve that (19) and (21) remain unchanged. In (22), on the otherhand, we must now add to . For small pertur-bations, can be neglected in the denominator of
and
(41)
Equating the phase of (41) to and noting that (24) and(26) can be shown to still hold, we have
(42)
Fig. 15 shows a PLL consisting of a phase/frequency detector(PFD), a charge pump (CP), and a low-pass filter ( and ),and the VCO under injection. Since with a low injection level,the PLL remains phase-locked to , it is more meaningful toexpress the output phase as rather than . Thus,
and
(43)
(44)
where it is assumed radian. This approximation is rea-sonable if pulling does not excessively corrupt the PLL output.
Fig. 14. Reduction of phase noise due to injection locking.
Fig. 15. PLL under injection pulling.
The above result can now be used in a PLL environment. InFig. 15, the PFD, CP, and loop filter collectively provide thefollowing transfer function:
(45)
where the negative sign accounts for phase subtraction by thePFD. We therefore have
(46)
Substituting for in (44) and differentiating both sides withrespect to time, we obtain
(47)
where . This reveals that the PLL behavesas a second-order system in its response to injection pulling.Defining
(48)
(49)
we have
(50)
where denotes the phase of the transfer function at a frequencyof .5
5A dual-loop model developed by A. Mirzaei arrives at a similar result butwith a different value for the peak amplitude of the cosine [17].
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[Niknejad, EECS 142]
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Phase Noise
• Phase noise spectral density (PN) units à dBc/Hz and measured at ∆" from the "#
• Low spectral purity à convolution of blocker (∆") & "$% à noise contribution in RF BW (reciprocal mixing)
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
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Harmonics à Phase Noise
IN5240: Design of CMOS RF-Integrated Circuits, Dag T. Wisland and Sumit Bagga
[Niknejad, EECS 142]
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Key References
1. A. M. Niknejad, EECS 142, 242 and 105
2. A. Liscidini, “Fundamentals of Modern RF
Receivers,” ISSCC 2015
3. E. Kim, EEE 194
4. B. Razavi, EE215C
IN5240: Design of CMOS RF-Integrated
Circuits, Dag T. Wisland and Sumit Bagga