1 EXPERIMENT 01 RTL Circuits Objectives 1. Examine the RTL characteristics. 2. Familiarize with the internal working of the RTL circuits. 3. Design and analyze an RTL inverter and determine its input-output characteristics, Propagation delay, and noise margins. Required Equipments • Oscilloscope • Power supply • Function generator • Digital Multimeter • Bread-Board o Protoboard Required Parts list • 10 KΩ ¼-watt resistor. • 0.1 μF capacitor • 470 Ω ¼-watt resistor. • 2N2222 NPN silicon transistor, or equivalent • 1N4001 Diode semiconductor Background Resistor-Transistor Logic (RTL) refers to the obsolete technology for designing and fabricating digital circuits that employ logic gates consisting of nothing but transistors and resistors. RTL gates are now seldom used, if at all, in modern digital electronics design because it has several drawbacks, such as bulkiness, low speed, limited fan-out, and poor noise margin. A basic understanding of what RTL is, however, would be helpful to any engineer who wishes to get familiarized with TTL, which for the past many years has become widely used in digital devices such as logic gates, latches, buffers, counters, and the like. Basically, RTL replaces the diode switch with a transistor switch. If a +5V signal (logic 1) is applied to the base of the transistor (through an appropriate resistor to limit base-emitter forward voltage and current), the transistor turns fully on and grounds the output signal. The output signal rise to +5 volts if the input is grounded (logic 0), the transistor is off. In this way, the transistor does invert the logic sense of the signal, but it
Transcript
1
EXPERIMENT 01 RTL Circuits Objectives
1. Examine the RTL characteristics. 2. Familiarize with the internal working of the RTL circuits. 3. Design and analyze an RTL inverter and determine its input-output
characteristics, Propagation delay, and noise margins. Required Equipments
• Oscilloscope • Power supply • Function generator • Digital Multimeter • Bread-Board o Protoboard
Resistor-Transistor Logic (RTL) refers to the obsolete technology for designing and fabricating digital circuits that employ logic gates consisting of nothing but transistors and resistors. RTL gates are now seldom used, if at all, in modern digital electronics design because it has several drawbacks, such as bulkiness, low speed, limited fan-out, and poor noise margin. A basic understanding of what RTL is, however, would be helpful to any engineer who wishes to get familiarized with TTL, which for the past many years has become widely used in digital devices such as logic gates, latches, buffers, counters, and the like.
Basically, RTL replaces the diode switch with a transistor switch. If a +5V signal (logic 1) is applied to the base of the transistor (through an appropriate resistor to limit base-emitter forward voltage and current), the transistor turns fully on and grounds the output signal. The output signal rise to +5 volts if the input is grounded (logic 0), the transistor is off. In this way, the transistor does invert the logic sense of the signal, but it
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current begins to flow in the transistor, the output voltage begins its decline. As the input voltage increases, the base current increases, the collector current increases, and the collector-to-emitter voltage decreases. The operation in the active region continues until the collector-to-emitter voltage becomes equal to its saturation voltage. The transistor is now at the verge of saturation. The collector current is 10.21 mA. If β = 100, the base current is 0.1021 mA. Let us denote the input voltage that forces the transistor to enter the saturation region as VIH. Note that VIH is the minimum value of the high-input voltage and is given as
If we denote the corresponding low output voltage as VOL, then VOL = VCE(sat) = 0.2 V. These voltages are also shown in Figure 2. As the input voltage increases above 1.82 V, the output remains at 0.2 V and the transistor goes into deep saturation. The operation in the deep saturation region continues until the input voltage reaches its maximum value. SUMMARY: In the above discussion we have defined some terminology pertaining to the RTL circuit. We will use this terminology for all types of gates. Therefore, let us formally define it. Voltage Transfer Characteristic VOH = Nominal High Output Voltage This is the output voltage that corresponds to logic 1 (high) and it may vary with the loading and temperature. The manufacturers usually specify its minimum value in order to compensate for the component tolerances and variations in the loading conditions. VOL = Nominal Low Output Voltage This is the gate output voltage that corresponds to logic 0 (low). The manufacturers usually specify its maximum value. VIH = High input voltage at which |dvo/dt| = 1 The minimum input voltage that is interpreted as logic 1 (high) by the gate. VIL = Low input voltage at which |dvo/dt| = 0 The maximum input voltage that is interpreted as logic 0 (low) by the gate. Transition Region: The region between VIL and VIH is called the transition region.
Transition region is mostly the active region and it is the forbidden region for the logic circuit. The input voltage should either be low (less than or equal to VIL) or high (greater than or equal to VIH). If there is a random noise in the system, it should be small enough such that it does not drive the transistor into the forbidden region. Transition Width: It is the difference between the two input voltages (VIH – VIL). For RTL gate, the transition width is 1.22 V.
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Logic Swing: The difference between the two output voltages (VOH – VOL) is designated as the logic swing. For the RTL under discussion, the logic swing is 4.8 V. Noise Margins
The input signal to a gain can be corrupted by some unwanted and unexpected signal. If the gate is not properly designed the unwanted signal can force the gate to malfunction. A noise margin is the figure of merit for the gate. If the noise margin is high the gate is less susceptible to malfunction. We define the noise margin for each level of the input signal. Thus, we have the definitions for the lower- and upper-noise margins for the low- and high-level of the input signal. These margins are defined as follows: The Lower Noise Margin: NML = VIL – VOL
By definition, it is the difference between the maximum allowed input voltage that can be interpreted as low by the gate and the actual low output voltage of the preceding stage driving the gate. For the RTL circuit we just analyzed, the maximum input voltage that can be interpreted by the gate as low is 0.6 V. The gate usually receives the input signal from the other gate whose minimum output is 0.2 V. Then the lower noise margin is 0.4V=(0.6V – 0.2V). Keep in mind that each gate generates a random noise voltage, however small it may be. For the RTL gate under discussion, the largest random noise voltage that can corrupt the low input signal is 0.4 V. The reason, of course, is that when the random noise voltage is added to the input voltage, the total voltage should be less than or equal to the maximum input voltage that is interpreted as low by the gate. Since the actual input signal voltage is 0.2 V, the maximum input voltage that can be added to it is 0.4 V, which is simply the lower noise margin. The Upper Noise Margin: NMH = VOH – VIH
By definition, it is the difference between the actual output voltage of the preceding stage driving the gate and the minimum value of the input voltage that can be interpreted as high by the gate. For the RTL gate under discussion, the maximum input voltage is VBB=5 V. The minimum input voltage that the gate can interpret as high is 1.82 V. Then, the upper noise margin is 3.18 V = (5V – 1.82V). This simply means that the largest random noise voltage that the gate can tolerate is 3.18 V. The logic circuit should still be able to interpret the input voltage as high when the upper noise margin is subtracted from the input signal. All our discussion pertains to a single RTL circuit. When it is used as a driver for other gates, its noise margins are bound to change, as we will show later.
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Dynamic Response of Logic Gates
An important figure of merit to describe logic gates is their response in the time domain.
The rise and fall times, tf and tr, are measured at the 10% and 90% points on the
transitions between the two states as shown by the following expressions:
V10% = VL + 0.1ΔV
V90% = VL + 0.9ΔV = VH – 0.1ΔV
Where ΔV = VH – VL. Rise and fall times usually have unequal values; the characteristic shapes of the input and the output waveforms also differ. Propagation Delay
• Propagation delay describes the amount of time between a change at the 50% point input to cause a change at the 50% point of the output described by the following:
2LH
50%VVV +
=
7
• The high-to-low propagation delay, τPHL, and the low-to-high propagation delay, τPLH, are usually not equal, but can be described as an average value:
2PHLPLH
Pττ
τ+
=
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Pre – Laboratory RTL Inverter Propagation Delay
In this laboratory the concept of propagation delay is addressed for the RTL inverter using PSPICE to simulate Transient behavior. The RTL inverter circuit is shown in Figure 5.
Figure 5: RTL Inverter Schematic Circuit
Circuit description and specific parameters
The input voltage vin is a PULSE waveform with an amplitude of 5V, the rise time
(TR) and fall time (TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of
200 NS and a period (PER) of approximately 500 NS.
The transistor used in all simulations will be a 2N2222 with the following model
parameters for both Netlist and Schematic circuit.
.MODEL parameters for the npn transistor are:
IS=1E-14 A, BF=50, VAF=80 V, TF=0.45NS, TR=5NS, CJE=7.6PF, CJC=3PF, RB=13,
RC=6.2
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Pre – Laboratory Procedure
1. Use PSPICE1 to get the transient response for the circuit shown in Figure 5.
2. Plot both Vin and VCE as outputs superimposed on the same plot.
3. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the
report's questions.
4. Determine τPHL and τPLH for the simulation and record the values in the report's
questions.
5. Print the plot.
Pre – Laboratory Report
1. What are the values for :
VIL = _____ VIH = _____ VOL = _____ VOH = _____
2. Calculate τPLH and τPHL for the simulation.
τPLH = __________________ τPHL = _________
3. What is the propagation delay of the gate? τP = _________
1 First become familiar with the MicroSim PSPICE software installed on the PC Lab (INCADEL or
CRAY). Refer to the manual for PSPICE for getting started in the construction of a circuit, adding
Specific Parameters for Transient Analysis and for other tips for plots or visit
https://ece.uprm.edu/seminarios/.
LabRTL
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11
Laboratory Report
Table 1
DC Parameters
Measured Valued
Vin = 0V
Measured Valued
Vin = 5V IC
IB
VC
VBC
VBE
VCE
Graphic 1
12
1. Record the values of VS corresponding to the VC values given below from the
transfer curve displayed on the oscilloscope.
VC = 4V Vin =______V.
VC = 3V Vin =______V.
VC = 2V Vin =______V.
2. What are the values for :
VIL = _____ VIH = _____
VOL = _____ VOH = _____
3. What are the noise margins for the Gate?
NMH = ____________
NML = ____________
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EXPERIMENT 02 7400 Standard NAND Gate: Transient Analysis and Voltage Transfer Characteristic. Objectives
4. Examine the TTL characteristics. 5. Familiarize with electrical properties of logic gates built from bipolar transistors
(TTL). 6. Build and test logic gate networks for measure its voltage transfer characteristics,
Propagation delay, Fan-Out, and power dissipation of the 7400 TTL NAND. Required Equipments
• Oscilloscope • Power supply • Function generator • Digital Multimeter • Bread-Board o Protoboard
Now that we have studied the characteristics of the saturating transistor inverter, we have the knowledge in place to understand the behavior of the transistor-transistor logic or TTL. For years, TTL has been a workhorse technology for implementing digital functions and for providing “glue logic” necessary in microprocessor system design. TTL is interesting from another point of view since it is the only circuit that we shall encounter that makes use of transistors operating in all four regions of operation—forward-active, inverse-active, saturation, and cutoff.
The classical TTL inverter shown in Figure 1 solves is the typically circuit found in TTL unit logic in which several identical gates are packaged together in a single dual-in-line package, or DIP. Transistor Q1 controls the supply of base current to Q2. Input voltage Vi causes the current iB1 to switch between either the base-emitter diode or the base-collector diode of Q1. Q2 forces the output low to VCESAT2. The load resistor is an
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active pull-up circuit formed by transistor Q4 and diode D1. Q3 and D1 are required to ensure that Q4 is turned off when Q2 is turned on and vice versa.
Figure 1 A complete standard Two-input TTL NAND gate is shown in the schematic in
Figure 2. If any one of the two input emitters is low, then the base current to transistor Q3 will be zero and the output will be high, yielding Y = AB .
15
Figure 2
In this lab, you will know the electrical properties of logic gates built from bipolar transistors (TTL) Power Dissipation
Power dissipation is the power lost in the transistors of a logic gate. Since modern integrated circuits involve millions of transistors, it is important to minimize this power loss (the very first Pentium CPU had 3.2 million transistors).
y measuring the input characteristics and the transfer characteristics of all the chips, we can assess the power loss of each chip. The current flowing into a gate at any point is a good indication of power dissipation. To assess the amount of power dissipated by a gate at a specific state, we simply measure the current flowing into the gate at that state. A comparison of the output voltage to the input voltage during a change in state of a logic gate can provide information on how much power is lost as the gate switches. In the plot of output voltage versus input voltage, the slope indicates the amount of power dissipation. A steeper slope indicates smaller power dissipation. Pre-Laboratory Procedure
Perform the following simulations for the 7400 TTL NAND of the Figure 2. 1. DC transfer characteristics: Use the DC command to step Vin from 0 to 5V in
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0.1V increments. Obtain the plot of the DC transfer curve Vout versus Vin using PROBE.
2. Transient response: Carry out a transient simulation and obtain the plot of Vin and Vout using PROBE. Use Vin as a PULSE waveform with an amplitude of 5 Volts, rise and fall times equal to 2 NS and delay time equal to 0 NS, set the pulse duration for 50 NS and pulse period for 100 NS.
Pre-Laboratory Report
1. For the 7400 TTL NAND gate, determine VIH, VOH, VIL, VOL and the break points from the DC simulations.
2. From the transient simulations, determine τPHL and τPLH and calculate the average
propagation delays for TTL NAND gate. 3. Calculate the average power dissipation for the circuit.
Laboratory Procedure Part A: Electric Characteristics
1. Assemble the circuit in Figure 3 using the 7400. a. Mount the 7400 (TTL) carefully and firmly with the pins in the center rows of
your breadboard. Connect the 5-volt DC supply to VCC and connect ground to GND of the 7400.
b. Connect pin 1 to the +5V supply via the 1kΩ resistor, connect pin 2 to one of
the probes of the digital Multimeter (DMM), and leave the other probe unconnected. Use the DMM to measure the input current when the second probe is connected to +5V via the 1kΩ resistor (pin 2 is pulled high), and when the second probe is connect to ground via the 510Ω resistor (pin 2 is pulled low). Use the DMM to measure the output voltage at pin 3 as the input voltage is changed. Record the readings, indicating the polarities, in the Table 1 of the report.
c. Remove the 7400, and replace it with the 74LS00 and repeat step a and b. You
can use the same circuit configuration because the pin locations for all two chips are exactly the same.
234
5
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20
Laboratory Report
Table 1 V-I Characteristic 7400 74LS00
Input current when pin 2 is high Output voltage when pin 2 is high Input current when pin 2 is low Output voltage when pin 2 is low
Table 2 Voltage Characteristics
vi 7400
vO 74LS00
vO 0V
2V 4V 6V 8V
10V
Graphic 1(7400 and 74LS00)
21
1. From the input current values that were measured in Part A-1, which is the power dissipation for both chips? Explain your reasoning.
2. Using the table of measured values that you obtained in Part A-4 plot VO versus Vi for the 7400 and 74LS00 in different colors.
3. Refer to the data sheet of the DM7400 to obtain the value of VIH. VIH is the
Manufacturer’s minimum level for an input 1. On the graph you just plotted, draw a vertical line at Vi =VIH. Does the chip operate within this specification? Explain your reasoning. You may want to look at the typical values for VOH and VOL.
22
4. From the data sheet of the DM7400, find the value of VIL. This is the
manufacturer’s maximum level for and input 0. On the graph of the previous page, draw a vertical line at Vi = VIL. Does the chip operate within this specification? Explain your reasoning.
5. Compare the static and dynamic measurements of the transfer characteristics for the 7400 and explain your conclusions.
Graphic 2(7400 and 74LS00)
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Graphic 3(7400 and 74LS00)
6. What are the noise margins (NML and NMH) for a fan-out of 2 and 6 for both
chips?
7. How much is average power dissipation in both chips?
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EXPERIMENT 03 Analysis of a Schottky RTL inverter Objectives
7. Examine the Schottky RTL characteristics. 8. Familiarize with the internal working of the Schottky RTL circuits. 9. Design and analyze a Schottky RTL inverter and determine its input-output characteristics,
Propagation delay, and noise margins. Required Equipments
• Oscilloscope • Power supply • Function generator • Digital Multimeter • Bread-Board o Protoboard
A serious problem that severely limits the switching speed of BJT inverter is the amount of time required to remove the enormous stored charge from the base of a saturated BJT. The Schottky-clamped transistor drawn in figure 1 was developed to solve this problem. The Schottky-clamped transistor consists of a metal semiconductor Schottky barrier diode (SBD) in parallel with the collector-base junction of the bipolar transistor.
When conducting, the forward voltage drop of the Schottky diode is designed to be approximately
0.30 to 0.45 V, so it will turn on before the collector-base diode of the bipolar transistor becomes strongly forward-biased. Referring to Figure 1, we see that
vCE = vBE − vSBD = 0.70V − 0.30V = 0.4 V
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Figure 1: Schottky-clamped transistor.
If the input current in increased, the SBD will begin to conduct at VSBD(ON) =
0.3V. Hence, the base-collector junction reaches the forward-bias of VBC = 0.3V. Any further increase in current i’
B entering this configuration will be diverted from the base of the BJT, though the SBD, and turn into the collector of the BJT. Thus, VBC is limited to VSBD(ON) = VBC(HARD)= 0.3V. This BJT – SBD combination is called a Schottky-clamped BJT (SBJT) or Schottky transistor and the BJT cannot operate in saturation. Hence, the time consuming saturation stored-charge removal (and insertion) for the base is eliminated.
The mode of operation where the BJT is forward active and the Schottky diode is conducting is referred to as the “on hard” mode. This mode is similar to saturation with VBE increased to 0.8V, except VBC is only forward biased to 0.3V. An SBJT inverter is shown in Figure 2.
Figure 2: Schottky RTL inverter
Invention of this circuit required a good understanding of the exponential dependence of the BJT collector current on base-emitter voltage as well as knowledge of the differences between Schottky and PN junction diodes. Successful manufacture of the circuit relies on tight process control to maintain the desired difference between the forward drops of the base-emitter and Schottky diodes.
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Pre – Laboratory Schottky RTL Inverter Propagation Delay
In this laboratory the concept of propagation delay is addressed for the Schottky RTL inverter using PSPICE to simulate Transient behavior. The Schottky RTL inverter circuit is shown in Figure 3.
Figure 3: Schottky RTL Inverter
Circuit description and specific parameters
The input voltage VS is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time
(TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of 200 NS and a period (PER) of
approximately 500 NS. The transistor used in all simulations will be a 2N2222. Pre – Laboratory Procedure
6. Use PSPICE to get the transient response for the circuit shown in Figure 3.
7. Plot both vin and vOUT as outputs superimposed on the same plot.
8. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's
questions.
27
9. Determine τPHL and τPLH for the simulation and record the values in the report's questions.
10. Print the plot.
Pre – Laboratory Report
4. What are the values for :
VIL = _____ VIH = _____ VOL = _____ VOH = _____
5. Calculate τPLH and τPHL for the simulation.
τPLH = __________________ τPHL = _________
6. What is the propagation delay of the gate?
τP = _________
Laboratory Procedure Schottky RTL Inverter Voltage Transfer Characteristic
8. Wire the circuit shown in Figure 4, the input voltage VS = 0V.
9. With your Multimeter, measure the base-emitter, base-collector, collector-emitter, and collector
DC voltages, with respect to ground, and measure the DC currents and record your values in table
1 of the report.
10. Set the input voltage at 5V and repeat the step 2.
11. Use the Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at
0.5 Volts/division.
12. Adjust the X zero reference to the screen center and the Y reference below the center.
28
Figure 4
13. Wire the circuit shown in Figure 5.
14. The input vS is a sine wave from a function generator with a peak amplitude of 5 Volts and
frequency of 100 Hertz.
15. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 1(Indicate
the scales that were used) of the report and ask the question.
16. Determine VIL, VIH, VOL, and VOH for the VTC displayed on the oscilloscope and record the values
in the report's questions.
Figure 5
29
Laboratory Report Table 1
DC Parameters
Measured Valued
Vs = 0V
Measured Valued
Vs = 5V VC
VBC
VBE
VCE
I’B
IB
ISBD
I’C
IC
Graphic 1
30
4. Record the values of VS corresponding to the VC values given below from the transfer curve
displayed on the oscilloscope.
VC = 4V VS =______V.
VC = 3V VS =______V.
VC = 2V VS =______V.
5. What are the values for :
VIL = _____ VIH = _____
VOL = _____ VOH = _____
6. What are the noise margins for the Gate?
NMH = ____________
NML = ____________
7. Compare this experiment’s results with experiment one’s result.
A MOSFEion in the samalized NMOS device may be er, but in an e for a load is er is applied d
ge is equal to th
No input rnt since the gtially Zero. The
Note that e 1 can be dirt as follows
VL =
Also, since gh the channel
NT 04
ter
analyze an NMthe voltage trand measure the
uipments
pe ply enerator ltimeter rd o Protoboard
ts list
watt Potentiomeacitor.
ET can be ume fashion as
inverter is sha resistor, likactual MOS
another MOSdirectly to the he gate to sourc
VIN =
resistor is neegate current Ie output is take
VOUT =
the voltage V
rectly expresse
VL(VOUT) = V
the input currof the MOSFE
MOS Inverter.ansfer charactee propagation d
d
eter
used to achiethe BJT inve
hown in Figurke that used inFET inverter
SFET. The inpugate. Hence,
ce voltage VGS
ded to limit tIG of a MOen at the drain,
= VDS
VL across the ed as a functio
VDD - VOUT
ent is negligibET
eristic (VTC) odelays of the N
ve logic erter. The re 1. The n the BJT
a better ut to this the input
the input SFET is and thus
load in on of the
le, the current
IL = ID
of NMOS inverNMOS inverter
though the loa
rter .
ad is equal to t
3
the drain curren
31
nt
used to
of the RL. Fdrain c
only aoperatoutputwith th
reduceThe V
These relatio determine th
Figure 2 shN-channel ou
or VIN < VT, Ncurrent, with V
As the inpua small current ting in the satut voltage continhe resistor curr
or
Substituting
Solving for
As VIN is fue the drain vol
VTC of the resis
ions between the VTC and pow
hows the NMOutput transistor NO is cutoff andVIN < VT, IRL = I
ut in increased flows and the
uration region. Wnues to fall. Thrent to obtain
g VGS = VIN an
VOUT, we have
urther increasetage such that stor loaded NM
he voltages andwer dissipation
S inverter withNO and VIN= V
d does not condID (OFF) = 0 an
slightly above drain voltage iWith further inhe analytical fo
( GSVk2
nd VDS = VOUT y
( INVk2
e
OUTV −=
ed, ID increasesVDS ≤ VGS –
MOS inverter h
d currents of thn for NMOS.
h resistive loadVGS. The outpuduct drain currnd the output i
the threshold is slightly less ncrease of the iorm of the VTC
ID (sat) =IR
)TSV
V =− 2
yields
) DTN
VV =− 2
( INL VkR
−−2
s and the voltaVT. Under thi
has the form sh
he inverting NM
d, RL. The inpuut is at the drarent. Since the is VOUT = VDD.
voltage, NO bethan VDD. As
input, a larger C can be found
RL
L
DSDD
RVV −
L
OUTDD
RV−
) DDT VV +− 2
age drop acrosss condition NO
hown in Figure
MOS and the l
ut to the invertain and VOUT =
resistor curren
egins to conduclong as VDS ≥ drain current c
d by equating t
s RL can becoO operates in th3.
3
oad device are
ter is at the ga= VDS = VDD -nt is equal to th
ct. At this poinVGS – VT NO
conducts and ththe drain curren
ome sufficient the linear region
32
e
ate IL he
nt, is
he nt
to n.
33
Propagation Delay
MOS logic families have the lowest power dissipation per gate of any of the logic families. This is because of the large values of MOSFET resistance and consequently small current levels.
An NMOS gate dissipates power in the same manner form as the BJT gates. That is, the power
dissipated is given by the product of the power supply voltage and average current for a NMOS inverter
2)()( OLIOHIVP DDDD
DDDD+
=
Significant additional power dissipation also occurs for NMOS families driving switching from
one logic state to another. An expression for the MOS power dissipation during transient switching, called the dynamic power dissipation, is given by
2DDLD vVCP =
where CL is the total capacitance at the output of the gate and v is the frequency at which the gate is switched.
Since the gate terminal is always an input terminal and the gate sinks zero current for all input voltages fan-out for MOS families is unlimited. This is true for all load devices including a P-channel MOSFET as is the case for the CMOS inverter. Thus, the fan-out based upon current limitations is infinite for all NMOS gates. The maximum fan-out is restricted, however, by the maximum propagation delay tolerable. Resistor Loaded NMOS Inverter Dynamic Response
The total gd NMOS inveror high-to-lowion of the inpu
CapacitanceS Inverter
When oneer drives others, the inputer must betaneously. A lod NMOS invert
The dynamd NMOS inverapacitance load
nce is present btance and can bce.
gate capacitancrter. When the
w, this input (gt change.
e on a Res
e resistor loher resistor lt capacitance e charged oad capacitancter is shown in
mic response rter is determind.
between every be evaluated a
ce is the inputinput logic stagate) capacitan
sistor Loaded
oaded NMOSloaded NMOS
of each loador discharge
ce on a resiston Figure 4.
of a resistoned considering
pair of terminas the approxim
t capacitanceate to a resistornce must be
d
S S d e r
r g
nals for a MOSmated sum of th
between the gr loaded NMOcharge or disc
SFET. The gathe gate-source,
gate and grounOS inverter is s
charged, depen
3
te capacitance , gate-drain, an
nd of a resistoswitched low-tonding upon th
34
is nd
or o-he
35
Output High-to-Low Transition
The transient characteristics of interest during the Output High-to-Low Transition are the fall time
τf and the High-to-Low propagation time τPHL.
The fall time τf and the High-to-Low propagation time τPHL are expressed as
( )( ) ( ) ⎥
⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛+
−−−
+−
−+=
OLDD
OLTDD
TDDTDD
DDOLTLf VV
VVVVVkVVk
VVV
LWC
9.01.09.029.1
ln11.01.02'2'
τ
and
( ) ( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛−
−−
−+
−=
OLDD
OLTDD
TDD
L
TDD
TLPHL VV
VVV
VVk
CVVk
VC5.05.0
5.025.1ln'
22'
τ
As with τf, τPHL is directly proportional to the load capacitance and inversely proportional to
W/L. Output Low -to-High Transition
The analysis of the output low-to-high transition involves the charging of the output load capacitance through the load resistor RL of the inverter. The transient characteristics of interest during the
output low-to-high transition are the rise time τr and the low-to-high propagation time τPLH.
The rise time τr and the low-to-High propagation time τPLH are expressed as
⎥⎦
⎤⎢⎣
⎡−−
=OLDD
OLDDLLr VV
VVCR
1.01.09.09.0
lnτ
and
)2ln(LLPLH CR=τ
Pre-NMO
(VTC)and 7.
Circui
-LaboratoOS Inverte
Simulate th) and calculate
it description a
ry er Propagation
he NMOS inve and measure
and specific pa
n Delay
verters using Pthe propagatio
rameters
PSPICE to deon delays. The
termine the ve NMOS invert
oltage transfeters are shown
3
er characteristn in Figures 5,
36
tic 6
37
The input voltage VIN is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time
(TF) equal to 2 ηS, delay time (TD) equal to 0 ηS, a duration (PW) of 500 ηS and a period (PER) of
approximately 1 μS. VGG = 10V.
The transistors used in the simulation will be a NMOS with the following model parameters for both
Netlist and Schematic circuit.
.MODEL parameters for the NMOS are: (VTO=1 KP = 20u GAMMA = 0.37 PHI = 0.6 CBD = 3.1E-15 CBS=3.1E-15) M1 (W=10u L =5u) M2 (W=5u L =20u) Pre – Laboratory Procedure
11. Use PSPICE to get the DC operating point for the circuits shown in Figures 5, 6, and 7 and
complete the Table 1 of the pre-laboratory report.
12. Use PSPICE to get the transient response for the circuit shown in Figure 5.
13. Plot both VIN and VDS as outputs superimposed on the same plot.
14. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's
questions.
15. Determine τPHL and τPLH for the simulation and record the values in the report's questions.
16. Print the plot.
17. Vary W/L ratio of the NMOS M1 for the circuit shown in Figure 5 and repeat step 2 to 5
18. Vary RL for the circuit shown in Figure 5 and repeat step 2 to 5
38
Pre – Laboratory Report Table 1
NMOS Inverters DC Parameters Measured
Valued VIN=0V
Measured Valued VIN=5V
Resistor Load
ID
VDS(OUT)
Saturated Load
ID
VDS(OUT)
Linear Load
ID
VDS(OUT)
7. What are the values for :
VIL = _____ VIH = _____ VOL = _____ VOH = _____
8. Calculate τPLH and τPHL for the simulation.
τPLH = __________________ τPHL = _________
9. What is the propagation delay of the gate?
τP = _________
10. Make a comparative analysis of the table 1 data and explain yours reasoning.
LabNMO
boratory POS Inverte
1. Connec
2. Using
from 0
determ
drain c
report.
3. Vary th
Table 1
4. Replac
from a
Volts a
5. Use the
0.5 Vo
center.
6. Draw a
the sca
VOH, VO
7. Attach
8. Apply
Use the
inverte
9. Draw a
the sca
τr, τPH
Procedureer Voltage T
ct the NMOS i
the DC powe
0 to 5 V and
mine the voltag
current, record
he 10 kΩ poten
1 of the report.
e the DC inp
a function gen
and frequency o
e Oscilloscope
lts/division. A
a rough sketch
ales that were
VOL, VM, noise m
a load capacita
a 200 Hz 0 to
e oscilloscope
r.
a rough sketch
ales that were u
HL and τPLH.
e Transfer C
nverter shown
er supply, vary
d use the dig
ge at the outpu
ding your valu
ntiometer and
ut voltage VIN
nerator with p
of 100 Hertz.
with the Y-ax
djust the X zer
of the charact
used) of the r
margins, etc.
ance of 100 nF
5 volt square
to plot vIN and
of the charact
used) of the rep
Characteris
in figure 5.
y the input v
gital Multime
ut, and measu
es in table 1
record the val
N with a sine
eak amplitude
xis sensitivity s
ro reference to
teristic display
report. Comme
F to the output
wave to the in
d vOUT. Determ
teristic display
port. Comment
stic
oltage
ter to
ure the
of the
lues in
wave
e of 5
set to 1 Volt/di
o the screen cen
yed on the osci
ent on the imp
node.
nput of the inve
ine the propag
yed on the osci
t on the import
ivision and the
nter and the Y
illoscope in the
portant points o
erter. Set the D
gation delays, τ
illoscope in the
tant points of t
3
X-axis sensiti
Y reference belo
e Graphic 1(In
of the graph su
DC offset to be
τPHL and τPLH,
e Graphic 2(In
the graph such
39
ivity at
ow the
ndicate
uch as
e 2.5V.
of the
ndicate
as τf,
40
Laboratory Report
Table 1
Potentiometer Position DC Parameters
Measured Valued VIN=0V
Measured Valued VIN=5V
1KΩ ID
VDS
5 KΩ ID
VDS
10KΩ ID
VDS
Graphic 1
41
Graphic 2
8. Record the values of VIN corresponding to the VDS values given below from the transfer curve
displayed on the oscilloscope.
VDS = 4V VIN =______V.
VDS = 3V VIN =______V.
VDS = 2V VIN =______V.
9. What are the values for :
VIL = _____ VIH = _____
VOL = _____ VOH = _____
10. What are the noise margins for the Gate?
NMH = ____________
NML = ____________
42
EXPERIMENT 05 CMOS Technology Objectives
4. Familiarize with the CMOS structure. 5. Design and analyze a CMOS Inverter. 6. Determine the voltage transfer characteristic (VTC) of CMOS inverter 7. Calculate and measure the propagation delays of the CMOS inverter.
Required Equipments
• Oscilloscope • Power supply • Function generator • Digital Multimeter • Bread-Board o Protoboard
Background A CMOS inverter is an ingenious circuit which is built forms a pair of NMOS and PMOS transistors operating as complementary switches as illustrated in Figure3.2. The main advantage of a CMOS inverter over many other solutions is that it is built exclusively out of transistors operating as switches, without any other passive elements like resistors or capacitors. From Figure 1 note that the PMOS (pull-up transistor) is connected between VDD and the output node, VOUT, whereas the NMOS (pull - down transistor) is connected between the output node, VOUT, and the ground, GND. The principle of operation is as follows (refer also to the right part of Figure 2).
• For small values of the input voltage, VIN, the NMOS transistor is switched off, whereas the pull-up PMOS transistor is switched on and connects the output mode to VDD.
• For large values of the input voltage, VIN, the PMOS transistor is switched off, whereas the pull-down NMOS transistor is switched on and connects the output mode to GND = 0V.
43
A better inside into the working of the CMOS inverter can be obtain by looking at its transfer and current characteristics presented in Figure 2.
The transfer characteristic presents the output voltage vOUT versus the input voltage vIN. Note that when the input voltage increases from 0V to 5V the output voltage decreases from 5V to 0V. The current characteristic presents the current flowing through the transistors between VDD and GND also versus the input voltage VIN. From the above characteristics we can observe the existence of three basic regions of operations denoted 1, 2, 3 in Figure 2.
• In region 1 when 0 _ VIN < VTN The NMOS transistor is cut off, the PMOS switch is closed and VOUT = VDD iD = 0
• In region 3 when VIN > VDD - VTN
The PMOS transistor is cut off, the NMOS switch is closed and VOUT = 0 and iD=0 The fact that in regions 1 and 3 no current flows between VDD and GND, is very attractive because there is no power dissipation at this stages. This very fact is the reason that all digital circuitry is now build in the CMOS technology. In region 2 when VN < VIN < VP
The transistor remains only for a short period of time, when the input voltage switches between VL and VH.
In this region there is non-zero current flowing between VDD and GND, and some power
dissipation, which is converted into heat. Note that the same current flows through the PMOS and NMOS transistors, that is,
44
IDp = IDn
Transient properties of the CMOS inverter In this section we will investigate basic transient properties of the CMOS inverter, that is, its dynamic behavior during switching the input signals from low-to-high or high-to-low voltages and associated power dissipation. Propagation delay Let us consider a CMOS inverter driven by a voltage pulse. Typical input/output waveforms are shown in Figure 3. Basic characterization of the dynamic behavior of an inverter is given by its two propagation delay times, τHL and τLH as illustrated in Figure 3. Note that these propagation times are specified with respect to the mid voltage V0.5:
Figure 3.7: Input/output waveforms for a CMOS inverter.
The propagation delay times, τHL (τLH) specifies the input-to-output time delay during the high-to-low (low-to-high) transition of the output voltage. Often, it is convenient to refer to the average propagation delay, τp which specifies the average time required for the input signal to propagate through the inverter:
Similarly, we can define the fall time, τF , and the rise time, τR, as the time required for the output voltage to change between V90% and V10% . Where V10% = VL + 0.1(VH − VL) , and V90% = VL + 0.9(VH − VL)
45
The physical reason for the propagation time delay is the existence of the parasitic capacitances associated with a MOS transistor. We can combine all such capacitances into an equivalent load capacitance, Cld, as illustrated in Figure 4.
As illustrated by the voltage and current characteristics from Figure 2, during transition between low and high input voltages, there is a current flowing through the transistors forming the inverter. A part of this current charges and discharges the load capacitance which is responsible for propagation delays. If we approximate the current flowing through the load capacitance by its average value, Iavg, then the propagation time can be estimated as:
where ΔV indicates the voltage change across the load capacitance, that is, the change of the output voltage. The value of the load capacitance of the inverter without the interconnecting lumped capacitance is in the order of 0.01pF = 10fF. We can estimate that the propagation time is in the order of τp = 100ps = 0.1ns Pre-Laboratory CMOS Inverter Propagation Delay
Simulate the CMOS inverters using PSPICE to determine the voltage transfer characteristic (VTC) and calculate and measure the propagation delays. The CMOS inverter is shown in Figure 5.
Circui
(TF) e
approx
param Pre –
it description a
The input v
equal to 2 ηS
ximately 1 μS.
The transis
meters for both N
– Laborato
19. Use PS
Table
20. Use PS
21. Plot bo
22. Determ
questio
23. Determ
24. Print th
and specific pa
voltage VIN is a
S, delay time
stors used in
Netlist and Sch
ory Procedu
SPICE to get t
1 of the pre-lab
SPICE to get th
oth VIN and VO
mine VIL, VIH
ons.
mine τPHL and
he plot.
Figur
rameters
a PULSE wave
(TD) equal to
the simulatio
hematic circuit
ure
the DC operati
boratory report
he transient res
OUT as outputs s
, VOL, and V
τPLH for the sim
re 5: CMOS Inv
eform with an a
o 0 ηS, a dur
n will be a N
t.
ing point for t
t.
sponse for the c
superimposed o
VOH for the sim
mulation and r
verter
amplitude of 5
ration (PW) o
NMOS and P
the circuits sho
circuit shown i
on the same plo
mulation and
record the valu
5V, the rise tim
f 500 ηS and
PMOS with th
own in Figures
in Figure 5.
ot.
record the va
ues in the repor
4
me (TR) and fa
d a period (PE
he following
s 5 and comple
alues in the r
rt's questions.
46
all time
ER) of
model
ete the
eport's
47
25. Vary W/L ratio of the MOSFETs for the circuit shown in Figure 5 and repeat step 2 to 5
26. Vary CL for the circuit shown in Figure 5 and repeat step 2 to 5
48
Pre – Laboratory Report Table 1
Circuit DC Parameters Measured
Valued VIN=0V
Measured Valued VIN=5V
CMOS Inverter
ID
VOUT
VOUT
11. What are the values for :
VIL = _____ VIH = _____ VOL = _____ VOH = _____
12. Calculate τPLH and τPHL for the simulation.
τPLH = __________________ τPHL = _________
13. What is the propagation delay of the gate?
τP = _________
LabCMO
boratory POS Inverte
10. Connecfigure 6
11. Using t
input v
the dig
the vo
measur
your va
12. Replac
with a
generat
Volts a
13. Use the
0.5 Vo
center.
14. Draw a
the sca
VOH, VO
15. Attach
16. Apply
Use the
inverte
Procedureer Voltage T
ct the CMOS in6.
the DC power
voltage from 0
gital Multimet
oltage at th
re the drain cu
alues in table 1
e the DC inp
a sine wave f
tor with peak
and frequency o
e Oscilloscope
lts/division. A
a rough sketch
ales that were
VOL, VM, noise m
a load capacita
a 200 Hz 0 to
e oscilloscope
r.
e Transfer C
nverter shown
supply, vary t
0 to 5 V and u
ter to determi
he output, an
urrent, recordin
1 of the report.
put voltage V
from a functio
amplitude of
of 100 Hertz.
with the Y-ax
djust the X zer
of the charact
used) of the r
margins, etc.
ance of 22 nF t
5 volt square
to plot vIN and
Characteris
in
the
use
ne
nd
ng
VIN
on
f 5
xis sensitivity s
ro reference to
teristic display
report. Comme
to the output n
wave to the in
d vOUT. Determ
stic
set to 1 Volt/di
o the screen cen
yed on the osci
ent on the imp
node.
nput of the inve
ine the propag
ivision and the
nter and the Y
illoscope in the
portant points o
erter. Set the D
gation delays, τ
4
X-axis sensiti
Y reference belo
e Graphic 1(In
of the graph su
DC offset to be
τPHL and τPLH,
49
ivity at
ow the
ndicate
uch as
e 2.5V.
of the
50
17. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 2(Indicate
the scales that were used) of the report. Comment on the important points of the graph such as τf,
τr, τPHL and τPLH.
51
Laboratory Report
Table 1
CL DC Parameters Measured
Valued VIN=0V
Measured Valued VIN=5V
.22nF ID
VOUT
22nF ID
VOUT
Graphic 1
52
Graphic 2
11. Record the values of VIN corresponding to the VOUT values given below from the transfer curve
displayed on the oscilloscope.
VOUT = 4V VIN =______V.
VOUT = 3V VIN =______V.
VOUT = 2V VIN =______V.
12. What are the values for :
VIL = _____ VIH = _____
VOL = _____ VOH = _____
13. What are the noise margins for the Gate?
NMH = ____________
NML = ____________
53
EXPERIMENT 06 Logic Interfacing Objectives
8. Familiarize with TTL open-collector devices, three state outputs and transceivers. 9. Design logic interface between different logic families.
Required Equipments
• Digital Multi-meter • Digit-lab • Bread-Board o Protoboard
Situation often arise where many components in digital system must share a common path to be able to transfer data to one another. To reduce the number of interconnections, a small set of shared lines called bus may be used. In general, outputs from different devices cannot be simultaneously present on the bus. Consequently, for proper operation, that is, to prevent bus contention, only one of the devices connected to a shared bus can place information on the bus at any time. TTL open-collector devices permit the simultaneous connection of the outputs of two or more devices to form a bus.
In many applications such as bus-organized digital systems where various outputs must be ANDed, using TTL gates with totem-pole outputs would require an AND gate with as many input lines as there are signals to be ANDed.
Additional logic is created when the outputs of two or more open-collector gates are tied together, as in Figure 1. This scheme is called the wired-AND and is used to save logic gates in comparison with other methods.
54
It is not possible to interconnect
TTL gates with totem-pole output stages in the configuration. Figure 2 depicts the high level current path when the outputs of totem-pole gates are tied together. Gate A dissipate a large amount of power, and Q3B is required to sink a current which may exceed its guaranteed 16mA sink capacity.
Although the main application of the open collector gate is to allow the formation of the wire-AND, it is also useful for driving an individual load like an LED or relay. The output stage for the two-input open-collector NAND gate 7401 consists solely of the common-emitter transistor without even a collector resistance. This gate, when supplied with a proper load resistor RL, may be paralleled with other similar TTL gates. At the same time, it will drive from one to nine standard loads of its own series. When no other open-collector gates are tied, it may be used to drive ten loads. Their main disadvantage is that these gates are inherently slowly and more subject to noise than their totem-pole counterpart. The pull-up resistor bias can be raised to any voltage within the breakdown voltage of the driver transistor
55
to enable interfacing to a system employing voltage swings, like a CMOS.
To determine the value of the external pull-up resistor, we should find the upper and lower limits of the range of values the resistor can take. A maximum value is found which will ensure that sufficient source current to the loads and off current through paralleled outputs will be available when the output is logical 1. Therefore, the total leakage current determines the maximum value of RL when all driving transistors are off, as shown in Figure 4. When Vo is high so that the drivers are off, the voltage drop across RL must be less than
VRL(max) = VCC – VOH(min)
On the other hand, the total current through RL is the sum of the load current IIH and the leakage current IOH through each driver. Therefore,
IRL = ηIOH + NIIH Where η is the number of gates wired-AND connected, and N is the number of standard loads. Note that IOH is into the output terminal and hence positive. Using equations 1 and 2, we find
RL(max) = VRL(max)/IRL
RL(max) = (VCC – VOH(min))/ (ηIOH + NIIH)
A minimum value for the
pull-up resistor is established when Vo is logical 0, so that the current through RL and the total sinking current from the load gates do not cause the output voltage to rise
above VOL(max) even if only one driving gate is sinking all the current. Therefore, the current must be limited to the recommended maximum IOL, which will ensure that the low-level output voltage will be below VOL(max). Since part of IOL will be supplied from the loads, the amount of current that can be allowed through RL will be reduced. Hence, neglecting the leakage currents of the turned-off drivers, we have
RL(min) = VRL(min)/IRL
RL(min) = (VCC – VOL(max))/ (IOL(max) – N|IIL|)
Logical 0 circuit conditions to calculate RL(min) are illustrated in Figure 5. Table 1 provides the electrical characteristics of the 7401 open-collector NAND gate.
56
Table1: Electrical Characteristics of the two-Input NAND Gate 7401
VOH (min) 2.4V
IOH (min) 250uA
τPLH 35ns
VIH (min) 2V
IIH (min) 40uA
τPHL 8ns
VOL (max) .4V
IOL (max) 16mA
CL 15pF
VIL (max) .8V
IIL (max) -1.6mA RL 4kΩ for τPLH
400Ω for τPHL
57
Three-State Outputs
Another useful variant of TTL that can solve the problem of driving a common bus line by two or more logic circuits is the three-state output arrangement shown in Figure 6. The term tri-state is also used. However, it is registered trademark of National Semiconductor Corporation, which introduced this design concept in 1970.
Figure 6
By combining the high-speed advantage of the totem-pole output with the advantages of an open-
collector output, the three-state gates enable the connection of a number of gates to a common output line or bus. In addition to a totem-pole output, these gates have another terminal, called the output enable, which permits the device to function normally or the output signal to be disconnected from the rest of the circuit by going into a third state in which both output transistors are turned off, resulting in an extremely high output impedance. Therefore, a disabled gate can be assumed to have an open circuit in its output line, so that the high impedance state may be equated to the voltage level of a conductor that has no sources connected to it, that is, it is floating.
The two most frequently used three-state ICs in the standard TTL logic subfamily are the 74125 and 74126 quadruple-bus buffers with independent output controls. Both are non-inverting buffers, but the former’s output for the 74125 is enabled by a logical 0 while the 74126 is enabled by an active high signal. Three-State CMOS Buffers
The CMOS three-state output buffer has logic elements in the gate connections to each of the transistors in the final inverter, so that both may be turned off under the control of an enable function. Figure 7 illustrates the logic diagram of such a buffer with active low-enable input. Note that additional inverters are added as buffers or to optimize timing. The truth table of the CMOS Buffers is shown in table 2.
58
G' A VGP VGN Y 0 0 0 0 1 0 1 1 1 0 1 0 1 0 Z 1 1 1 0 Z
Table 2: Truth table
59
Pre-Laboratory TTL Open-Collector Outputs
60
Pre – Laboratory Procedure
27. Simulate the circuit shows in Figure 8 using PSPICE. Use 7401 and 7400 TTL Open-
Collector NAND and standard NAND respectively.
28. Sweep the value of the pull-up resistor and determine the value maximum and minimum for
optimum performance and complete the Table 1 of the pre-laboratory report.
29. Connect the circuit shows in Figure 9 using PSPICE and determine how many TTL inputs
can drive.
30. Simulate the circuit of Figure 10 using PSPICE and find the DC operating point and complete
the Table 2 of the pre-laboratory report.
31. Simulate the circuit shows in Figure 11 using PSPICE and prove the truth table of the circuit.
How many TTL inputs can drive the circuit of Figure 7
Table 2
Figure 10 VRL (High) VOL IOL
DC parameters
61
Laboratory Procedure Open-Collector TTL Outputs
18. Connect the circuit of Figure 12 with the 7401 and 7400 TTL Open-Collector NAND and standard
NAND respectively. Vcc = +5V
19. Add load to the output in order to
determine the fan-out of the gate. Use the digital
Multimeter to determine the output voltage and the
currents in the circuit when you are adding a gate and
record your values in table 1 of the report.
20. Co
nnect the circuit
of Figure 13
using 7401 and
7400 TTL NAND and AND gate respectively with high
input voltages and record your values in Table 1 of the
report. Vcc = +5V
21. Vary the 10 kΩ potentiometer and record the values in
Table 1 of the report.
22. Using the Digit lab DC switch to vary the input voltage
from 0 to 5 V and use the digital Multimeter to determine
the voltage at the output, and the currents in the circuit
recording your values in table 1 of the report.
23. Connect the circuit shown in Figure 14.
24. Using the Digit lab DC switch to vary the input
voltage from 0 to 5 V and use the digital Multimeter
to determine the voltage at the output, and the
currents in the circuit recording your values in table
3 of the report.
25. Change the 7401 TTL Open-Collector NAND by the
7400 standard NAND and repeat step 7.
62
26. Connect the circuit shown in Figure 15.
27. Using the Digit lab DC switch to vary the input
voltage from 0 to 5 V and use the digital Multimeter to
determine the voltage at the output, and the currents in the
circuit recording your values in table 4 of the report.
63
Laboratory Report
Table 1
Loads VOL VOH IOH IIH IOL IIL 1
2
3
4
5
Table 2
DC Parameters
RL Value VOL VOH IOH IIH IOL IIL
IRL(OH)= 410Ω
IRL(OL)=
IRL(OH)= 1kΩ
IRL(OL)=
IRL(OH)= 2.3 kΩ
IRL(OL)=
IRL(OH)= 5 kΩ
IRL(OL)=
64
Table 3
Figure 14 VRL (High) VOL IOL VOH IOH
7401
7400
Table 4
Figure 15 VRL (High) VOL IOL VOH IOH
7400
Compare the results obtain in table 3 and table 4 and explain your conclusions Conclusions
65
EXPERIMENT 07 Regenerative circuits Objectives
1. Wire and observe the operation of an R-S flip-flop. 2. Wire and observe the operation of a Master-Slave J-K flip-flop level and edge triggered. 3. Compare the wave shaping action of a regular TTL IC with a Schmitt trigger IC.
Required Equipments
• Digit-lab • Bread-Board o Protoboard • Function Generator • Oscilloscope
Required Parts list
• 7402 2-input NOR gate IC • 7404 inverter TTL IC • 7414 Schmitt trigger inverter TTL IC • 74104 or 74105 J-K Master-Slave flip flop • 74109 Dual J-K Positive-Edge-Triggered Flip-Flop with Clear and Preset • 74112 Dual J-K Negative-Edge-Triggered Flip-Flop with Clear and Preset • 74279 S-R flip flop with NAND • 3 LEDs • (2) 150Ohms resistors
Background
Multivibrators are regenerative circuits that are used used to implement a variety of simple two-state systems such as oscillators, timers and flip-flops. The most common form is the astable or oscillating type, which generates a square wave - the high level of harmonics in its output is what gives the multivibrator its common name.
There are three types of multivibrator circuit:
• Astable, in which the circuit is not stable in either state - it continuously oscillates from one state to the other.
• Monostable, in which one of the states is stable, but the other is not - the circuit will flip into the unstable state for a determined period, but will eventually return to the stable state. Such a circuit is useful for creating a timing period of fixed duration in response to some external event. This circuit is also known as a one shot. A common application is in eliminating switch bounce.
• Bistable, in which the circuit will remain in either state indefinitely. The circuit can be flipped from one state to the other by an external event or trigger. Such a circuit is important as the fundamental building block of a register or memory device. This circuit is also known as a flip-flop. A similar circuit is a Schmitt trigger.
In electronics and digital circuits, the flip-flop or bistable multivibrator is a pulsed digital circuit capable of serving as a one-bit memory. A flip-flop typically includes zero, one, or two input signals; a clock signal; and an output signal, though many commercial flip-flops additionally provide
the complement of the output signal. Some flip-flops include a clear input signal, which resets the current output. Because flip-flops are implemented as integrated circuit chips, they also require power and ground connections.
Pulsing, or strobing, the clock causes the flip-flop to either change or retain its output signal, based upon the values of the input signals and the characteristic equation of the flip-flop. Strobing here means changing the clock; some flip-flops change output on the rising edge of the clock, and other change on the falling edge.
Flip-flops can be split into two main categories: level-triggered and edge-triggered. They can further be divided into four types that have found common applicability in clocked sequential systems: these are called the T ("toggle") flip-flop, the SR ("set-reset") flip-flop, the JK flip-flop, and the D ("Data") flip-flop. The behavior of the flip-flop is described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, Q(next), in terms of the input signal(s) and/or the current output, Q.
Level-triggered flip-flops respond whenever a signal level changes.
Set-reset flip-flops (SR flip-flops)
The SR (set-reset) flip-flop has two inputs: S (set) and R (reset). If R is active, the output goes to zero. If S is active, the output goes to one. If neither is activated, the previous state is maintained. Both inputs should not be activated simultaneously; however, if they are, the typical response is for both the inverted and non inverted outputs to have the same level.
The behavior of an SR flip-flop can be written in the form of a truth table:
NOR NAND S R Q Q(next) S R Q Q(next) 0 0 Q Q(next) 0 0 undetermine 0 1 1 0 0 1 x 0 1 0 0 1 1 0 x 1 1 1 Undetermined 1 1 Latch Latch
Truth table for an SR flip flop with NOR and NAND gates
We can implement a SR flip-flop with a pair of either NAND or NOR gates. The NOR version is conceptually easier as it has active high inputs. However, the NAND version is more widely known and used, as NAND gates were cheaper in transistor-transistor logic.
We can also easily add an enable input. If this is implemented in the same gates as the flip-flop, then it serves to further invert the inputs - meaning a NAND based device will now have active high inputs. This input may be regarded as a clock but the flip-flop is still unsuitable for sequential design. When the clock goes high, the signal will propagate through all flip-flops, not just from one to the next.
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68
SCHMITT TRIGGER
In electronics, a Schmitt (or Schmidt) trigger is a comparator circuit that incorporates positive feedback.
When the input is higher than a certain chosen threshold, the output is high; when the input is below another (lower) chosen threshold, the output is low; when the input is between the two, the output retains its value. The trigger is so named because the output retains its value until the input changes sufficiently to trigger a change. This dual threshold action is called hysteresis, and implies that the Schmitt trigger has some memory.
The benefit of a Schmitt trigger over a circuit with an only single input threshold is greater stability (noise immunity). With only one input threshold, a noisy input signal near that threshold could cause the output to switch rapidly back and forth from noise alone. A noisy Schmitt Trigger input signal near one threshold can cause only one switch in output value, after which it would have to move to the other threshold in order to cause another switch.
The Schmitt trigger was invented by US scientist Otto H. Schmitt.
The symbol for Schmitt triggers in circuit diagrams is a triangle with a hysteresis symbol.
Pre-Laboratory Regenerative circuits
Wire and test one J-K flip flop from the CMOS 4027 dual J-K flip flop IC. Observe and record your values in table 1.
Pre – Laboratory Report Table 1
Mode of operation Inputs Outputs
Asynchronous Synchronous
PS CLR CLK J K Q Q'
Asynchronous Set 0 1 x x x Asynchronous reset 1 0 x x x
Prohibited 0 0 x x x 1 1 Hold 1 1 ↑ 0 0 No change Reset 1 1 ↑ 0 1 Set 1 1 ↑ 1 0
Toggle 1 1 ↑ 1 1 Preset Clear Clock Data Data
Laboratory Procedure Regenerative circuits
1. Wire the logic circuit of the R-S flip-flop shown in Figure. Wire outputs Q and Q’ to two LEDs.
10. Operate the asynchronous inputs PS and CLR and record the results in Table 5.
11. In the right-hand column of Table 5 write the condition of the output. Choices are listed.
12. Disable the asynchronous inputs (PS and CLR to 1).
13. Operate the synchronous inputs J, K and CLK of the 74LS112 IC according to the truth table in
Table 6. Observe and record the results in column Q and Q’.
14. In the right-hand column of Table 6 write the condition of the output. Choices are listed.
15. Insert the 7404 and 7414 ICs into the mounting board and wire the circuits shown in the Figure.
16. Set Vin with the function generator. Set the function generator to sine wave. Set the frequency
from 50 to 200 Hz. Adjust the function generator voltage to 2 to 4 V p-p.
17. Use the Oscilloscope to observe the output waveforms for the circuits. Draw a rough sketch of the
characteristic displayed on the oscilloscope in the Graphic 1 and 2(Indicate the scales that were used)
of the report.
71
Laboratory Report Table 2
NOR
S R Q Q(next)
Name of
condition
0 0
0 1
1 0
1 1
Table 3
R-S flip-flop 74279
S R Q Q(next)
Name of
condition
0 0
0 1
1 0
1 1
Table 4
Inputs Outputs
Clock Data Before clock pulse After clock pulse Name of condition
CLK S R Q Q' Q Q'
0 0 0 1
0 1 0 1
1 0 0 1
1 1 0 1 Prohibited
0 0 1 0
0 1 1 0
1 0 1 0
1 1 1 0 Prohibited
Hold, reset, or set
72
Table 5
Inputs Outputs
Clear Preset Q Q' Name of Condition
0 0 Prohibited
0 1
1 0
1 1
Clear Q to 0
Disable
Preset Q to 1
Table 6
Inputs Outputs
Clock Data
Before clock
pulse
After clock
pulse Name of condition
CLK J K Q Q' Q Q'
↑ 0 0 0 1
↑ 0 1 0 1
↑ 1 0 0 1
↑ 1 1 0 1
↑ 0 0 1 0
↑ 0 1 1 0
↑ 1 0 1 0
↑ 1 1 1 0
PS and CLR=1 Hold, reset, set, or toggle
73
Graphic 1(7404)
Graphic 2(7414)
Which IC seems to do the best job of converting the sine wave into a sharp square wave?
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The typical A/D converter will have eight output lines. Each line is capable of being a logic 1 or 0. Each binary digit is called a bit –an acronym for binary digit. Thus such an A/D device is called an 8 nit A/D converter. Now assuming that each of the eight output lines could be a logic 1 or 0, there are 28, or 256, different binary codes which can be represented by the 8-bit A/D converter. Assume an input voltage of 0V to the A/D converter; its output would be the binary equivalent, or 00000000. For each input voltage level there will be a specific equivalent binary output on the eight output lines. Resolution and accuracy
Resolution of an A/D converter is defined as the smallest increment input voltage that can be determined by the converter. Resolution is primarily a function of the number of output bits. For example, if the converter has 256 different outputs codes, the input signal is represented by binary numbers from 00000000 to 11111111. If the input ranges from 0 to 5 V, the resolution is
VV 0195.02565
=
Thus, the binary output of 00000001 represents 0.0195 V. Likewise, 00000010 represents 0.039 V, and so on. What would be the binary representation of, say, 3.042V? Clearly,
1560195.0042.3
=V
which, when converted to binary, is 10011100.
The accuracy of the A/D converter is determined by how closed the actual converter output is to the theoretical output. For example, if the 8-bit A/D converter had an accuracy expressed as ± 1 least significant bit (LSB), the accuracy could be expressed as
%4.0100*2561100*
21
8 ===accuracy
Digital-to-Analog converter In electronics, a digital-to-analog converter (DAC or D-to-A) is a device for converting a digital
(usually binary) code to an analog signal (current, voltage or electric charge). Digital-to-analog converters are the interface between the abstract digital world and the analog real life. Simple switches, a network of resistors, current sources or capacitors may implement this conversion.
The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers) into a physical quantity, usually an electrical voltage. Normally the output voltage is a linear function of the input number. Usually these numbers are updated at uniform sampling intervals and can be thought of as numbers obtained from a sampling process. These numbers are written to the DAC, sometimes along with a clock signal that causes each number to be latched in sequence, at which time the DAC output voltage changes rapidly from the previous value to the value represented by the currently latched number. The effect of this is that the output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant output (Figure 2). This is equivalently a zero-order hold operation and has an effect on the frequency response of the reconstructed signal.
The fact that practical DACs do not output a sequence of dirac impulses (that, if ideally low-pass
filtered, result in the original signal before sampling) but instead output a sequence of piecewise constant values or rectangular pulses, means that there is an inherent effect of the zero-order hold on the effective frequency response of the DAC resulting in a mild roll-off of gain at the higher frequencies (a 3.9224 dB loss at the Nyquist frequency). This zero-order hold effect is a consequence of the hold action of the DAC
