Analog & Digital ElectronicsCourse No: PH-218

BJT

Lec-6: I-V characteristics and Ebers-Moll Model

Course Instructors:

� Dr. A. P. VAJPEYI

Department of Physics,

Indian Institute of Technology Guwahati, India 1

I-V Characteristics of BJT under common base configuration

Common Base configuration IE

2

Input characteristics Output characteristics

� Input characteristics are like a normal forward biased diode.

�As the CB junction is reverse biased, the current IC is independent of collector

voltage and depends only upon the emitter current IE. The collector current is almost

constant and work as a current source.

�When IE=0 , IC=ICB0 is the leakage current caused by the minority carriers crossing

the pn-junction.

I-V Characteristics of BJT common emitter configuration

Input characteristics Output characteristicsnpn common emitter

VCE

VBE

ICIB

3

� Input characteristics are like a normal forward biased diode.

�As the CE junction is reverse biased, the current IC is independent of collector

voltage and depends only upon the base current IB.� In real diode, the collector current slightly increases with increase in collector

emitter voltage(Early effect).

� At low value of VCE, the CBJ becomes forward-biased and the transistor enters the

saturation region.

Early Effect (Base width modulation)

VA is called the Early voltage and

ranges from about 50 V to 100 V.

Observed by James Early

+=

A

CEkT

eV

sC

V

VeII

BE

1

Early effect can be modeled as

4

� When VCB increases:

� depletion region of CBJ widens

� so the effective base width decreases (base-width modulation) VCB > VCB

o

CE

cC

r

VII +=

')exp(I s

'

kT

eVI

BE

c=where

Base punch through

� if reverse bias voltage of C-B junction is keep on increasing, a situation arises

where E-B and C-B space charge regions touch each other, and the width of the

quasi-neutral base region becomes zero, Known as base punch through.

5

� Any increase in VCB beyond the punch-through point lowers the E-B potential

barrier and allows a large injection of carriers from the emitter directly into the

collector.

�If punch-through occurs, the maximum voltage (VCB0 or VCE0) that can be applied

to a BJT is limited.

RC

VBB

VCC+

vBE

+

-

VCE

IB

IE

IC

RB

DC Load Line Analysis

6

-

Application of KVL in output (CE)circuit:

VCE = VCC – ICRC ; is called Load line equation.

When IC = 0, VCE = VCC ; When VCE = 0, IC = VCC/RC

� The operating point Q (VCEQ, ICEQ) is determined by finding the intersection

point of load line and BJT output characteristics for a particular value of base current.

Ebers-Moll Model (Large-Signal Model)

� The Ebers-Moll (EM) model is a large-signal model for BJT. It relates the transistor d.c terminal currents to voltages.

� EM model is low frequency (static) model based on the fact that BJT is composed of two pn junctions – EB and CB junction.

� Therefore terminal currents of BJT can be expressed as a superposition of the currents due to the two pn junctions.

D : E-B junction diode

7

DE : E-B junction diode DC : C-B junction diode

)1(I SE −=T

BE

V

V

DEeI )1(I SC −=

T

BC

V

V

DCeI

)1()1(II

SC−=−==

T

BE

T

BE

V

V

SE

V

V

DEeIeI

αα

Ebers-Moll Model (Large-Signal Model)

Forward Active ModeReverse Active Mode

8

DCRFB

DCFC

DCRE

II

II

II

)1()I1(

I

I

DE

DC

DE

αα

α

α

−+−=

+−=

−=

)1(I

)1(

)1()1(I

S

S

−−−=

−−−=

T

BC

T

BE

T

BC

T

BE

V

V

R

V

V

SC

V

V

S

V

V

F

E

eeII

eIeI

α

α

Ebers-Moll Model (Large-Signal Model)

BJT Forward Active Mode

BE forward-biased, BC reverse-biased:

9

BJT Reverse Active Mode

BE reverse-biased, BC forward-biased:

BJT Cut-off Mode

BE reverse-biased, BC reverse-biased:

Ebers-Moll Model (Large-Signal Model)

10

BJT Saturation Mode

BE forward-biased,

BC forward-biased:

BJT with input ac signal

11

Biasing schemes for BJT

� Biasing refers to the application of D.C. voltages to setup the operating

point in such a way that output signal is undistorted throughout the whole operation.

� Also once selected properly, the Q point should not shift because of change of IC due to

(i) β variation(ii) Temperature variation

12

(ii) Temperature variation

Different biasing schemes

(i) Fixed bias (base resistor biasing)(ii) Collector base bias

(iii) Emitter bias

(iv) Voltage divider bias

DCRFB

DCFC

DCRE

II

II

II

)1()I1(

I

I

DE

DC

DE

αα

α

α

−+−=

+−=

−=

13

)1(I

)1(

)1()1(I

S

S

−−−=

−−−=

T

BC

T

BE

T

BC

T

BE

V

V

R

V

V

SC

V

V

S

V

V

F

E

eeII

eIeI

α

α