Insights into circuits for frequency synthesis at mm-waves
Francesco Svelto
Università di Pavia
July 9th, 2013
Outline
Mm-wave applications, challenges of frequency synthesis
Inductor-less CMOS dividers operating at mmW
Wide range low noise VCO in a scaled 32nm node
Wideband receiver for Gbit/s communications
Conclusions
From RF to mmW applications
High data rate wireless communications
Automotive radars
Imaging (Security, Industrial controls, Medical diagnosis)
Chemical sensors (spectrometers)
Effort toward CMOS solution
High fT, Integration with DSP, Low cost for large volumes
30 100 200 300 40040 1000freq. [GHz]
High data rate wireless communications
~7GHz of unlicensed bandwidth available around ~60GHz
Intense standardization activity
WiGig, 802.11ad, WirelessHD, 802.15.3c, ECMA-387
MAN / LAN PAN
LO
LNA
Q
RF Mixer
IF Mixers
VCO
0°
90°
/ 2
I
Buffer
Buffer
Buffer/ 2
Synthesizer
(2/3 RF
frequency)
Fref
Typical IF receiver at mm-waves
Frequency synthesizer is challenging: wide range
and low noise at tens of GHz
RF IN
2Gbps 16-QAM
Why low phase noise? Received signal constellation
Source: IEEE 802.15-06-0477-01-003c [Online]
Phase noise rotates signal constellation and impairs BER
Phase noise <-113dBc/Hz @10MHz is required in most stringent cases, assuming 1MHz PLL bandwidth
@10MHz
Frequency Synthesizer
- Inductor-less CMOS dividers operating at mmW
- Wide-range low noise VCO in a 32nm scaled node
- Synthesizer for a receiver at Gbit/s
Outline
Mm-wave applications, challenges of frequency synthesis
Inductor-less CMOS dividers operating at mmW
Wide range low noise VCO in a scaled 32nm node
Wideband receiver for Gbit/s communications
Conclusions
For more, refer to:
A. Ghilioni et al., “mm-wave frequency dividers analysis and design based on dynamic latches with load modulation” to appear on JSSC
Injection locked dividers for mmW PLLs
Limited power consumption
Many examples demonstrated on bulk CMOS
Limited tunability due to the LC resonance
Large area due to the inductor
CML static dividers for mmW PLLs
Very wide operating range
Small area (no inductors)
Large power consumption to reach mm-Waves
Differential pair as a dynamic CML latch
Synchronous divider by four
Ring of four dynamic latches to
perform frequency division by four
Waveforms assuming Roff ∞
MAXf
tt
VtVtV
2
1
)()( 11
*
swmp When
pConR*
tt
*pDDDDp eVVVtV
pConR*
tt
bonDD*m*mm e1IRVVVtV
Maximum frequency of operation
fmax
=1
2Ron
Cp
1.41+ 0.59g( ) gg =
Vsw
Ron
Ib
Waveform with finite Roff
Rise time almost independent of Roff
fmax starts reducing only assuming Roff < 4Ron
Impact of finite Roff on fmin
VDD
- VDD
- Ron
Ibe
-thold
Roff
Cp
æ
è
çç
ö
ø
÷÷
<Vsw
Capacitors’ discharge during hold phases
determines a minimum operating frequency fmin
To ensure locking, the voltage must not fall below Vsw during the
hold phases
Minimum frequency of operation
fmin
=1
2Roff
Cpln 1/ g( )
Test chip photomicrograph
Technology:
32nm bulk CMOS
Core area: 18 x 55 µm2
Supply voltage: 1V
Meas vs. sim: sensitivity curves
Measured phase noise
Comparison with state of the art
Ref fin/fout fmin-fmax
[GHz]
L.R.
[%]
Pdiss
[mW]
Area
[µm2]
Tech
CMOS
[nm]
FoM
GHz
2
mW
[25] 3 58.6-67.2 13.7 5.2 170 x 220 65 111
[26] 3 48.8-54.6 3.5a 3.0 300 x 300 65 31.0
[27] 4 79.7-81.6 2.4 12 106 x 330 65 12.9
[28] 4 62.9-71.6 3.2 2.8 110 x 130 90 58.7
[29] 4 82.5-89.0 7.6 3.0 220 x 290 90 193
[30] 4 67.0-72.4 7.7 15.5 870x760 90 25.2
[31] 4 58.5-72.9 21.9 2.2 160x260 65 477
This
work 4 14 – 70
b 60 – 90 1.3 – 4.8 18 x 55 32 471 – 581
aEstimated from reported sensitivity curves.
bMaximum input frequency limited by our available instrumentation.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Outline
Mm-wave applications, challenges of frequency synthesis
Inductor-less CMOS dividers operating at mmW
Wide range low noise VCO in a scaled 32nm node
Wideband receiver for Gbit/s communications
Conclusions
For more, refer to:
E. Monaco et al., “A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension” ISSCC 2013
•Reduces dramatically with increasing oscillation frequency
•Wide tuning Range leads to poor phase noise FoM
•Achieving state of the art FoM and wide tuning range is
challenging
5
10
15
20
25
Frequency [GHz]20 30 40 50 60
Tu
nin
g R
ang
e [%
]
5%
10%
15%
20%
25%
30%
20.0 30.0 40.0 50.0 60.0
TR
[%]
Frequency[GHz]
30
Issues of mmWave - VCOs
• Continuous scaling driven by complex Systems on Chip • ~ 20-30% fT improvement only per generation • mmWave passive components penalty due to BEOL scaling
0.13 um 6 layers
IEDM 2010, S. Francisco
CMOS Technology Evolution
• 32nm H.L.M closer to substrate (~85%) but same thickness
• 32nm L.L.M. closer to substrate and thinner (~50% )
• 2 time resistivity of 32nm VIAs
CMOS65nm CMOS32nm
Low Level
Metals
High Level
Metals
Top Level
Metal
Low Level
Vias
High Level
Vias
CMOS 65nm vs 32nm: BEOL
• Trade-off between csw and rsw
• FOMsw measures quality of the switch:
1SW
M
rg
SW GSc C
1SW SW SW
T
FOM c rf
Switch On Switch Off
rSW csw
300
350
400
450
500
550
600
650
20.025.030.035.040.045.050.055.060.065.070.0
FO
M [
fs]
Gate Length [nm]
550
500
400
300
450
350
2030405060
FO
M[f
s]
Gate Length [nm]
70
600
650
Performance of MOS Switches
550
500
400
300
450
350
2030405060
FO
M[f
s]
Gate Length [nm]
70300
350
400
450
500
550
600
650
20.025.030.035.040.045.050.055.060.065.070.0
FO
M [
fs]
Gate Length [nm]
600
650
•Routing parasitics comparable to rSW and cSW
• FOM tends to saturate in ultra scaled technologies
Switch On Switch Off
rSW csw
w.Routing
w.o.Routing
MOS Switch With Routing Parasitics
MOM capacitors realized with low level metals for max. density MOM Q in 32nm ~70% than 65nm due to half thickness of Low Level of Metals and 2x via resistance
0
10
20
30
40
20 30 40 50 60
Qu
ality
Fac
tor
Frequency [GHz]
40
30
10
20
0
Qu
ali
ty F
ac
tor
20 30 40 50 60
Frequency [GHz]
CMOS32nm
CMOS65nm
C=250fF
measurement
CMOS 65nm vs 32nm: MOM Capacitors
• Significant MOM loss (RMOM) due to higher metals and vias resistivity. Much in the same way Csw limits tuning range
• Switched cap. tank does not benefit from technology scaling
12
MOMMAX
MIN SW
CC
C c
2
2
low
MOM MOM SW
QC R r
CMOMRMOM
LC Tank
cSW
rSW
CMOM RMOM
Switch ON
Switch OFFCMOM RMOM
Switched Capacitor Structure
32nm switched MOM worse than 65nm
5
6
7
8
9
10
1.5 1.6 1.7 1.8 1.9 2.0
Qu
ality
Fac
tor
CMAX/CMIN
10
9
7
5
8
6
1.5 1.6 1.7 1.8 1.9 2.0
Qu
alit
y F
acto
r
Cmax/Cmin
CMOS32nm
CMOS65nm
@40GHz
Q versus CMAX/CMIN
Inductors usually realized with top metals for maximum Q and self Resonance frequency Slightly lower dielectric constant in 32nm compensates lower metal distance to substrate in 32nm
0
10
20
30
0 20 40 60 80
Qu
ality
Fac
tor
Frequency [GHz]
30
20
10
0
Qu
ali
ty F
ac
tor
0 20 40 60 80
Frequency [GHz]
CMOS32nm
CMOS65nm
L=100pH
CMOS 65nm vs 32nm: Inductors
• CFIX: parasitic cap of buffer and core devices
• CFIX equal or greater than CT at mmW
.
1
2
MIN
T FIX T
fL C C
1 1
22
,SW T FIXMAX
T FIXT SWT FIX
T SW
c C Cf
L CC cL C
C c
• SW OFF: fMAX determined by CFIX
• SW ON:
-rCFIX
CT LT
csw
Switched Capacitor Oscillator
• cSW in series with CT+CFIX
• Higher frequency jump
.
1 1
22
,SW T FIXMAX
T SWT FIX SW
T
T FIX SW
c C Cf
L cC C cL
C C c
-rCFIX CT
LT
csw
• SW OFF: CFIX no more limiting fMAX
• SW ON: fMIN as in switched cap. oscillator
Proposed Oscillator
.
For the same frequency step, switch in the proposed tank may display much larger csw
-rCFIX
CT LT
-rCFIX CT
LT
csw csw
Assuming: CFIX=CT=100fF, LT=100pH, FOMSW=550fs fMIN=35.6GHz, fMAX/fMIN=1.2
cSW=50fF cSW=400fF
Comparison with same frequency jump
.
Much lower rsw leads to 2x tank Q
cSW=50fF rSW=11
Q=8
cSW=400fF rSW=1.37
Q=16
rSWrSW
-rCFIX
CT LT
-rCFIX CT
LT
Assuming: CFIX=CT=100fF, LT=100pH, FOMSW=550fs fMIN=35.6GHz, fMAX/fMIN=1.2
Comparison with same frequency jump
1
2
3
4
5
1.1 1.2 1.3
Qu
ality
Fac
tor
fMAX/fMIN
5
4
2
1
3
1.1 1.2 1.3
Qu
alit
y F
acto
r
fmax/fmin
Switch Capacitor
Proposed Tank
Advantage increase for higher frequency step and/or larger Cfix
@40
GH
z
Q vs fmax /fmin with finite components Q
Loop Gain with a conventional transconductor
Switch ON
Switch OFF
• Loop gain penalty
• Tank is an open at DC, latching issue
PON T TR L Q
2 POFF T TR L Q
0.55 0.75sw
T FIX sw
c
C C c
rsw
LT
gM
RPON CTCFIX
csw
LT
gM
RPOFF CTCFIX
M PGLOOP g R
Loop Gain with Transformer Feedback
• Transformer restores loop gain and
avoids latching
21MGLOOP g Z
21 S
PON
T
LZ K R
L
21
S POFF
T
L RZ K
L
0.55 0.75sw
T FIX sw
c
C C c
Switch ON
Switch OFF
rsw
CT
LT
CFIX
gM
RPON
LS
K 21
CTCFIX
gM
RPOFF
K
csw
LT LS
21
Simulated Impedance RP and Z21
0
50
100
150
200
250
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0
Impe
danc
e[oh
m]
Frequency [GHz]00
10 20 30 50 6040 70 80Frequency [GHz]
250
200
150
100
50
Imp
edan
ce[Ω
]
SwitchONZ21 (SwitchOFF)
RP (SwitchOFF)
• Inductor splitting with MSW for largest tuning step
• Variable tank capacitance (CT) with switched digital MOMs and varactor
• LT=100pH, CT=140fF, CFIX=120fF
• Tank Q ranges from 4 to 5.5
• Rb instead of PMOS mirrors lowers 1/f noise
LT/2
LS
M1 M2
VDD
CT
RbRb
LT/2 700µm
32nm
48µm
32nm
48µm
32nm
MSW
CFIX RCM
Realized VCO
• Direct output and after div. by 4 for Phase Noise measurement in X-Band (8-12GHz)
• CMOS 32nm LP from STMicroelectronics
• Supply voltage:1V • Core area: 70um x 120um
÷4
VCO
Divider
S
RF
Output
Divider
Output
G
G
S
G
G
Test Chip
40GHz Phase Noise Measurement
Phase Noise and FoM over Tuning Range
REF FREQ
[GHz]
TR
[%]
POWER
[mW]
PN @10MHz
[dBc/Hz]
FOM
[dBc/Hz] TECH
CICC12 57.5/90.1 44.2 8.4/10.8 -104.6/-112.2 172/180 65nm
RFIC11 11.5/22 59 20/29 -107/-127* 158.6/177.4 130nm
RFIC10 34.3/39.9 15 14.4 -118/-121* 178.4/180.1 65nm
JSSCC11 43.2/51.8 22.9 16 -117/-119* 179/180 65nm
ISSCC11 21.7/27.8 24.8 12.2 -121 177.5 45nm
This Work 33.6/46.2 31.6 9.8 -115.2/-118 177.5/180 32nm
* estimated from the reported phase noise at 1MHz
Summary and comparison
[8]
[9]
[10]
[11]
[12]
Outline
Mm-wave applications, challenges of frequency synthesis
Inductor-less CMOS dividers operating at mmW
Wide range low noise VCO in a scaled 32nm node
Wideband receiver for Gbit/s communications
Conclusions
For more refer to:
F. Vecchi et al., “A Wideband Receiver for Multi-Gb/s Communications in 65nm CMOS”, JSSC, march 2011
PHY for Gb/s wireless communications
Large RF bandwidth (~9GHz minimum)
RX Minimum Sensitivity: from -60dBm (1Gb/s) to -50dBm (4Gb/s)
RX Maximum Noise Figure < 10dB
Large LO tuning range required
Very stringent phase noise at maximum data rate
57 66 fGHz58.32 60.48 62.64 64.8
2.16 GHz
1 2 3 4
Source: ECMA International, “High Rate 60 GHz Phy, MAC and HDMI PAL”, Standard ECMA-387, 1st Edition, Dec. 2008 [Online]
High Rate 60GHz PHY Proposal
First down-conversion to 1/3 of the received frequency
Only one PLL at 38.9÷43.2 GHz
Integrated PN: <-18dBc
Injection Locked Dividers to generate I/Q IF signals
RX architecture
LO
LNA
Q
RF Mixer
IF Mixers
VCO
0°
90°
/ 2
I
Buffer
Buffer
Buffer/ 2
PLL
Fref 40GHz
Sliding IF architecture
PLL architecture
Design strategy
Increase CP current (2mA)
But reduce VCO gain (500MHz/V)
And optimize LPF to ensure stability
PFD
ILFD
÷ 2
CML
÷ 4CML to
CMOS
CMOS
÷ 5÷ 30
÷ 27
CP
VCO36 MHz
To RF
Mixer
To IF
Mixers
2
1
22
N
I
SL
CP
IcpCP
CP contribution to In-band phase noise :
Increasing ICP reduces LCP but stability becomes an issue
Phase noise measurements
LNA
RF MIXER
40 GHz
VCO
20
GHz
BUFFER
PN
/2
IF MIXER
fGHz60
fGHz40.1
fGHz0.2
PN + 3.5 dB
40GHz PLL
40
60.1
0.1
-115dBc/Hz @10MHz from 60GHz carrier
VCO Phase Noise:
-118.5dBc/Hz @10MHz from 40 GHz carrier
Integrated Phase Noise:
-22.5dBc [10kHz-10MHz] from 60GHz carrier
mmW wideband receiver
Technology: STM 65nm CMOS
Area: 2.4mm2
Power Consumption: 75mW
External LO Integrated PLL
Same Gain and Noise Figure
VCO tuning range: 16%
LNA
DIV. I
RF & IF
MIX.
SY
NT
HE
SIZ
ER
VC
O
DIV. Q
2
3
4
5
6
7
8
9
10
0
5
10
15
20
25
30
35
40
55 60 65 70
No
ise
Fig
ure
(d
B)
Ga
in (
dB
)
Frequency (GHz)
Comparison with state of the art
[13]
Scheir 09 [14]
Richard 10 [15]
Lee 08 [16]
Marcu 09
Conclusions
Several examples of realized mmW CMOS circuits for Local Oscillator generation have been presented.
A wideband divider by-4 based on dynamic latches is attractive to replace traditional injection locked prescalers. Experiments show >60% fractional bandwidth, <5mw power, 55x18mm2.
VCO with >31% tuning range around 40GHz and a remarkable FOM from 177.5dBc/Hz to 180dBc/Hz despite being in an unfavorable ultra-scaled 32nm node.
A 65nm PLL proves suitable to satisfy the stringent requirements of a wideband mmW receiver, exploiting the advantages of a sliding IF RX architecture.
[1] Hsieh-Hung Hsieh et al, "A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS," Custom Integrated Circuits Conference, pp.1-4, Sept. 2010
[2] X. P. Yu, H. M. Cheema, R. Mahmoudi, A. van Roermund and X. L. Yan, “A 3 mW 54.6 GHz Divide-by-3 Injection Locked Frequency Divider With Resistive Harmonic Enhancement,” IEEE Microwaves and Wireless Components Letters, vol.19, no.9, pp.575-577, Sept. 2009
[3] P. Mayr, C. Weyers, U. Langmann, "A 90GHz 65nm CMOS Injection-Locked Frequency Divider," ISSCC Dig. Tech. Papers, pp. 198-596, Feb. 2007
[4] K. Yamamoto and M. Fujishima, "70GHz CMOS Harmonic Injection-Locked Divider," ISSCC Dig. Tech. Papers, pp. 2472-2481, Feb. 2006
[5] C. Chung-Chun, T. Hen-Wai and W. Huei, "Design and Analysis of CMOS Frequency Dividers With Wide Input Locking Ranges," Microwave Theory and Techniques, IEEE Transactions on, vol.57, no.12, pp.3060-3069, Dec. 2009
[6] C.-A. Yu, T.-N. Luo and Y.-J. E. Chen, “A V-Band Divide-by-Four Frequency Divider With Wide Locking Range and Quadrature Outputs,” IEEE Microwaves and Wireless Components Letters, vol.22, no.2, pp.82-84, Feb 2012
[7] Liang Wu; Luong, H.C.; , "A 0.6V 2.2mW 58-to-73GHz divide-by-4 injection-locked frequency divider," Custom Integrated Circuits Conference (CICC), 2012 IEEE , vol., no., pp.1-4, 9-12 Sept. 2012
References
[8] J.Yin, H.C.Luong: “A 57.5-90.1GHz Magnetically-Tuned Multi-Mode CMOS VCO,” in Proc. Custom Integrated Circuits Conference (CICC), Sep. 2012
[9] S.Saberi, J.Paramesh: “A 21-to-54.5GHz Transformer-Coupled Varactorless VCO in 45nm SOI CMOS,” in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2012
[10] M.Nariman, R.Rofougaran, F.D.Flaviis, “A Switched-Capacitor mm-Wave VCO in 65 nm Digital CMOS,” in Proc. RFIC Conf. 2010, May. 23–25,2010, pp. 157–160.
[11] D.Murphy et al.: “A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1606–1617, July 2011
[12] J.Osorio et al.: “A 21.7-to-27.8GHz 2.6-degrees-rms 40mW frequency synthesizer in 45nm CMOS for mm-wave communication applications,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig, Feb. 2011,pp. 278–280
[13] K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, “A 57-to-66 GHz quadrature PLL in 45 nm digital CMOS,” in 2009 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 494–495
[14] O. Richard, A. Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D. Belot, and P. Urard, “A 17.5-to-20.94 GHz and 35-to-41.88 GHz PLL in 65 nm CMOS for wirelessHD applications,” in 2010 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 252–253
References
[15] J. Lee, M. Liu, and H. Wang, “A 75-GHz phase-locked loop in 90-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414–1426, Jun. 2008
[16] C. Marcu, D. Chowdhury, C. Thakkar, J. Park, L. Kong, M. Tabesh, Y. Wang, B. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, E. Alon, and A. M. Niknejad, “A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3434–3447, Dec. 2009
References