REMOTELY PROGRAMMABLE UNIVERSAL INSTITUTION TIMER 2013

INTRODUCTION

The technological advance in the field of electronics has brought more and more sophistication in the domestic and industrial environment. Remotely controlled systems are the demands of the day, which may, not only reduce unwanted human involvement, to switch on and off various machines especially hazardous one. The Remotely Controlled Universal Institution Timer is very attractive and useful system to each and every institution and offices that need to keep time management in their daily routine. This system can control many receivers which are remotely placed and the distance is around 100 Meters.The system has two parts, one is a Transmitter and the other is a receiver. The Transmitter holds a keyboard, a control unit, Display Unit an encoder and a Transmitting antenna. The Receiver unit holds a Receiving antenna, a Decoder, a Central Processing Unit, a Display Unit, a real time clock, power supply and a bell.We are going to design this system in such a way that the transmitter can control as many receivers in its range.

REMOTELY PROGRAMMABLE UNIVERSAL INSTITUTION TIMER

The project named REMOTELY PROGRAMMABLE UNIVERSAL INSTITUTION TIMER is a useful applicable system using 89c51 as its heart It has a built in precision real time clock with a calendar of 100 years. With leap year correction. This ability is provided by a DS 1307 RTC. The equipment can provide 28 bells including 20 short bells and 8 long bells. The most attractive feature of this product is that its receiver did not need any maintenance (it depends up on the leadacid backup battery life) and 1s it is fixed we did no want to bother about that. The equipment will ring the bell with respect to the set time. Even there have no mails supply. The real time clock is displayed on the equipment by the help of a LCD module.The data, about the clock time, bells including short or long can be sent to the receiver wirelessly using a remote technically named transmitter. We can interface with the transmitter using a keyboard that has 5 keys. The transistor is built around an 89c52 mc working in 12MHz clock. And the display of the transmitter displays a menu and the added data.

BLOCK DIAGRAM OF RECEIVER RF RECEIVER

DECODER

Circuit OperationREAL TIME CLOCKDISPLAY UNITMICROCONTROLLER

POWER SUPPLY

ALARM SECTION

Microcontroller The heart of this system microcontroller (C), which performs the arithmetical and logical functions there by steering the performance of peripherals for a full proof and successful performance. It is easy to use an eight bit microcontroller in this section as the system is to handle a sequential operation and is supposed to do only one work at time.Display This section consists of a liquid crystal display. A liquid crystal display (LCD) is a flat panel display electronic visual display, or video display that uses the light modulating properties of liquid crystals. Liquid crystals do not emit light directly. The LCD display is interfacing with a microcontroller.

Real Time Clock(RTC)The DS12885, DS12887, and DS12C887 real-time clocks (RTCs) are designed to be direct replacements for the DS1285 and DS1287. The devices provide a real-time clock/calendar, one time-of-day alarm, three maskable interrupts with a common interrupt output, a programmable square wave, and 114 bytes of battery backed static RAM (113 bytes in the DS12C887 and DS12C887A). The DS12887 integrates a quartz crystal and lithium energy source into a 24-pin encapsulated DIP package. The DS12C887 adds a century byte at address 32h. For all devices, the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. The devices also operate in either 24-hour or 12-hour format with an AM/PM indicator. A precision temperature-compensated circuit monitors the status of VCC. If a primary power failure is detected, the device automatically switches to a backup supply. A lithium coin-cell battery can be connected to the VBAT input pin on the S12885 to maintain time and date operation when primary power is absent. The device is accessed through a multiplexed byte-wide interface, which supports both Intel and Motorola modes.Receiver and EncoderThe receiver section receives the radio frequencies from the transmitter and converts them into the electrical signals. The output of the receiver is connected to the encoder.Bell SectionIt consist of the bell driving circuit using MOFET or transistor. The bell section is enabled by the Microcontroller.Power supply The system requires a regulated voltage of +5v along with an unregulated 12v supply for relay. These low voltages are obtained from the domestic supply with the help of this block.

BLOCK DIAGRAM OF TRANSMITTER

POWER SUPPLYASK TRANSMITTERENCODERDISPLAY UNITMICROCONTROLLERKEYBOARD

Microcontroller The heart of this system microcontroller (C), which performs the arithmetical and logical functions there by steering the performance of peripherals for a full proof and successful performance. It is easy to use an eight bit microcontroller in this section as the system is to handle a sequential operation and is supposed to do only one work at time.

Display This section consists of a liquid crystal display. A liquid crystal display (LCD) is a flat panel display electronic visual display, or video display that uses the light modulating properties of liquid crystals. Liquid crystals do not emit light directly. The LCD display is interfacing with a microcontroller.KeyboardThe keyboard section is used to read the inputs from the user .There are 5 switches for controlling the remote section. The Microcontroller reads the switches directly and makes corresponding HEX data. The Reset switch is used to reset the Microcontroller. There are two switches to give input to the Microcontroller. There is a switch to give multiple inputs. There is a SEND switch to send the whole data to the transmitter section.TransmitterThese section converts the electrical signal from the microcontroller into radio frequency wave and disperse into the air. The input of the transmitter is connected to decoder.

RECEIVER CIRCUIT DIAGRAM

TRANSMITTER CIRCUIT DIAGRAM

POWER SUPPLY

WORKING

Working of each circuit is explained in the circuit design section. The power supply unit energizes the system as soon as the power is switched on. The power on reset circuit reset the program counter in both microcontrollers. The microcontrollers start fetching opcodes from the internal ROM whenever the reset voltage at the reset pin disappears.Through I2C bus and displayed in the LED screen the RTC is backed up by a lithium ion battery. The data is received using ASK module and HT12D decoder. We can set long or short bell as our requirement using the transmitter module. The power supply has a 12 v dc output with a 230 v ac input and it also have the ability to change over to battery when the ac input is failed. When the ac fails a transistor is turned off and releases an EMR to its normally closed position it connect the 12 V sealed lead acid battery to the output and the output is always stable. The change over time is balanced by the capacitors in the circuit. The lead acid battery is charged by receiving a signal from the microcontroller. The signals drive a Darlington transistor pair and active an EMR. It connects the battery to the 12 v dc and starts charging the battery. The charging time is set as 2 hrs in the program. At a prefixed time the signal to charge the battery is generated and after 2 hrs de activated.The regulated 5v is generated at the main circuit using 7805 regulator.The transmitter module built around 89C51 mc. it have a LCD module and a 5 switches to give input the entered data is temporarily stored inside the data memory of the mc. and when we press the send switch the data is transmitted wirelessly using ASK transmitter module to ensure security we use 12th generation encoder named HT 12E.The transmitter (remote) is powered by 9V 6F22 type battery. Using a 7805 regulator IC the 9v is converted in to 5 volts and is given to the MC. The remote have a reset switch that can be also used as a range detector. When we press that it blinks a LED in the receiver only if the receiver is in range.

MICROCONTROLLER

Master ControllerThe 8-bit microcontroller AT89C51 from ATMEL is selected to control the system. This is a 40-pin chip, which contains four input/output ports, 256 bit RAM, and 8Kbyte of the PROM. The power is applied across the Vcc(pin 40) and Gnd(20) pins. The external execution is eliminated by connected to Vcc through a resistor.The AT89C51 is a low-power, high performance CMOS 8-bit microcontroller with 8K bytes of Flash programmable and erasable read only memory(PEROM).The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.The AT89C51 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a sixvector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.

Pin Description

Port 1In receiver circuit the Port 1 is directly connected to the LCD module (D0-D7).The Microcontroller writes data to LCD through these pins. In transmitter circuit the Port 1 is used to interface with the encoder circuits. In transmitter only five pins are used (P1.0-P1.4). The first four pins are DATA pins and the last pin is the TA (Transmission Enable pin).Port 2In receiver circuit the Port 2 is used to interface the microcontroller with the RTC module and to drive the bell circuit. P2.4 and P2.5 are used as SCL (Serial Clock) and SDA (Serial Data) of the RTC respectively. P2.6 is used to drive the bell circuit and P2.7 is used as a range indicator. In transmitter the Port 2 is used to read input from the keyboard circuit and also to drive the LCD display.

Port 3In receiver circuit Port 3 is used to drive the LCD display and to read the received information from the decoder circuit. P3.4 to P3.7 is used to read data from the decoder and P3.3 is used as VT (Valid Transmission). In transmitter circuit the Port 3 is used to write data to the LCD module. Port PinAlternate Functions

P3.0RXD (serial input port)

P3.1TXD (serial output port)

P3.2INT0(external interrupt 0)

P3.3INT1(external interrupt 1)

P3.4TO(timer 0 external input)

P3.5T1(timer 1 external input)

P3.6WR(external data memory write strobe)

P3.7RD(external data memory read strobe)

RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable is an output pulse for latching the low byte of the address during access to external memory. This pin is also the program pulse input (PROG) during Flash programming.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt is selected.XTAL1:- Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:-Output from the inverting oscillator amplifier.Clock InputsThe X1 and X2 inputs are connected to the ends of a piezo electric crystal. We can choose the crystal frequency from 1 MHz to 24MHz.Also both of the crystal inputs are connected to ground through capacitors of value 33pF.Reset InputsThe reset pin is connected to a power on circuit. The capacitor voltage at the time of power on will be 1.This will reset microcontroller. The voltage drops to zero shortly after some time. This will remove the reset condition and the microcontroller will start fetching now.

Real Time Clock (RTC)-DS1307

The DS1307 serial real-time clock (RTC) is a low-power, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially through an I2C, bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12- hour format with AM/PM indicator. The DS1307 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply. Timekeeping operation continues while the part operates from the backup supply.

FEATURES Real Time Clock (RTC) Counts, Seconds,Minutes,Hour,Date of the Month, Month,and Day of the week. and year with Leap Year 56-Byte, Battery-Backed, General-Purpose RAM with Unlimited Writes I2C Serial Interface Programmable Square-Wave Output Signal Automatic Power-Fail Detect and Switch Circuitry Consumes Less than 500nA in Battery-Backup Mode with Oscillator Running Optional Industrial Temperature Range: -40C to +85C Available in 8-Pin Plastic DIP or SO Underwriters Laboratories (UL) Recognized

WORKINGThe DS1307 is a low-power clock/calendar with 56 bytes of battery-backed SRAM. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The DS1307 operates as a slave device on the I2C bus. Access is obtained by implementing a START condition and providing a device identification code followed by a register address. Subsequent registers can be accessed sequentially until a STOP condition is executed. When VCC falls below 1.25 x VBAT, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. When VCC falls below VBAT, the device switches into a low-current battery-backup mode. Upon power-up, the device switches from battery to VCC when VCC is greater than VBAT +0.2V and recognizes inputs when VCC is greater than 1.25 x VBAT. The block diagram in Figure 1 shows the main elements of the serial RTC.

OSCILLATOR CIRCUIT The DS1307 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.RTC AND RAM ADDRESS MAPTable 2 shows the address map for the DS1307 RTC and RAM registers. The RTC registers are located in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multi-byte access, when the address pointer reaches 3Fh, the end of RAM space, it wraps around to location 00h, the beginning of the clock space.CLOCK AND CALENDAR The time and calendar information is obtained by reading the appropriate register bytes. Table 2 shows the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the BCD format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.) Illogical time and date entries result in undefined operation. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. On first application of power to the device the time and date registers are typically reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS). The CH bit in the seconds register will be set to a 1. The clock can be halted whenever the timekeeping functions are not required, which minimizes current (IBATDR). The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). The hours value must be re-entered whenever the 12/24-hour mode bit is changed. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any I2C START. The time information is read from these secondary registers while the clock continues to run. This eliminates the need to re-read the registers in case the internal registers update during a read. The divider chain is reset whenever the seconds register is written. Write transfers occur on the I2C acknowledge from the DS1307. Once the divider chain is reset, to avoid rollover issues, the remaining time and date registers must be written within one second.

Timekeeper Registers

I2C DATA BUS The DS1307 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1307 operates as a slave on the I2C bus.

Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH. START data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. STOP data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the I2C bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1307 operates in the standard mode (100kHz) only. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

The DS1307 can operate in the following two modes:

1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit (see Figure 4). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1307 address, which is 1101000, followed by the direction bit (R/W), which for a write is 0. After receiving and decoding the slave address byte, the DS1307 outputs an acknowledge on SDA. After the DS1307 acknowledges the slave address + write bit, the master transmits a word address to the DS1307. This sets the register pointer on the DS1307, with the DS1307 acknowledging the transfer. The master can then transmit zero or more bytes of data with the DS1307 acknowledging each byte received. The register pointer automatically increments after each data byte are written. The master will generate a STOP condition to terminate the data write.

2. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. The DS1307 transmits serial data on SDA while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (see Figure 5). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1307 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address the DS1307 outputs an acknowledge on SDA. The DS1307 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The register pointer automatically increments after each byte are read. The DS1307 must receive a Not Acknowledge to end a read.

Data WriteSlave Receiver Mode

Data ReadSlave Transmitter Mode

212 SERIES OF ENCODER (HT12E)The 212 encoders are a series of CMOS LSIs for remote control system applications. They are capable of encoding information which consists of N address bits and 12N data bits. Each address/ data input can be set to one of the two logic states. The programmed addresses/data are transmitted together with the header bits via an RF or an infrared transmission medium upon receipt of a trigger signal. The capability to select a TE trigger on the HT12E or a DATA trigger on the HT12A further enhances the application flexibility of the 212 series of encoders. The HT12A additionally provides a 38 kHz carrier for infrared systems.FEATURES Operating voltage 2.4V~5V for the HT12A 2.4V~12V for the HT12E Low power and high noise immunity CMOS technology Low standby current: 0.1_A (typ.) at VDD=5V HT12A with a 38kHz carrier for infrared transmission medium Minimum transmission word Four words for the HT12E One word for the HT12A Built-in oscillator needs only 5% resistor Data code has positive polarity Minimal external components HT12A/E: 18-pin DIP/20-pin SOP package Minimum transmission word Four words for the HT12E One word for the HT12A Built-in oscillator needs only 5% resistor Data code has positive polarity Minimal external components HT12A/E: 18-pin DIP/20-pin SOP package

BLOCK DIAGRAM

PIN DIAGRAM

PIN DESCRIPTION

Pin NameI/OInternal connectionDescription

A0~A7

ICMOS INPull-high(HT12A)

Input pins for address A0~A7 settingThese pins can be externally set to VSS or left open

NMOSTRANSMISSIONGATEPROTECTIONDIODE(HT12E)

AD8~AD11

INMOSTRANSMISSIONGATEPROTECTIONDIODE(HT12E)Input pins for address/data AD8~AD11 settingThese pins can be externally set to VSS or left open

D8~D11ICMOS INPull-highInput pins for data D8~D11 setting and transmission enable, active lowThese pins should be externally set to VSS or left open

DOUTOCMOS OUTEncoder data serial transmission output

L/MBICMOS INPull-highLatch/Momentary transmission format selection pin:Latch: Floating or VDDMomentary: VSS

TEICMOS INPull-highTransmission enable, active low

OSC1IOSCILLATOR 1Oscillator input pin

OSC2OOSCILLATOR 1Oscillator output pin

X1IOSCILLATOR 2455kHz resonator oscillator input

X2OOSCILLATOR 2455kHz resonator oscillator output

VSS I___Negative power supply, grounds

VDDI___Positive power supply

FUNCTIONAL DESCRIPTIONOPERATIONThe 212 series of encoders begin a 4-word transmission cycle upon receipt of a transmission enable(TE for the HT12E or D8~D11 for the HT12A, active low). This cycle will repeat itself as long as theTransmission enable (TE or D8~D11) is held low. Once the transmissions enable returns high the encoder output completes its final cycle and then stops as shown below.

Information wordIf L/MB=1 the device is in the latch mode (for use with the latch type of data decoders). When the transmission enable is removed during a transmission, the DOUT pin outputs a complete word and then stops. On the other hand, if L/MB=0 the device is in the momentary mode (for use with the momentary type of data decoders). When the transmission enable is removed during a transmission, the DOUT outputs a complete word and then adds 7 words all with the _1_ data code.An information word consists of 4 periods as illustrated below.

Address/data waveformEach programmable address/data pin can be externally set to one of the following two logic states asshown below.

HT12D/HT12F 212 SERIES OF DECODERS

The 212 decoders are a series of CMOS LSIs for remote control system applications. They are paired with Holteks 212 series of encoders (refer to the encoder/decoder cross reference table). For proper operation, a pair of encoder/decoder with the same number of addresses and data format should be chosen. The decoders receive serial addresses and data from a programmed 212 series of encoders that are transmitted by a carrier using an RF or an IR transmission medium. They compare the serial input data three times continuously with their local addresses. If no error or unmatched codes are found, the input data codes are decoded and then transferred to the output pins. The VT pin also goes high to indicate a valid transmission. The 212 series of decoders are capable of decoding informations that consist of N bits of address and 12_N bits of data. Of this series, the HT12D is arranged to provide 8 address bits and 4 data bits, and HT12F is used to decode 12 bits of address information

Features Operating voltage: 2.4V~12V Low power and high noise immunity CMOStechnology Low standby current Capable of decoding 12 bits of information Binary address setting Received codes are checked 3 times Address/Data number combination HT12D: 8 address bits and 4 data bits HT12F: 12 address bits only Built-in oscillator needs only 5% resistor Valid transmission indicator Easy interface with an RF or an infrared transmissionmedium Minimal external components Pair with Holtek_s 212 series of encoders 18-pin DIP, 20-pin SOP packageBLOCK DIAGRAM

PIN DISCRIPTION

FUNCTIONAL DESCRIPTION

OperationThe 212 series of decoders provides various combinations of addresses and data pins in different packages so as to pair with the 212 series of encoders. The decoders receive data that are transmitted by an encoder and interpret the first N bits of code period as addresses and the last 2_N bits as data, where N is the address code number. A signal on the DIN pin activates the oscillator which in turn decodes the incoming address and data. The decoders will then check the received address three times continuously. If the received address codes all match the contents of the decoders local address, the 12_N bits of data are decoded to activate the output pins and the VT pin is set high to indicate a valid transmission. This will last unless the address code is incorrect or no signal is received. The output of the VT pin is high only when the transmission is valid. Otherwise it is always low. Output type of the 212 series of decoders, the HT12F has no data output pin but its VT pin can be used as a momentary data output. The HT12D, on the other hand, provides 4 latch type data pins whose data remain unchanged until new data are received.

ASK DATA TRANSMITTER AND RECEIVERRX-433A1 transmitter and receiver pair is a low cost solution for radio wireless control application circuits. Operating at 433MHz ISM frequencies this low power radio system has a remote operating reach of more than 100 Meters in open field (125 meters/370 ft being typical). The control distance can be stretched to 175meters, if short temporary disconnections due to RF signal drop outs can be tolerated.RF-433A1-T TRANSMITTER CIRCUITThe transmitter module is based on Micrels UHF transmitter MICRF113. This is a very stable UHF oscillator locked to a crystal frequency. It is capable of delivering RF output of up to 10dbm, although in our circuit, actual RF output is about 3 to 4dB less because of external components influence.The transmitter is ASK pulse modulated by applying LVTTL level pulses at the TXIN input. TXIN input is nonlinear. Basically, what the input pulses does is turn ON and OFF the transmitter at a succession to effect ASK transmission.

The transmitter module is crystal locked in frequency, ensuring a stable and more reliable transmitting function. All external components are fixed in value. Nothing can be accidentally detuned. Frequency Range: 433.92 MHZ Modulate Mode: ASK Circuit Shape: LC Date Rate: 4800 bps Selectivity: -106 dB Channel Spacing: 1MHZ Supply Voltage: 5V High Sensitivity Passive Design. Simple To Apply with Low External Count.

DC CHARECTERISTICS

INTERFACE PORT P1

The transmitter module component layout. A stranded core insulated wire cut to 17cm in length can be used as an antenna.

RX-433A1-R RECEIVER CIRCUIT

The receiver module is built around ATA3741, a UHF receiver circuit capable of demodulating either an ASK or FSK signal. The receiver frequency is likewise crystal locked to keep the frequencyfrom wandering off and getting out of tune with the transmitter. The output of the ATA3741 is already in the form of digital pulses. But as it is, it is not ready for use. As I already mentioned, we could expect a data output mixed with all sorts of noise. Hence, to ensure successful data transfer, the receiver hosts MCU need something it could easily recognize from noise to get it start processing of reception dataand deal with the separation of data from noise more effectively. For this, the data packet is sendby the transmitting device with extra payloads for synchronization and error detection. The payload depends on the protocol used. Following is the scary detail. VirtualWire starts transmission by sending a series of synchronization pulses, 18 pairs of 1 and 0s to be exact. The hosts MCU running the VirtualWire reception routine continuously checks for this sync pulses, and will only start processing upon the detection of sync signal. The sync pulses are immediately followed by a start marker - a 12bitpulse pattern, the number of bytes to transmit, and the data stream itself. Transmission is concludedwith a 4 byte CRC that must be used by the host controller to validate the data. All data after the start marker are encoded in 4b/6b format in order not the upset the DC bias of the ATA3741 receiver PLL circuit. Any undesired C bias within the PLL control loop will almost guarantee a data lost. Fortunately for Arduino and gizDuino programmers, you need not worry about these details. Every complicated thing just mentioned had already been taken cared of by the VirtualWire library, so that you dont have to. It is a free Arduino IDE add-onlibrary that can work with RX-433A1 wireless hardware. If you havent done so, now is the good time to download this library. Users of non-Arduino compatible platform/MCUs are not as lucky, and may have to do the dirty work themselves.

RX-4331A R Receiver Module Schematic diagram

P1 INTERFACE PORT

.

EGRF-433A1-R Receiver Module components layout

LCD CONTROLLER/DRIVER

The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. A single HD44780U can display up to one 8-character line or two 8-character lines.The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace an LCD-II with an HD44780U. The HD44780U character generator ROM is extended to generate 208 5 8 dot character fonts and 32 5 10 dot character fonts for a total of 240 different character fonts. The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any portable battery-driven product requiring low power dissipation.Features 5 8 and 5 10 dot matrix possible Low power operation support: 2.7 to 5.5V Wide range of liquid crystal display driver power 3.0 to 11V Liquid crystal drive waveform A (One line frequency AC waveform) Correspond to high speed MPU bus interface 2 MHz (when VCC = 5V) 4-bit or 8-bit MPU interface enabled 80 8-bit display RAM (80 characters max.) 9,920-bit character generator ROM for a total of 240 character fonts 208 character fonts (5x8 dot) 32 character fonts (5x10 dot) 64x8-bit character generator RAM 8 character fonts (5x8 dot) 4 character fonts (5x10 dot) 16-common 40-segment liquid crystal display driver Programmable duty cycles 1/8 for one line of 5x 8 dots with cursor 1/11 for one line of 5x10 dots with cursor 1/16 for two lines of 5x8 dots with cursor Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift Automatic reset circuit that initializes the controller/driver after power on Internal oscillator with external resistors Low power consumption

HD44780U BLOCK DIAGRAM

HD44780U-PIN FUNCTIONS

SignalNo: of LinesI/ODevice Interfaced withFunction

RS1IMPUSelects registers.0: Instruction register (for write) Busy flag:address counter (for read)1: Data register (for write and read)

R/W1IMPUSelects read or write.0: Write1: Read

E1IMPUStarts data read/write

DB4 TO DB74I/OMPUFour high order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U. DB7 can be used as a busy flag.

DB0 to DB34I/OMPUFour low order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U.These pins are not used during 4-bit operation.

CL11OExtension driverClock to latch serial data D sent to the extensionDriver

CL21OExtension driverClock to shift serial data D

M1OExtension driverSwitch signal for converting the liquid crystaldrive waveform to AC

D1OExtension driverSwitch signal for converting the liquid crystaldrive waveform to AC

COM1 to COM1616OLCDSegment Signals

SEG1 to SEG4040OLCDSegment Signals

V1 to V55_Power SupplyPower supply for LCD driveVCC V5 = 11 V (max)

VCC, GND2_Power SupplyVCC: 2.7V to 5.5V, GND: 0V

OSC1, OSC22_Oscillationresistor clockWhen crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1.

Instructions

Clear DisplayClear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1 (increment mode) in entry mode. S of entry mode does not change.Return HomeReturn home sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. The DDRAM contents do not change.The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed).Entry Mode SetI/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read from DDRAM.The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1.The same applies to writing and reading of CGRAM.S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1. The display does not shift if S is 0.If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when reading from DDRAM.Also, writing into or reading out from CGRAM does not shift the display.Display On/Off ControlD: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, butcan be displayed instantly by setting D to 1.C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, thefunction of I/D or other specifications will not change during display data write. The cursor is displayedusing 5 dots in the 8th line for 5x8 dot character font selection and in the 11th line for the 5x10 dotcharacter font selection.B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed asswitching between all blank dots and displayed characters at a speed of 409.6-ms intervals when fCP or fOSCis 250 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changesaccording to fOSC or the reciprocal of fCP. For example, when fCPis 270 kHz, 409.6x250/270 = 379.2 ms)Cursor or Display ShiftCursor or display shift shifts the cursor position or display to the right or left without writing or readingdisplay data (Table 7). This function is used to correct or search the display. In a 2-line display, the cursormoves to the second line when it passes the 40th digit of the first line. Note that the first and second linedisplays will shift at the same time.When the displayed data is shifted repeatedly each line moves only horizontally. The second line displaydoes not shift into the first line position.The address counter (AC) contents will not change if the only action performed is a display shift.Function SetDL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1,and in 4-bit lengths (DB7 to DB4) when DL is 0.When 4-bit length is selected, data must be sent orreceived twice.N: Sets the number of display lines.F: Sets the character font.Set CGRAM AddressSet CGRAM address sets the CGRAM address binary AAAAAA into the address counter.Data is then written to or read from the MPU for CGRAM.Set DDRAM AddressSet DDRAM address sets the DDRAM address binary AAAAAAA into the address counter.Data is then written to or read from the MPU for DDRAM.However, when N is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 (2-line display),AAAAAAA can be 00H to 27H for the first line and 40H to 67H for the second line.Read Busy Flag and AddressRead busy flag and address reads the busy flag (BF) indicating that the system is now internally operatingon a previously received instruction. If BF is 1, the internal operation is in progress. The next instructionwill not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the sametime, the value of the address counter in binary AAAAAAA is read out. This address counter is used byboth CG and DDRAM addresses, and its value is determined by the previous instruction. The addresscontents are the same as for instructions set CGRAM address and set DDRAM address.Read Data from CG or DDRAMRead data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM. The previous designation determines whether CG or DDRAM is to be read. Before entering this read instruction, either CGRAM or DDRAM address set instruction must be executed. If not executed, the first read data will be invalid. When serially executing read instructions, the next address data is normally read from the second read. The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out DDRAM). The operation of the cursor shift instruction is the same as the set DDRAM address instruction. After a read, the entry mode automatically increases or decreases the address by 1. However, display shift is not executed regardless of the entry mode.

PCB Fabrication

The first step of assembling is to procure a printed circuit board. The fabrication of the program counter plays a crucial role in the electronic field. We are using a microcontroller-based system that handles high frequencies. In the high frequency circuit the data may easily be violated in the PCB due to the physical parameters. That is the track capacitance and inductance can cause the cross talk in the buses. Also, unwanted noise can be induced to supply rails and from there it can affect the total response. Hence, the PCB design has a major role in the system performance. The board is designed using a personal computer. The layout is drawn using the software Proteus. The layout is printed in a butter sheet using a laser printer. The layout is transferred to the copper clad sheet using the screen print procedure. First, a negative screen of the layout is prepared with the help of a professional screen printer. Then the copper clad sheet is kept under this screen. The screen printing ink is pored on the screen and brushed through the top of the screen. The printed board is kept under shade for few hours till the ink become dry.The etching medium is prepared with the un-hydrous ferric chloride and water. The printed board is kept in this solution till the exposed copper dissolves in the solution fully. After that the board is taken out and rinsed in the flowing water under a tap. The ink is removed with the help of NC thinner. The board is coated with solder in order prevent oxidation. Another screen, which contains component side layout, is prepared and the same is printed on the component side of the board. A paper epoxy laminate is used as the board. Both component and the track layout of the peripheral PCB is given below.

Components layout of transmitter

PCB layout of transmitter

Components layout of encoder

PCB layout of encoder

Components layout of keyboard

PCB layout of keyboard

Components layout of receiver

PCB layout of receiver

Components layout of decoder

PCB layout of decoder

Components layout of power supply

PCB layout of power supplyPROGRAM SECTION

START

LCD Initialization

Main Menu Display

While(1)

yes Yes No No No yesHour Key==1Min Key==1Next key==1Reset Key==1

No

Minute++Hour++

NoSend key

YesSending message

Send DATA to transmitter

//TRANSMITTER PROGRAM

#include

#define LCD P3#define DATA P1

sbit RS=P2^5; //connect p2.5 to rs pin of lcdsbit EN=P2^7; //connect p2.7 to en pin of lcdsbit RW=P2^6; //connect p2.6 to en pin of lcd

sbit TE=P1^4; //transmission enable

char DecimalToBCD(unsigned char);

void init_lcd(void);void cmd_lcd(unsigned char);void write_lcd(unsigned char);void display_lcd(unsigned char *);void delay_ms(unsigned int);

void alarm();void settime();void process();void send(unsigned char);void longbell();void hr(int);void mn(int,unsigned char);void hrmn();void disp(unsigned char);void keys(int,int,unsigned char);void aa();void reset();

unsigned char *s[];unsigned char c,a1,a2,h,m,d;unsigned int j=0,i=0,mode=0,a=0,b=1,f=1,e=0;unsigned char arr[40];

void main(void)

{start:DATA=0xFF;TE=1;e=0;a1=0x00,a2=0x00;init_lcd();//MAIN MENUcmd_lcd(0x01);display_lcd(" *REALTRONICS*");delay_ms(300);cmd_lcd(0x01);display_lcd("1 CLOCK 2 ALARM");cmd_lcd(0xc0);display_lcd("3 LONGBELL");while(1){while((P2&0x10)==0) //Reset Key 1{TE=0;DATA=0x0D;delay_ms(100);goto start;}while((P2&0x02)==0) //Key 2{e=1;}while((P2&0x04)==0) //Key 3{e=2;}while((P2&0x01)==0) //Key 4{e=3;}switch(e){case 1:settime();break;case 2: alarm();break;case 3: longbell();break;}}}// END OF MAIN

void delay_ms(unsigned int i) //Delay function

{unsigned int j; while(i-->0) { for(j=0;j