Instruction Enhancement Programme (IEP)

on

“Introduction to Analog and

Digital VLSI Design”

LAB MANUAL FOR ANALOG LAB 1

Department of Electronics and Electrical Engineering

Indian Institute of Technology Guwahati.

ANALOG LAB 1: MOSFET DC and small signal characteristics (and CS amplifier).

AIM

The aim of the experiment is to study the MOSFET device characteristics and to extract the related

model parameters along with finding the voltage gain of common source (CS) amplifier with

resistive load.

STEPS:

Introduction to Pyxis tool.

Plot IDS vs VGS for different values of VDS.

Plot gm variation vs VGS and extraction of model parameters Vth, kn, rds.

Plot gm/IDS variation vs VGS for VDS=VDD/2.

Plot IDS vs VDS for different values of VGS.

Plot CGCS variation vs VGS.

Plot for voltage gain of common source (CS) amplifier with resistive load.

STEP 1: Introduction to Pyxis tool

Pyxis is a leading CAD/EDA tool form Mentor Graphics. Pyxis is a tool for creating schematic

and layout. It can be used to simulate gate level and transistor level circuits.

Prerequisites

A basic understanding of CMOS technology.

A basic understanding of VLSI fabrication flow.

Technology file corresponding to the desired technology.

A) Open Mentor Graphics Pyxis Schematic

Login into a linux system, right click and go to Open terminal option and then type following

commands.

→ csh (for a c shell terminal)

→ source mentor.cshrc

. cshrc is a c shell startup configuration file. This file is found in a user's home directory and contain

shell and other commands to set variables, define aliases, and perform any other initialisation

which should happen for every shell (as opposed to .login which is only run for a login shell).

Then, type the following command to open pyxis schematic window.

→ adk_daic

B) Creating a Schematic in Pyxis Schematic

Go to file → New → Schematic (or Ctrl+N), following window should pop up

Click on New Directory icon and give name to your directory → Click OK

Open your directory and give name to your schematic → Click OK

After above steps, following Pyxis schematic window should show up.

C) Drawing Schematic

Adding Components: To add components to your schematic go to ADK IC Library under

schematic toolbar in the right side. After clicking ADK IC Library, choose appropriate components

required for your schematic (For example, in this lab we need NMOS which we can choose from

Transistor toolbar).

Click wherever you want to place it. Similarly, add all (DC source, VDD, GND, IN and OUT

port etc.) the components from the library required to complete the schematic.

For making interconnections click on the nodes which you want to connect.

D) Edit Object and Sizing of MOSFET

Click on the gate → press q to get following window.

Scroll down to length and width to set required L and W for the gate. For example, L=0.18 and

W=0.36. By pressing q over any component, we can edit its parameters.

E) Check and save

F) Analysis

Click on Setup Simulation icon if there are no errors faced during check and save.

Including model file

Click on Set up simulation icon in left side toolbar. Then, click on “Includes” icon to include model

file. Type $ADK/technology/ic/models and select tsmc018.mod (for 180 nm technology) and

finally click on Apply icon in end of scrollbar.

Applying signals:

Select Forces (to force various dc voltages in the schematic like VDD, IN etc.) → Select the

branches where you want to force, for example VDD. Go to Setup Simulation window→ Source

type (for example DC) → enter magnitude for the selected source (like VDD=1.8V) → Add.

Setting output variable

Click outputs→ Select from schematic (node for current and branch for voltage). For example,

for MN1 has been highlighted (white) in the following figure.

Open Setup Simulation→ in Task select PLOT

Click Add and then Apply.

Analysis 1: DC Analysis

Click Analysis→ Select DC → Sweep type (select Source)

Click on select source icon (highlighted in following figure) →from schematic, select the input

which you want to sweep (Here, /V2 which is Vgs has been selected). Accordingly, set the start,

stop and step values and then click on Apply.

Run Simulator to perform the analysis: Click on Run Simulator (shown with green arrow symbol

in the left side toolbar in the following figure)

After running the simulator, there should be zero error in log window. To view complete log Click

the highlighted icon→ View Complete Log.

Plotting the waveform:

Click the highlighted icon→ click plot

After clicking plot, the following window should pop up

In Ezwave window, from currently opened databases, select the one with the schematic name→

select DC → parameter to be plotted (for example ID)

To change the properties of waveform, right click on the plot and go to “properties” to edit.

After editing X and Y axis, we have following figure

We can also add one or more curser to know the data points at any instance

Saving the waveform:

Click on file→ Export.

Give appropriate file name to save.

STEP 2: Plot of IDS vs VGS L=180 nm and W=360 nm for different values of VDS.

Basic theory and equations needed for designing and calculating parameters is summarized as

follows:

A NMOS transistor has four terminals the gate, drain, source and body or substrate. In nearly all

practical applications we connect the substrate of the NMOS to the most negative supply in the

system. This effectively makes the device a three terminal one. The NMOS transistor has three

regions of operation:

Cutoff: When VGS is not large enough to cause the formation of a channel the device is in cutoff.

Irrespective of the VDS value applied no current can flow between the drain and source. The critical

value of VGS which results in the formation of a channel (induced n region) for current flow from

drain to source is called the threshold voltage thV . As VGS has to be increased beyond a threshold

value thV , to enhance the number of carriers in the channel it is called an enhancement MOSFET.

Linear Region: Let GS thV V and a small VDS is applied between drain and source. The VGS value

results in an n-channel and the VDS value results in a current DSI to flow from drain to source

through the induced channel. The current depends on the density of electrons in the channel which

depends on the applied VGS voltage. If – DS GS thV V V , the device is said to be operating in the

triode or linear region and the drain current is given by the following equation

(1)

With VDS kept small the MOSFET behaves like a linear resistor whose value is controlled by VGS.

Saturation Region: When – DS GS thV V V and > GS thV V , the current no longer is a straight line

rather it theoretically saturates at this value. This happens because at certain points in the channel

region, the local potential difference between the gate and the oxide-silicon interface will be less

than the threshold. This occurs when – ( ) GS thV V x V where ( )V x is the voltage in the channel.

In these regions the channel disappears or is said to be pinched off. So, the channel no longer

reaches the drain. The current equation is now given by

21

2DS n ox GS th

WI C V V

L … (2)

The voltage VDS at which saturation occurs is given by:

= – satDS GS thV V V … (3)

2

2

DSDS n ox GS th DS

VWI C V V V

L

Channel Length Modulation: At pinch-off and beyond (increasing potential difference between

gate and drain) the actual length of the channel is no longer L. The modified channel length L ' is

a function of VDS and using a first order approximation, the current equation in saturation is

21

12

DS n o Sx S t DG h

WI C V V V

L … (4)

Here, is the channel length modulation coefficient. This results in current being no longer

constant in the saturation region but having dependence on VDS in the saturation region. is an

empirical parameter and 1

L .

We can express resistance between drain and source by following equation

2

1 1

1

2DS DS

n ox GS t

DS

h

rdsWd

d

I IC V V

V

L

… (5)

PMOS TRANSISTOR

Like the nmos transistor the PMOS TRANSISTOR is also effectively a 3 terminal device as the

substrate is typically connected to the most positive supply in the system. The device operation is

the same as in the nmos case except that GSV , DSV and the threshold voltage thV are negative. Also

the current DSI enters the source terminal and leaves through the drain terminal. As the current

direction is opposite to that of the nmos transistor by convention the values obtained for DSI will

be negative. Hence, the three regions of operation of the pmos can be summarized as follows

Cut off region: > GS thV V … (6)

Linear region:

2

<

> –

2

GS thp

DS GS thp

DSDS p ox GS thp DS

VWI C V V V

L

V V

V V V

…. (7)

Saturation region:

21

2

<

–

GS thp

DS GS th

DS p ox

p

GS thp

W

V V

V

I C V

V V

VL

… (8)

Considering channel length modulation, drain current can be written as

21

12

DS p ox GS thp DS

WV VI C V

L …. (9)

Go to Set up simulation → click on “Params/Sweeps” in simulation panel→ Click on Instance.

Then bring the curser on the schematic and click on the component whose values need to be swept.

Set the values for start, stop and increment by after selecting “Range” option→ Add→ Apply.

After clicking on “Run simulator” and plot option, Ezwave window will pop-up. Then following

previous instruction, we can have different plots of IDS vs VGS for different values of VDS as shown

in following figure.

STEP 3: Plot gm variation vs VGS for L=180 nm, W=360 nm and extraction of model

parameters Vth, kn, rds.

A figure of merit is defined to indicate how well the device converts the voltage to current. A

MOSFET in saturation produces a current in response to its gate source overdrive voltage

GS thV V and we define the transconductance, mg as follows

DSm

GS

dIg

dV Keeping DSV as constant … (10)

m n ox GS th

Wg C V V

L for NMOS …(11)

m p ox GS thp

Wg C V V

L for PMOS … (12)

gm represents the sensitivity of the device. So for a high gm, a small change in GSV results in a large

change in DSI . Also, thV is defined as the gate voltage at which the derivative of the

transconductance, GS

mdg

dV, is maximum.

Using waveform calculator, we can differentiate IDS w.r.t VGS to get transconductance, mg as

shown in following figures.

Again, using waveform calculator, we can differentiate mg plot w.r.t VGS to extract threshold

voltage Vth which is the gate voltage (VGS) value corresponding for maximum value in m

GS

dg

dV plot.

Using drain current equations for saturation region and the data points from the following plot, we

can also calculate the values of parameters like kn, rds.

From the above plot, m

GS

dg

dV, is maximum for GSV = 0.55 V. Hence, thV = 0.55 V. Also, we find that

mg = 243 S and DSI = 225 A for GSV =1.6 V.

For, GSV =1.6 V, 1.6 0.55 1.05GS thV V V < 0.9DSV V, the device is in saturation. Using,

the ideal first order saturation current equation from (2), we can calculate nn oxK C as follows

21

2DS n ox GS th

WI C V V

L

21 0.36

225 1.6 0.552 0.18

n oxA C

Which gives nn oxK C = 204 2

A

V

.

Plot of log (IDS) vs VGS can also be plotted using waveform calculator as shown in following figure.

STEP 4: Plot gm/IDS variation vs VGS for VDS=VDD/2.

Dividing gm plot with IDS plot in the waveform calculator and selecting /V1=0.9 V plot, we can

easily plot gm/IDS variation vs VGS for VDS=VDD/2 as shown below.

STEP 5: Plot of IDS vs VDS for different values of VGS.

Following the same steps as done in STEP 2, by selecting /V1 (VGS) as Instance in the

“Params/Sweeps” section and setting required values, we can plot Plot of IDS vs VDS for different

values of VGS as shown below.

Using waveform calculator, we can plot for DS

DS

dI

dV and inverse of the plot can give DS

ds

DS

dVr

dI .

Here, dsr value comes near 177 K for 0.6DSV V .

STEP 6: Plot CGCS variation vs VGS. We will use following circuit for plotting gate-channel capacitance variation with VGS. Here, a DC current source of 1 nA has been used with a very high resistance connected between source and drain.

TRANSIENT Analysis:

For this experiment, we will perform transient analysis of the given circuit. Go to “Analysis” tab in Set up simulation toolbar as before. Check the TRAN option and also check the “Enable TRAN”. Set the values for start and stop time and also Max. Time step. (For example, we have taken start time as 0 s, stop time as 5 µs and Max. Time step as 100 ns). If Max. Time Step is taken in ps, the simulation may take a long time to get completed. Finally, click on “Apply” as shown below.

Set the output variables by clicking on the NMOS (MN1) and the gate node (N$2) for analyzing gate current and gate-to-source voltage variation as shown below.

Run simulator. Click on I (G) and V (N$2) to get the following graph.

We know the expression for current through a capacitor as c

dVI C

dt . Using, this equation, we can

find the gate-channel capacitance plot. Use waveform calculator to get dV

dtplot as shown below.

Divide the resultant plot by current plot to get the following plot for capacitance variation with time.

To get capacitance variation with gate-source voltage, bring both graphs together as shown in following figure.

To get the plot for capacitance variation with gate-source voltage, right click and set voltage plot as X axis by clicking on “Set as X axis” option as shown below.

We get final plot of nmos parasitic capacitance variation with gate voltage as follows

STEP 7: Plot for voltage gain of common source (CS) amplifier with resistive load

For this experiment, we have following parameters given:

Technology: tsmc018 technology, 0.2DS ovV V V ,L=180 nm and W=360 nm.

Following circuit is used to implement this experiment.

Design steps are as follows:

Since we consider NMOS to be in saturation, we can use drain current equation from (2) as

21

2DS n ox GS th

WI C V V

L

Here, let us assume 320n oxC 2/A V and 0.2DS ovV V V

We get 12.8DSI A

Now, the value of resistor is 125DD ov

DS

V VR K

I

.

After, designing part, we will go for AC analysis.

AC Analysis:

Go to Set up simulation and select “Analysis”, then click on AC in Analysis selector and click on

Enable AC. Set start and stop frequency.

Then go to “Forces”, select the component from the schematic by clicking on it. Click on AC

option in Source Type and set the values of DC and AC magnitude. DC magnitude is set for biasing

the transistor in the required region of operation and AC magnitude is set for small-signal input to

verify the gain of the CS amplifier. For example, here we set DC magnitude of 0.63 V to set the

NMOS in saturation region and we set AC magnitude as 0.0002 V.

Then we set the output variable as done earlier by clicking in “Outputs” and following rest steps

as before. Set the Magnitude (dB) to get the voltage outputs in dB.

Click on Run simulator for simulation.

Go to plot.

Following window will pop-up.

Click on AC to see the waveforms for input and output voltage in dB as shown in following

figure.

Using waveform calculator, get the gain plot by subtracting the ( )outV dB plot from ( )inV dB in dB

as follows.

The gain plot is as follows. Here, we get a gain of near 20 dB.

Save the gain plot using the “Export” option and following the previous steps.

Assignments:

1. Simulate all above steps for NMOS transistor for L=250 nm, W=500 nm and L=350 nm,

W=700 nm.

2. Simulate all above steps for PMOS transistor for L=180 nm and W=360 nm.