Instruction Set Architecture

Part 2

Mehran Rezaei

2

This week

• Review and Register Naming Convention

• MIPS Arithmetic, Load/store and logical instructions

• slt and jr instructions

• Branches and jumps

• pc – relative addressing

3

Review

• Execution Cycle

• Levels of Computer Languages

• Stored Program Computer/Instruction Execution Cycle

• SPIM, a MIPS Interpreter

• MIPS and Register File

• Register Naming convention

4

Naming Convention for registers

0 zero constant 0

1 at reserved for assembler

2 v0 expression evaluation &

3 v1 function results

4 a0 arguments

5 a1

6 a2

7 a3

8 t0 temporary: caller saves

. . . (callee can clobber)

15 t7

16 s0 callee saves

. . . (caller can clobber)

23 s7

24 t8 temporary (cont’d)

25 t9

26 k0 reserved for OS kernel

27 k1

28 gp Pointer to global area

29 sp Stack pointer

30 fp frame pointer

31 ra Return Address (HW)

5

Example

• Compile

A[20] += A[8]; address of A[0] is in $s1

6

Anatomy of data transfer inst.

lw $t0, 5($s1)

offset

Base registerIndex register (why?)

7

Translate to machine code

A[20] +=A[8];

Instructions, so far

8

Shifters

Two kinds:

logical-- value shifted in is always "0"

arithmetic-- on right shifts, sign extend

msb lsb"0" "0"

msb lsb "0"

Note: these are single bit shifts. A given instruction might request0 to 32 bits to be shifted!

9

MIPS logical instructions

and $1,$2,$3 $1 = $2 & $3

or $1,$2,$3 $1 = $2 | $3

nor $1,$2,$3 $1 = ~($2 |$3)

andi $1,$2,10 $1 = $2 & 10

ori $1,$2,10 $1 = $2 | 10

sll $1,$2,10 $1 = $2 << 10

srl $1,$2,10 $1 = $2 >> 10

sra $1,$2,10 $1 = $2 >> 10

10

A different style

• Make access to small constant fast

– Application

– Profile analysis shows:

• In gcc 52%

• In spice 69%

Of arithmetic instructions involve constants

for(j=0;j<10;j++)

A[j]++;addi $s4,$s4,4

op rs rt immediate

11

A tiny problem

• What if the immediate value is beyond the

range that 16 bits can provide• By the way, what is this range?

lui $s1,5

• What if I want to load 5*216+25 to $s1?

– Who is responsible for doing this?

• MIPS provides $at for such cases

0000 0000 0000 0101 0000 0000 0000 0000$s1

12

American Std Code for Info. Interchange

(ASCII)

13

Load and store bytes

lb $t0,0($sp)

sb $t1,4($sp)

$sp

14

Alignment

• MIPS requires that all words start at addresses that are multiples of 4 bytes

• Called Alignment: objects must fall on address that is multiple of their size. Why do we care?

0 1 2 3

Aligned

NotAligned

15

Endian-ness or Edianess

• Big Endian: Leftmost byte is word address

• Little Endian: Rightmost byte is word address

– .byte 0,1,2,3

msb lsb

3 2 1 0 little endian

Big endian 0 1 2 3

16

MIPS arithmetic instruction format

R-type:

I-Type:

31 25 20 15 5 0

op Rs Rt Rd funct

op Rs Rt Immed 16

Type op funct

ADDI 10 xx

ADDIU 11 xx

SLTI 12 xx

SLTIU 13 xx

ANDI 14 xx

ORI 15 xx

XORI 16 xx

LUI 17 xx

Type op funct

ADD 00 40

ADDU 00 41

SUB 00 42

SUBU 00 43

AND 00 44

OR 00 45

XOR 00 46

NOR 00 47

Type op funct

00 50

00 51

SLT 00 52

SLTU 00 53

17

New instructions

• lbu $t0,0($s0)

• lb $t0,0($s0)

94H

Extension

$s0

94H

$t0

18

Instructions for making decisions

• Conditional/Unconditional branches

beq $s1,$s2, L1

bne $s3,$s4, L2

j L3

• Example

– Compile

Given i: $s1, j: $s2, f: $s3, g: $s4, h: $s5, and k: $s6

if(i == j)

f = g + h – k;

else

f = g + h + k;

19

More examples

• compile

Loop: g += A[i];

i += j;

if(i != h) goto Loop;

20

Compile a while loop

while (save[j] == k)

j += n;

Loop: if(save[j] != k) goto Exit;

j += n;

goto Loop;

Exit:

21

Hierarchical Interpretation of an Application (Executable file)

Executable File

Object Object

procedure procedure

Basic block Basic block

instruction

22

New Instructions

slt $s1,$s2,$s3

if $s2 < $s3

set $s1 to 1

else

set $s1 to 0

jr $s0

jump to the address given by the $s0

23

Branches (Conditional)

• I-Type

bne $s0, $s1, Exit

What seems to be the problem?

5 16 17 Exit

24

PC – Relative addressing

• MIPS adds the content of PC to the immediate field to provide a wider range. Why?

– 50% of conditional branch targets in gcc are smaller than 16 instructions apart from their origin

– bne $s0, $s1, addressPC = (PC + 4) + 4*address

– What is the range of the branching?

– What if you need branch farther than that? We will come back to this shortly.

25

Wrap Up

• MIPS Arithmetic, Load/store and logical instructions

• slt and jr instructions

• Branches and jumps

• pc – relative addressing