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Insulated gate bipolar transistor

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Copyright © by John Wiley & Sons 2003 Insulated Gate Bipolar Transistors (IGBTs) MANGAL DAS M.TECH VST SHIV NADAR UNIVERSITY 1
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Page 1: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Insulated Gate Bipolar Transistors (IGBTs)

MANGAL DASM.TECH

VSTSHIV NADAR UNIVERSITY

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Page 2: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Outline• Why we need IGBT?

• Physical operation

• Construction and I-V characteristics

• SPICE simulation models

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Page 3: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

IGBT

BJT MOSFET*Lower conduction losses*Larger blocking voltage

*Turn Off time*Turn on time small

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Page 4: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Multi-cell Structure of IGBT

• IGBT = insulated gate bipolar transistor.

N +N +N + N +

N-

N+

PP

gate oxide

gate conductor

field oxide

emitter conductor

contact to source diffusion

gate width

P+ collector metallization

buffer layer (not essential)

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Page 5: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Cross-section Of IGBT

• Cell structure similar to power MOSFET cell.

• P-region at collector end unique feature of IGBT compared to MOSFET.

• Punch-through (PT) IGBT - N+ buffer layer present.

• Non-punch-through (NPT) IGBT - N+ buffer layer absent.

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Page 6: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Blocking (Off) State Operation of IGBT

• With N+ buffer layer, junction J 1 has

small breakdownvoltage and thus IGBT has little reverse blocking capability - anti-symmetric IGBT

• Buffer layer speeds up device turn-off

• Blocking state operation - VGE < VGE(th) • Junction J2 extends principally in to n- drift

Region, since the p-type body region is purposely Doped much more heavily than drift region. The thickness of Drift region is large enough to Accommodate the depletion layer. This type of IGBT is called as symmetrical IGBT.

P+

N -

N+

PN

+N

+

emittergate

collector

SiO2

J2

J3

Ls

Parasitic thyristor

Buffer layer (not essential)

J1

- Unique feature of IGBT

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•Vgs<Vth : No inversion layer created

• Depletion layer is created along J2 ,which expands as Vgs increases.

•In ‘NON PUNCH THROUGH’ no buffer layer is present so large reverse voltage

blocking capacity.

•In ‘PUNCH THROUGH ’ buffer layer is present shorter drift region, which lower

on-state losses but reverse voltage blocking capacity will be low.

Drift layer

Buffer layer

Page 7: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

IGBT On-state Operation

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P+

N -

N+

P

N+

N+

emittergate

collector

lateral (spreading) resistance

++ ++ ++ ++

•Vgs>Vth , Channel is shorting Body-Drain-Drift regions.

•P+ inject holes in to N+ region

•Holes moves towards body region along a random path .

•Many holes will attracted by emitter metallization.

•Some holes recombines with electrons.

Page 8: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

• Approximate equivalent circuit for IGBT valid for normal operating conditions.

• IGBT equivalent circuit showing transistors comprising the parasitic thyristor.

Approximate Equivalent Circuits for IGBTs

gate

collector

emitter

Body region spreading resistance

Principal (desired) path of collector current

Conduction path resulting in thyristor turn-on (IGBT latchup) if current in this path is too large

gate

drift region resistance

VJ1Vdrift

I RC channel

• VCE(on) = VJ 1 + Vdrift + IC Rchannel

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Page 9: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

collector

emitter

gate

gate

drain

source

IGBT I-V Characteristics and Circuit Symbols

• Transfer curve

• Output characteristics

• N-channel IGBT circuit symbols

iC

vCE

BVCES

VRM

increasing VGE

• No Buffer Layer

VRM BV CES

• With Buffer Layer

VRM

0

GE3v

GE1v

GE2v

GE4v

iC

vGEV

GE(th)

9

Vth

Page 10: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Development of Spice IGBT Model

P+

N -

N+

P

N+

N+

drain

sourcegate

Coxd

Cgdj

CdsjCcer

Coxs

Cm

Cebj + Cebd

Drain-body or base-collector depletion layer

Rb

• Reference - "An Experimentally Verified IGBT Model Implemented in the SABER Circuit Simulator", Allen R. Hefner, Jr. and Daniel M. Diebolt, IEEE Trans. on Power Electronics, Vol. 9, No. 5, pp. 532-542, (Sept., 1994)

• Nonlinear capacitors Cdsj and Ccer due to N-P junction depletion layer.

• Nonlinear capacitor Cebj + Cebd due to P+N+ junction

• MOSFET and PNP BJT are intrinsic (no parasitics) devices

• Nonlinear resistor Rb due to conductivity modulation of N- drain drift region of MOSFET portion.

• Nonlinear capacitor Cgdj due to depletion region of drain-body junction (N -P junction).

• Circuit model assumes that latchup does not occur and parasitic thyristor does not turn.

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Page 11: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Parameter Estimation for Spice IGBT Model

• Built-in IGBT model requires nine parameter values.

• Parameters described in Help files of Parts utility program.

• Parts utility program guides users through parameter estimation process.

• IGBT specification sheets provided by manufacturer provide sufficient informaiton for general purpose simulations.

• Detailed accurate simulations, for example device dissipation studies, may require the user to carefully characterize the selected IGBTs.

Cm + Coxs

Cgdj

CoxdCdsj

Rb

Cebj + Cebd

Ccer

Drain

Source

Gate

• Built-in model does not model ultrafast IGBTs with buffer layers

(punch-through IGBTs) or reverse free-wheeling diodes.

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Page 12: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

Application

• Current rating of single IGBT can be up to 1200 volts,400Amps.

• Frequency of operation:20Khz.

• It is useful for medium power applications

• Ac and DC motor drives.

• Solid state relays

• High frequency signal choppers.(not preferred)

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Page 13: Insulated gate bipolar transistor

Copyright © by John Wiley & Sons 2003

THANK YOU

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