Integrated Circuits Technology for Physicistskucewicz/download/p1Introduction.pdfAny Book about IC...

W.Kucewicz VLSICirciuit Design 1

Integrated Circuits Technology for

Physicists

Integrated Circuits Integrated Circuits Technology for Technology for

PhysicistsPhysicists


Integrated Circuits Technology for Physicists

Integrated Circuits Technology for Integrated Circuits Technology for PhysicistsPhysicists

ee--mail: mail: kucewiczkucewicz@@iekpiekp..fzkfzk.de.de

http://www.http://www.cyfcyf--krkr..eduedu.pl/~.pl/~gekucewigekucewi//

Wojciech Kucewicz - prof. – Electronics Department

of University of Mining and Metallurgy at Krakow (PL)

Wojciech KucewiczWojciech Kucewicz -- pprofrof. . –– Electronics Department Electronics Department

of University of Mining and Metallurgy at Krakow (PL)of University of Mining and Metallurgy at Krakow (PL)


DELPHI ExperimentDELPHI ExperimentDELPHI Experiment


PHOBOS Experiment at RHIC (BNL)PHOBOS Experiment at RHIC PHOBOS Experiment at RHIC ((BNLBNL))


KANAL ODCZYTOWY P OLACZENIE

LINIE ZAS ILAJACE

REZYSTOR

P IERS CIENIE OCHRONNE

KOMÓRKI

ODCZYTOWE

KOMÓRKI

P OSREDNIE

Pixel Detectors with Interleaved PixelPixel Detectors with Interleaved PixelPixel Detectors with Interleaved Pixel




Contents of the lecture:Contents of the lecture:

1.1. IntroductionIntroduction2.2. CMOSCMOS TechnologyTechnology3.3. MOS TransistorMOS Transistor4.4. Design rulesDesign rules5.5. MOS InverterMOS Inverter6.6. Basic gates Basic gates 7.7. Arithmetic circuitsArithmetic circuits8.8. Latches & MemoriesLatches & Memories9.9. Analog CellsAnalog Cells

May May be be alsoalso::1.1. Noise Parameters in MOS technology. Noise transistor modelNoise Parameters in MOS technology. Noise transistor model2.2. Amplifier for silicon detectors. Preamplifier and shaper. Noise Amplifier for silicon detectors. Preamplifier and shaper. Noise analysisanalysis




Reference Reference BookBookss::Any BookAny Book aboutabout IC Design + LectureIC Design + Lecture

Recommended books:Recommended books:1.1. N.N. WesteWeste and K.and K. EshraghianEshraghian, , Principles ofPrinciples of CMOS VLSICMOS VLSI

DesignDesign, Addison, Addison--Wesley, 1993.Wesley, 1993.2.2. J.J. RabaeyRabaey, , Digital Integrated Circuits A Design Digital Integrated Circuits A Design

PerspectivePerspective, A, A PrenticeHallPrenticeHall 19961996

Analog circuits design:Analog circuits design:1.1. K. K. LakerLaker and and W. W. SansenSansen, , Design of Design of Analog Analog Integrated Integrated

Circuits and SystemsCircuits and Systems, , McGrawMcGraw--HillHill, 199, 19944..




This lecture is based on the books mentioned above and This lecture is based on the books mentioned above and materials on the web pages of: materials on the web pages of: 1. National Institute of Applied Sciences in Toulouse,

http:\\intrage.insa-tlse.fr\~etienne2.2. Pennsylvania State UniversityPennsylvania State University

http://www.http://www.csecse..psupsu..eduedu/~/~cg477cg477//3.3. Ecole Polytechnique FederaleEcole Polytechnique Federale dede LausanneLausanne --

http://http://lsiwwwlsiwww..epflepfl..chch//LSI2001LSI2001/teaching /teaching //webcoursewebcourse/index.html/index.html


Useful links fo VLSI Design Useful links Useful links fo VLSIfo VLSI Design Design qq INSAINSA -- http://www.http://www.insainsa--tlsetlse..frfr//qq EPFLEPFL -- http://http://lsiwwwlsiwww..epflepfl..chch//LSI2001LSI2001/teaching/teaching

//webcoursewebcourse/index.html/index.htmlqq UCUC BerkeleyBerkeley -- http:http:////bwrcbwrc..eecseecs..berkeleyberkeley..eduedu

/People/Faculty//People/Faculty/janjan//qq Pennsylvania State UniversityPennsylvania State University

http://www.http://www.csecse..psupsu..eduedu/~/~cg477cg477//qq EuropracticeEuropractice -- http://www.http://www.europracticeeuropractice.com/.com/qq MOSISMOSIS -- http://www.http://www.mosismosis.org/.org/qq TechOnLineTechOnLine -- http://www.http://www.techonlinetechonline.com/.com/qq SematechSematech -- http://www.http://www.sematechsematech.org/.org/qq IEEEIEEE -- http://www.http://www.ieeeieee.org/.org/qq EMC SocietyEMC Society -- http://www.http://www.emcsemcs.org/.org/qq IEC standardisationIEC standardisation -- http://www.http://www.ieciec..chch//


DDesignesign small fullsmall full--custom circuits in professional way in custom circuits in professional way in one of theone of the submicronsubmicron technologies. Circuits technologies. Circuits has has toto be be verified and analyzed for performance.verified and analyzed for performance.

Design and simulation ofDesign and simulation of CMOSCMOS integrated circuits will integrated circuits will be performed with userbe performed with user--friendly PC tools: friendly PC tools:

Dsch2Dsch2 andand Microwind2Microwind2..

Both programs can be copied from Both programs can be copied from http://http://intrageintrage..insainsa--tlsetlse..frfr/~/~etienneetienne//MicrowindMicrowind/index.html/index.html

Integrated Circuits Technology for Physicists - Exercise

Integrated Circuits Technology for Integrated Circuits Technology for PhysicistsPhysicists -- ExerciseExercise


TheThe Dsch2Dsch2 program is a logic editor and simulator and it program is a logic editor and simulator and it is used to validate the architecture of the logic circuit is used to validate the architecture of the logic circuit before the microelectronics design is started. before the microelectronics design is started.



Dsch2.exe

http://http://intrageintrage..insainsa--tlsetlse..frfr/~/~etienneetienne//MicrowindMicrowind/index.html/index.html

Dsch2cDsch2c




TheThe Microwind2Microwind2 program allows to design and program allows to design and simulate an integrated circuit at physical description simulate an integrated circuit at physical description level. It has build inlevel. It has build in VerilogVerilog Compiler, 2D and 3D Compiler, 2D and 3D process viewprocess view,, what design procedure makes easier to what design procedure makes easier to understand.understand.

Microwind2.exe

http://http://intrageintrage..insainsa--tlsetlse..frfr/~/~etienneetienne//MicrowindMicrowind/index.html/index.html

MicrowindMicrowind


Important !!!Important Important !!!!!!

Lecture in week 271-7 of July

I would like to move it in any other time:

When??...............

Lecture in week 27Lecture in week 2711--7 of July 7 of July

I would like to move I would like to move it it in in any other tany other timeime::

WhenWhen??...............??...............


1.0 Introduction

1.0 1.0 IntroductionIntroduction


ContentsContentsContents

1.1. TransistorTransistor SStorytory2.2. Progress in theProgress in the VLSIVLSI ProductionProduction3.3. Properties of ICProperties of IC4.4. VLSIVLSI Design StylesDesign Styles5.5. Full CustomFull Custom VLSIVLSI Design FlowDesign Flow


Transistor storyTransistor storyTransistor story


Electron Discovery - 1898Electron Discovery Electron Discovery -- 18981898

"To the electron "To the electron -- may it never be of any use to anybody." may it never be of any use to anybody." -- JJJJ. Thomson's favorite toast. Thomson's favorite toast


Mechanical ComputerMechanical ComputerMechanical ComputerThe Babbage Engine, developed in 1834, was perceived as a general-purpose computing machine, with features strikingly close to modern computers. Besides executing the basic operations (addition, subtraction, multiplication, and division) in arbitrary sequences, the machine operated in a two-cycle sequence, called “store” and “mill” (execute), similar to current computers.

Unfortunately, the complexity and the cost of the designs made the concept impractical.For instance, the design of Difference Engine I (part of which is shown) required 25,000 mechanical parts at a total cost of £17,470 (in 1834!).

BabbageBabbage Difference EngineDifference Engine


1945 - First Computer – ENIAC 1945 1945 -- First Computer First Computer –– ENIAC ENIAC

ENIAC ENIAC -- Electronic Numerical Integrator Analyzer and ComputerElectronic Numerical Integrator Analyzer and Computer

Filling up a 30 X 50 foot room,Filling up a 30 X 50 foot room, ENIACENIAC was made of 17, 468 vacuum was made of 17, 468 vacuum tubes,70,000 resistors, and 10,000 capacitors tubes,70,000 resistors, and 10,000 capacitors ---- not to mention all not to mention all those lights and switches.those lights and switches. Most importantly,Most importantly, the metal giant could the metal giant could

add 5,000 numbers in a single second.add 5,000 numbers in a single second.


Bipolar transistor historyBipolar transistor historyBipolar transistor history

qq Transistor Transistor ––BardeenBardeen, Brattain, Brattain (Bell Labs) in 1947(Bell Labs) in 1947

qq Bipolar transistor Bipolar transistor –– SchockleySchockley in 19in 195050

qq First monolithic IC First monolithic IC –– Jack Jack KilbyKilby in 195in 19588

qq First commercial IC logic gates First commercial IC logic gates –– Fairchild 19Fairchild 1959 59

qq TTLTTL –– 1962 into the 1990’s1962 into the 1990’sqq ECLECL –– 1974 into the 1980’s1974 into the 1980’s


The transistor was invented in The transistor was invented in 1947 at Bell Labs by the team of 1947 at Bell Labs by the team of JohnJohn BardeenBardeen, Walter, Walter BrattainBrattain, , and William Shockley, for which and William Shockley, for which they later received the Nobel they later received the Nobel PrizePrize (1956)(1956). .

Bipolar transistor historyBipolar transistor historyBipolar transistor history


Bipolar Transistor HistoryBipolar Transistor HistoryBipolar Transistor History

The first transistor was a germanium The first transistor was a germanium pointpoint--contact transistor consisting of contact transistor consisting of two thin electrodes in pointtwo thin electrodes in point--contact contact with the surface of a piece of with the surface of a piece of germanium and with a third wire germanium and with a third wire attached to the base. attached to the base.

GeGe

EmitterEmitter

BaseBase

CollectorCollector


Bipolar Transistor HistoryBipolar Transistor HistoryBipolar Transistor HistoryJ. Bardeen and W. H. Brattain. The transistor, a semiconductor triode.

Physical Review, 74:230, July 15 1948

Transistor == TransiTransistor == Transientent ReResistorsistor


Bipolar transistorBipolar transistorBipolar transistor

License price 25 k$License price 25 k$


Bipolar Junction Transistor -1950Bipolar Junction Transistor Bipolar Junction Transistor --19501950

EmitterEmitter

BaseBase

CollectorCollector

nn

nn

pp


1958: Invention of the Integrated Circuit

1958: Invention of the Integrated 1958: Invention of the Integrated CircuitCircuit

JackJack KilbyKilby from Texas Instruments.from Texas Instruments.Nobel Price in 2000Nobel Price in 2000







In January of 1959, Robert Noycefrom Fairchild Semiconductor

designed first planar integrated circuit

First commercial IC logic gates First commercial IC logic gates ––Fairchild 1960Fairchild 1960


MOS transistor historyMOS transistor historyMOS transistor history

qq MOSFETMOSFET transistor transistor -- LilienfeldLilienfeld (Canada) in 1925(Canada) in 1925

qq CMOSCMOS –– 1960’s, but plagued with manufacturing1960’s, but plagued with manufacturing problemsproblems

qq PMOS in 1960’s (calculators)PMOS in 1960’s (calculators)

qq NMOS in 1970’s (4004, 8080) NMOS in 1970’s (4004, 8080) –– for speedfor speed

qq CMOSCMOS in 1980’s in 1980’s –– preferred preferred MOSFETMOSFET technologytechnology because because of power benefitsof power benefits

qq BiCMOSBiCMOS


Lilienfeld patentLilienfeld Lilienfeld patentpatent


Microprocessor Intel 4004 (1971)Microprocessor Intel 4004 (1971)Microprocessor Intel 4004 (1971)

2300 transistors2300 transistors on one chipon one chip

FreqFreq. . --108 108 kHzkHz

TechnologyTechnology –– 10m10m

It was 1/8" by 1/16" It was 1/8" by 1/16" andand it was it was as powerful as as powerful as ENIACENIAC

pperformerforminging about 60,000 about 60,000 calculations in a second. calculations in a second.


Microprocesor Intel Pentium 4 (2000)MicroprocesorMicroprocesor Intel Pentium Intel Pentium 44 ((20002000))

42 millions transistors 42 millions transistors on one chipon one chip

Freq. Freq. –– 1.5 GHz1.5 GHz

TechnTechn. . –– 0.180.18µµ

performing billions of calculations each second


Progress in VLSI production

Progress in Progress in VLSI VLSI productionproduction


Moore’s LawMoore’s LawMoore’s Law

Amazingly visionary Amazingly visionary –– million transistor/chip barrier million transistor/chip barrier waswas crossed in the 1980’s.crossed in the 1980’s.

qq 2300 transistors (Intel 4004) 2300 transistors (Intel 4004) -- 19711971

q q 42 Million (Intel P4) 42 Million (Intel P4) -- 20012001

Gordon MooreGordon Moore ((IntelIntel)) predicted that the predicted that the number of transistorsnumber of transistors that can be that can be integrated on a die would growintegrated on a die would grown n

exponentially with time.exponentially with time.


Progress in VLSI productionProgress in Progress in VLSIVLSI productionproduction

Transistors/chip doubles every 1.5 yearsTransistors/chip doubles every 1.5 years

IIIIII

IIII

100M100M

10M10M

1M1M

100k100k

10k10k

1k1k

100100

100100

11

‘’70 ’75 ’80 ‘’70 ’75 ’80 ’85 ’90 ’95 ’85 ’90 ’95 20002000


Evolution of Intel ProcessorEvolution of Intel ProcessorEvolution of Intel Processor

qq Doubling of transistor density every 30 monthsDoubling of transistor density every 30 months

qq Increasing die sizesIncreasing die sizes

Doubling of transistors every 18 months in one dieDoubling of transistors every 18 months in one die


DRAM chip capacity evolutionDRAM chip capacity evolutionDRAM chip capacity evolution

YearYear

Mem

ory

(M

emor

y ( k

Bits

kBits /

chip)

/chip)

Memory/chipMemory/chipddoublesoubles every every

1.5 year1.5 year


Clock frequency trendsClock frequency trendsClock frequency trendsFr

eque

ncy

[MH

z]Fr

eque

ncy

[MH

z]10k10k

1k1k

100100

1010

TechnologyTechnology1.1.55µµm m 1.1.00µµm m 0.0.77µµm m 0.0.55µµm m 0.0.3535µµm m 0.0.2525µµm m 0.0.1818µµm m 0.0.1313µµm m 0.0.11µµmm

FrequencyFrequency doubledoubless eacheachgenerationgeneration


2.0 2.0 µµ

1.0 1.0 µµ

0.3 0.3 µµ

0.2 0.2 µµ

0.10.1 µµ0.050.05 µµ0.030.03 µµ

Technology trendsTechnology trendsTechnology trends

8028680386486

pentiumpentium II

ResearchPentium IV

Production

’85 ’86 ’89 ’92 ’95 ’98 20’85 ’86 ’89 ’92 ’95 ’98 2001 200401 2004


Technology trendsTechnology trendsTechnology trends

Leti1 MOS0.02µm

Dec. 2000


Evolution of Intel ProcessorEvolution of Intel ProcessorEvolution of Intel Processor

Implications: (in the same technology)Implications: (in the same technology)

1. New Arch ~ 21. New Arch ~ 2--33xx die area of the last die area of the last µµArchArch

2. Provides 1.52. Provides 1.5--1.71.7xx integer performance of the last Archinteger performance of the last Arch

3.03.017.8 mm17.8 mmPentium 4Pentium 410.3 mm10.3 mmPentium IIIPentium III0.250.25 µµ

2.12.117.3 mm17.3 mmPentium PROPentium PRO12.2 mm12.2 mmPentiumPentium0.50.5 µµ

3.23.217.0 mm17.0 mmPentiumPentium9.5 mm9.5 mmi486i4860.70.7 µµ

3.13.111.5 mm11.5 mmi486i4866.5 mm6.5 mmi386i3861.01.0 µµ

RatioRatioDie sizeDie sizeNew Architect.New Architect.Die sizeDie sizeOld Architect.Old Architect.TechnolTechnol..


Technology InfluenceTechnology InfluenceTechnology Influence

0.18 µm0.5 µml

2000 20011995

3 layers 7 layers 8 layers

120MHz 500MHz

0.12µm

1200 MHz

Devices

Interconnects

Frequency


Technology progress Technology progress Technology progress

q 0.7µm, 2 metal layers q Up to 100,000 devices on a chipq CPU frequency 50MHz

q 0.12µm, 7 metalq Up to 100,000,000 devicesq CPU frequency 1,5GHz

19911991 20012001

IC1000 pins1000 pins

40 pins40 pins 10 years of evolution

10 years of 10 years of evolutionevolution


Technology DirectionsTechnology DirectionsTechnology Directions

2.42.22.02.42.01.4Battery power [W]

18317417018013090Power [W]

0.60.60.81.21.51.8Power supp [V]

109-1098-97-86-7Wiring levels

14721408128010241024768Signal pins/chip

354308269235170-214170Chip size [mm2]

7012841154714-267Mtrans/cm2

355070100130180Feature size [nm]

201420112008200520021999Year


Moore’s Law Predictions – 2025?Moore’s Moore’s Law Law PredictionsPredictions –– 2025?2025?Assumptions in 1995 based on 1960Assumptions in 1995 based on 1960--1995 1995

qq Transistors per chip doubles every 1.5 years Transistors per chip doubles every 1.5 years qq Minimum feature size is cut in half every six years Minimum feature size is cut in half every six years qq Chip area goes up 2.3 times every six years Chip area goes up 2.3 times every six years qq Manufacturing costs remain about constant Manufacturing costs remain about constant

This leads us to the following predictions (will they come true?!)

qWafer size will be 32 inches!32 inches!q A wafer fabrication will cost a tens of G$ q The chips will be 3 by 6 inches3 by 6 inchesq T he minimum feature size will be 100 Angstroms100 Angstroms(which is about 5 photoresist molecules wide) q A Memory chip will hold 6464 TERATERA bitsbits


Major Design ChallengesMajor Design ChallengesMajor Design ChallengesqqMicroscopic issuesMicroscopic issues•• ultraultra--high speedshigh speeds•• power dissipation andpower dissipation and supply rail dropsupply rail drop•• growing importance ofgrowing importance of interconnectinterconnect•• noise, noise, crosstalkcrosstalk•• reliability,reliability, manufacturabilitymanufacturability•• clock distributionclock distribution

qqMacroscopic issuesMacroscopic issues•• timetime--toto--marketmarket•• design complexitydesign complexity (millions of gates)(millions of gates)•• systems on a chip (systems on a chip (SoCSoC))


Properties of ICProperties of ICProperties of IC


Properties of ICProperties Properties of ICof IC

Basic properties of a digital design help to quantify the quality of a design from different perspectives:

q Cost,

q Functionality

q Performance

q Energy consumption.


Cost of ICCost Cost of ICof IC

CostCost perper IC IC = = ++ Variable costVariable costVolumeVolume

Fixed costFixed cost

The fixed costThe fixed cost is independent of the sales volume, the number of is independent of the sales volume, the number of products sold. An important component of the fixed cost of an products sold. An important component of the fixed cost of an integrated circuit is the effort in time and manintegrated circuit is the effort in time and man--power it takes to power it takes to produce the design.produce the design.

The variable costThe variable cost accounts for the cost that is directly attributable accounts for the cost that is directly attributable to a manufactured product, and is hence proportional to the prodto a manufactured product, and is hence proportional to the product uct volume. Variable costs include the costs of the parts used in thvolume. Variable costs include the costs of the parts used in the e product, assembly costs, and testing costs.product, assembly costs, and testing costs.



360 M $800130 M Tr.0.132002

160 M $36032 M Tr.0.181999

120 M $27020 M Tr.0.251998

90 M $21013 M Tr.0.351997

Staff Cost

3 year Design Staff SizeComplexityTechn.Year

Design cost is strongly influenced by the complexity of the desiDesign cost is strongly influenced by the complexity of the design, the gn, the aggressiveness of the specifications, and the productivity of thaggressiveness of the specifications, and the productivity of the designer. e designer.

Bringing down the design cost in the presence of an everBringing down the design cost in the presence of an ever--increasing IC increasing IC complexity is one of the major challenges that is always facing complexity is one of the major challenges that is always facing the the

semiconductor industry.semiconductor industry.



Variable costVariable cost ==

diedie

final yieldfinal yieldcost cost of of diedie + test ++ test + packagingpackaging



Cost Cost of of diedie ==diesdies perper waferwafer xx die yielddie yield

cost cost of of waferwafer

Dies Dies per per waferwafer ((ππRR22) ) = = --Die areaDie area

π π x Rx R22 2π 2π x Rx RDie diagonalDie diagonal



Die yieldDie yield = = ((1 +1 + ) ) αα is a parameter that depends

upon the complexity of the manufacturing process, and isroughly proportional to the number of masks. αα = 3= 3 is a good estimate for today’s complex CMOS processes.

0,00

0,20

0,40

0,60

0,80

1,00

0,5 1 1,5 2 2,5 3 3,5 4 4,5

Die area [sqcm]

Yields 2 defects /s qcm

1 defect/sqcm

0,5 defects /s qcm

αα

defectsdefects perper unit areaunit area xx die areadie area −−αα

Yield strongly decrease with size Yield strongly decrease with size of chipof chip

Cost Cost of of diedie = = f(f(die areadie area))44



Cost Cost of of diedie = = f f ((die areadie area))44

The area is a function that is directly controllable by the desiThe area is a function that is directly controllable by the designer(s), gner(s), and is the prime metric for cost.and is the prime metric for cost.

The smaller circuit:The smaller circuit:qq the higher the integration density and the smaller the die sizethe higher the integration density and the smaller the die sizeqqmore tend to be faster and consume less energy, as the total more tend to be faster and consume less energy, as the total capacitancecapacitance——which is one of the dominant performance parameterswhich is one of the dominant performance parameters——often scales with the area.often scales with the area.


FunctionalityFunctionalityFunctionality

A prime requirement for a digital circuit is, obviously, A prime requirement for a digital circuit is, obviously, that it performs the function it isthat it performs the function it is designed for.designed for.

Manufactured circuit normally deviates from the expected response. Reasons for this aberration are two:

1. The variations in the manufacturing process; dimensions, threshold voltages, and currents of an MOS transistor vary between runs or even on a single wafer or die.

2. The presence of disturbing noise sources on or off the chip is another source of deviations in circuit response.


FunctionalityFunctionalitFunctionalityy

Noise in digital circuitsNoise in digital circuits

Capacitive and inductive cross talk:

Can influence signal on the neighboring strips

Supply fluctuation:

Can influence signal levels in the circuit


FunctionalityFunctionalityFunctionality

Noise in digital circuits vsNoise in digital circuits vs. . TechnologyTechnology

Noise margins definitionNoise margins definition

Pulse SignalPulse Signal


PerformancePerformancePerformance

The performance of a digital circuit expresses the computational load that the circuit can manage.

For instance, a microprocessor is often characterized by the number of instructions it can execute per second.

When focusing on the pure design, performance is most often expressed by the duration of the clock period (clock cycle time), or its rate (clock frequency).The minimum value of the clock period for a given technology and design is set by a number of factors such as:• the time it takes for the signals to propagate through the logic,• the time it takes to get the data in and out of the registers, • the uncertainty of the clock arrival times.


Propagation delay tpPropagation delay tPropagation delay tpp

VVinin

VVoutout

ttfallfall ttriserise

ttpHLpHL ttpLHpLH

22ttpp = =

ttpHLpHL + + ttpLHpLH


Propagation delay measurementPropagation delay measurementPropagation delay measurement

The standard circuit forThe standard circuit for delay measurement is the delay measurement is the ring oscillatoring oscillator, which r, which consists of an odd number of invertersconsists of an odd number of inverters connected in a circular chainconnected in a circular chain..

T = 2 T = 2 •• ttpp •• NN


Power consumptionPower consumptionPower consumption

The power consumption of a design determines how much The power consumption of a design determines how much energy is consumed per operation,energy is consumed per operation, and much heat the and much heat the circuit dissipates. circuit dissipates.

These factors influence a great number of criticalThese factors influence a great number of critical design design decisions, such asdecisions, such as::qq the powerthe power--supply capacity, supply capacity, qq the battery lifetime, the battery lifetime, qq supplysupply--lineline sizing,sizing,qq packaging and cooling requirements.packaging and cooling requirements.


Design Abstraction LevelsDesign Abstraction LevelsDesign Abstraction Levels

Circuit is constructedin a hierarchical way: a system is a collection of modules, each of which consists of a number of cells on its own. Cells are reused as much as possible to reduce the design effortand to enhance the chances for a first-time-right implementation.


7hAdder

VLSI Design Styles

VLSIVLSI Design Design StylesStyles


VLSI Design StylesVLSIVLSI Design StylesDesign Styles

Field Programmable Gate Array Design

Field Programmable Field Programmable Gate Array DesignGate Array Design

Gate Array DesignGate Array DesignGate Array Design

Standard Cells Based DesignStandard Cells Based DesignStandard Cells Based Design

Full Custom DesignFull Custom DesignFull Custom Design

Each design style has its own Each design style has its own merits and shortcomings, and merits and shortcomings, and thus thus a proper choice has to be a proper choice has to be made by designersmade by designers in order to in order to provide the functionality at low provide the functionality at low costcost


Field Programmable Gate Array Design (FPGA)

Field Programmable Gate Array Field Programmable Gate Array Design (FPGA)Design (FPGA)

Fully fabricated FPGA chips containing thousands of logic gates or even more, with programmable interconnects.

Users realize desired functionality by custom hardware programming




A typical FPGA chip consists of • I/O buffers, • an array of configurable logic blocks (CLBs), • programmable interconnect structures.




The programming of the interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors.

CLBCLB

CLBCLB

CLBCLB

CLBCLB

CLBCLB CLBCLB

CLBCLB CLBCLB


FPGA - configurable logic block (CLB)FPGAFPGA -- configurable logic block (configurable logic block (CLBCLB))

CLB consists of • four signal input terminals (A, B, C, D),• a clock signal terminal, • user-programmable multiplexers, • an SR-latch, • a look-up table (LUT).




AdvantagesAdvantages•• fast prototypingfast prototyping•• low volume applicationlow volume application•• reconfigurable, can be programmed an unlimited number of times •• very short turnvery short turn--around timearound time

DisadvantagesDisadvantages•• chip area only partially usedchip area only partially used•• relatively high power consumptionrelatively high power consumption•• long interconnection lineslong interconnection lines•• quite expensive quite expensive


Gate Array (GA)Gate Array (GA)Gate Array (GA)

Gate array implementation requires a two-step manufacturing process: • The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. • Chips can be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array.


Gate Array ChipGate Array Gate Array ChipChip

Gate array chip contains:• bonding pads,• diodes for I/O protection, nMOS and pMOS transistors for chip output driver circuits in the neighboring areas of bonding pads, • arrays of nMOS and pMOS transistors, • power and ground buses along with contact windows


Gate ArrayGate ArrayGate ArrayAdvantagesAdvantages•• quite fast prototyping quite fast prototyping (but slower than FPGA)(but slower than FPGA)•• low volume applicationlow volume application•• short turnshort turn--around time around time (but longer than FPGA)(but longer than FPGA)

DisadvantagesDisadvantages•• chip area only partially used chip area only partially used (but better than FPGA)(but better than FPGA)•• relatively high power consumptionrelatively high power consumption•• long interconnection lineslong interconnection lines•• notnot reconfigurablereconfigurable•• quite expensive quite expensive


Standard CellsStandard CellsStandard Cells

The standard-cells based design is one of the most prevalent full custom design styles which require development of a full custom mask set. In this design style, all of the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates,, D-latches, and flip-flops.



To enable automated placement of the cells and routing of inter-cell connections, each cell layout is designed with a fixed height, so that a number of cells can be abutted side-by-side to form rows. The power and ground rails typically run parallel to the upper and lower boundaries of the cell, thus, neighboring cells share a common power and ground bus



Inside the I/O frame which is reserved for I/O cells, the chip area contains rows or columns of standard cells. Between cell rows are channels for dedicated inter-

cell routing.



A common signal bus structure can also be incorporated into the

standard-cell-based chip layout.


Standard CellsStandard CellsStandard CellsAdvantagesAdvantages•• chip area nearly fully used chip area nearly fully used •• faster faster (shorter interconnections) (shorter interconnections) •• power consumption adequate to the circuit functionpower consumption adequate to the circuit function•• cheap in the long seriescheap in the long series

DisadvantagesDisadvantages•• longer prototyping longer prototyping •• expensive designexpensive design


Full CustomFull CustomFull CustomAdvantagesAdvantages•• chip area fully used chip area fully used •• faster faster (shorter interconnections) (shorter interconnections) •• power consumption adequate to the circuit functionpower consumption adequate to the circuit function•• cheap in the long series cheap in the long series (for example memories)(for example memories)

DisadvantagesDisadvantages•• very long prototyping very long prototyping •• very expensive development very expensive development


7hAdder

VLSI Design FlowFull Custom

VLSIVLSI Design FlowDesign FlowFull CustomFull Custom


VLSI Design FlowVLSIVLSI Design FlowDesign Flow

System IdeaSystem IdeaSystem Idea

Identifying SubBlocksIdentifyingIdentifying SubBlocksSubBlocks

Bottom-Up full customBottomBottom--Up full customUp full custom


VLSI Design Flow (Full Custom)VLSIVLSI Design Flow (Full Custom)Design Flow (Full Custom)

Sub-block SchematicSubSub--block Schematicblock Schematic

Transistor Level SimulationTransistor Level SimulationTransistor Level Simulation

LayoutLayoutLayout

ExtractionExtractionExtraction

Layout vs.Schematic CheckLayout vs.Schematic CheckLayout vs.Schematic Check

Post Layout SimulationPost Layout SimulationPost Layout Simulation


VLSI Design FlowVLSIVLSI Design FlowDesign Flow

PrototypingPrototypingPrototyping

Tape outTape outTape out

Placement and routingPlacement and routingPlacement and routing

TestsTestsTests

FabrificationFabrificationFabrification

Top Level VerificationTop Level VerificationTop Level Verification


ReferenceReferenceReference

BooksBooks::qqM.M. AnnaratoneAnnaratone, , DigitalDigital CMOSCMOS Circuit DesigCircuit Design,n, KluwerKluwer, 1986., 1986.qqT.T. DillingerDillinger,, VLSIVLSI EngineerinEngineering, Prentice Hall, 1988.g, Prentice Hall, 1988.qqE.E. ElmasryElmasry, ed., , ed., Digital MOS Integrated CircuitDigital MOS Integrated Circuits, IEEE Press, 1981.s, IEEE Press, 1981.qqE.E. ElmasryElmasry, ed., , ed., Digital MOS Integrated Circuits IDigital MOS Integrated Circuits II, IEEE Press, 1992.I, IEEE Press, 1992.qqL.L. GlasserGlasser and D.and D. DopperpuhlDopperpuhl, , The Design and Analysis ofThe Design and Analysis of VLSIVLSI CircuitCircuits, s, AddisonAddison--Wesley, 1985.Wesley, 1985.qqA. Kang andA. Kang and LeblebiciLeblebici,, CMOSCMOS Digital Integrated CircuitDigital Integrated Circuits, 2nd Ed., McGraws, 2nd Ed., McGraw--Hill, 1999.Hill, 1999.qqC. Mead and L. Conway, C. Mead and L. Conway, Introduction toIntroduction to VLSIVLSI SystemSystems, Addisons, Addison--Wesley, 1980.Wesley, 1980.qqK. Martin, K. Martin, Digital Integrated Circuit DesigDigital Integrated Circuit Design, Oxford University Press, 2000.n, Oxford University Press, 2000.qqD.D. PucknellPucknell and K.and K. EshraghianEshraghian, , BasicBasic VLSIVLSI DesigDesign, Prentice Hall, 1988.n, Prentice Hall, 1988.qqM. Shoji,M. Shoji, CMOSCMOS Digital Circuit TechnologDigital Circuit Technology, Prentice Hall, 1988.y, Prentice Hall, 1988.qqJ.J. UyemuraUyemura, , Circuit Design forCircuit Design for CMOS VLSCMOS VLSII,, KluwerKluwer, 1992., 1992.qqH.H. VeendrickVeendrick, , MOS IC’s: From Basics to ASICMOS IC’s: From Basics to ASICS,S, VCHVCH, 1992., 1992.qWeste and Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1985, 1993.

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